37 results about "Processor scheduling" patented technology

The embodiment of the invention provides a physical machine processor scheduling method, device, system, product and storage medium, the physical machine comprises a physical processor, the physical processor corresponds to a scheduling queue, the method comprises the following steps: switching a running host machine operating system from a root mode to a virtualization mode, and in the virtualization mode, the host machine operating system is switched to a virtual mode; creating at least one virtual processor; generating a scheduling object and adding the scheduling object to a scheduling queue of the physical processor; and in a process of selecting a running task for the physical processor based on the scheduling queue of the physical processor, if the scheduling object is selected, selecting a target virtual processor from the at least one virtual processor, and scheduling the physical processor to run the target virtual processor.

The invention discloses a scheduling method, a graphics processor, a scheduling device, a chip and equipment, and belongs to the field of chips. The scheduling method is executed by the GPU, the GPU at least comprises Y scheduling units, and each scheduling unit comprises a core or a processing unit. One core comprises at least one processing unit; the method comprises the following steps: recording an xth scheduling unit which is finally scheduled during nth scheduling; wherein the scheduling granularity of the nth scheduling is a working group or a working item, and one working group comprises a plurality of working items; in the (n + 1) th scheduling, scheduling is started from the (x + 1) th scheduling unit, so that polling scheduling in the Y scheduling units is realized; wherein the scheduling granularity of the (n + 1) th scheduling is a working group or a working item; n is a positive integer, and x is a positive integer smaller than or equal to Y. When multiple times of scheduling are executed, different scheduling units are cyclically executed for the first scheduling granularity, and therefore load balancing of the multiple scheduling units can be achieved for multiple times of scheduling.

The processing system (100) includes a scheduling mechanism for generating data for fine-grained reordering of workgroups of kernels to generate data blocks, such as for communication across devices to enable overlap of AllReduce communication and producer computations over a network. This scheduling mechanism enables a first parallel processor (702) to schedule and execute a set of workgroups of producer operations to generate data for transmission to a second parallel processor (704) in a desired traffic pattern. Concurrently, the second parallel processor schedules and executes a different set of workgroups of producer operations to generate data for transmission in a desired traffic pattern to a third parallel processor (706) or back to the first parallel processor.

The invention discloses a resource optimization method and system for decision making of a main processor and scheduling in an audio processor. The method comprises the following steps: acquiring processor load information when the audio processor performs audio processing on multiple audio input channels and channel feature information of each audio input channel; when the processor load information meets a preset load condition, the main processor determines an adjustment result of audio processing configuration according to a preset resource optimization rule based on the processor load information and the channel feature information; the main processor generates and sends a control instruction to the audio processor according to the adjustment result; and the audio processor updates the sound mixing routing relationship in the internal scheduling according to the control instruction, and carries out switching or intensity adjustment on the processing link of each channel according to the processing algorithm configuration. According to the technical scheme, the continuity and the stability of conference audio processing are improved on the premise of not changing a hardware structure.

The invention discloses a task scheduling system and chip, and relates to the technical field of computer processor scheduling, and the system comprises a resource monitor which is used for monitoring an original resource state of a processor and preprocessing the original resource state to obtain a target resource state; the task analyzer is used for analyzing the to-be-processed task to obtain an original task feature of the to-be-processed task, and preprocessing the original task feature to obtain a target task feature; the scheduling decision maker is used for processing the target resource state and the target task feature according to a reinforcement learning model to obtain a scheduling result of the to-be-processed task; and the task distributor is used for distributing the to-be-processed task to the processor according to the scheduling result. Task scheduling is carried out on the processor by means of hardware according to the reinforcement learning model, and the real-time performance of task scheduling can be guaranteed through the resource monitor; the preprocessing ensures the efficiency and accuracy of subsequent data processing; task scheduling can be performed in real time with high efficiency and high accuracy.

The invention discloses an AI data handling optimization method based on a multi-core system. The data handling optimization method comprises the steps that S1, initialization is carried out; s2, asynchronous request; s3, asynchronous processing; and S4, parallel execution. The processor A for executing the AI operation is always in the user state and does not need to fall into the kernel state, so that the system calling overhead is avoided; in the process that the processor A executes the AI operation, the processor B schedules DMA hardware to complete transmission processing of next data required by the AI reasoning operation, the DMA hardware and the AI reasoning operation are completely parallel, and when DMA transmission time is shorter than AI reasoning operation time, time overhead of DMA data transmission is completely masked; based on the software and hardware collaboration framework, the utilization rate of the computing part of the processor A can be close to 100%.

The invention relates to the technical field of processor scheduling, and discloses a scheduling circuit and equipment, and the scheduling circuit comprises a scheduling tree control unit and a scheduling tree; the scheduling tree comprises scheduling nodes; the scheduling nodes comprise tree root nodes located at the bottommost layer, middle nodes located at the middle layer and leaf nodes located at the topmost layer; the scheduling nodes are cascaded through a scheduling tree control unit; the tree root node, the intermediate node and the leaf node respectively comprise at least one authorization scheduler; the leaf nodes are used for receiving requests of request sources; and the scheduling tree control unit is used for selecting an authorization result from the request of the request source received by the leaf node according to the authorization request of the scheduling node. According to the scheme, the task scheduling waiting time is greatly shortened, and the scheduling efficiency of the scheduling circuit is improved.

An information handling system includes a BMC and a processor. The processor provides a guest operating stack and a Realm operating stack. The processor further launches a Realm on the Realm operating stack and loads an application on the Realm. The processor instantiates a Realm management monitor (RMM) on the Realm operating stack. The RMM provides a Realm initial measurement (RIM) for the Realm, generates a Realm attestation token based on the RIM, and provides the Realm attestation token to the BMC. The RIM includes information to identify the application. The BMC determines whether the application is authenticated by a certificate authority based on the Realm attestation token and directs the processor to schedule execution of the Realm when the application is authenticated by the certificate authority.

The invention discloses a computing power server load distribution method and system based on structure perception, and relates to the technical field of multi-core processor scheduling processing. According to the method, task core structure information is collected in real time, task types are determined, three types of structure conflict indexes including a cache conflict index, a power consumption interference factor and an execution unit overlapping degree are calculated, a structure conflict matrix is constructed, a matrix spectrum balance method is adopted to realize load distribution, and hidden conflicts are converted into computable numerical values; local optimization deviation is avoided, the cache hit rate is improved, task delay and performance fluctuation are reduced, the core temperature peak value and power consumption waste are reduced, and collaborative optimization of performance, stability and energy consumption efficiency of the multi-core CPU computing power server is achieved.

The application relates to the technical field of processor scheduling, and discloses a scheduling circuit and equipment, the scheduling circuit comprising a scheduling tree control unit and a scheduling tree; the scheduling tree comprises scheduling nodes; the scheduling nodes comprise tree root nodes located at the bottom layer, intermediate nodes located at the middle layer, and leaf nodes located at the highest layer; the scheduling nodes are cascaded through the scheduling tree control unit; the tree root nodes, the intermediate nodes, and the leaf nodes each comprise at least one authorized scheduler; the leaf nodes are used for receiving requests from request sources; and the scheduling tree control unit is used for selecting an authorized result from the requests received by the leaf nodes from the request sources according to authorized requests of the scheduling nodes. The above scheme greatly shortens the task waiting scheduling time and improves the scheduling efficiency of the scheduling circuit.

Embodiments of the present disclosure provide a processor scheduling method for a physical machine, a device, a system, a product, and a storage medium. The physical machine comprises a physical processor, and the physical processor has a corresponding scheduling queue. The method comprises: switching a running host operating system from a root mode to a virtualization mode, and creating at least one virtual processor in the virtualization mode; generating a scheduling object and adding same to the scheduling queue of the physical processor; and in the process of selecting a running task for the physical processor on the basis of the scheduling queue of the physical processor, if the scheduling object is selected, selecting a target virtual processor from the at least one virtual processor, and scheduling the physical processor to run the target virtual processor.

A resource scheduling method, a job processing method, a scheduler, a system, and a related device are related, and relates to the field of computer technologies. The scheduler obtains a to-be-processed first job; determines, based on a computing power topology, a plurality of first processors from a plurality of processors included in a resource pool, where the computing power topology indicates computing powers of the plurality of processors, and a difference between computing powers of the plurality of first processors does not exceed a threshold; and schedules the plurality of first processors for the first job, where the first job is executed in parallel based on the plurality of first processors. The difference between the computing powers of the plurality of first processors scheduled for the first job does not exceed the threshold.

This application discloses a processor scheduling method, apparatus, electronic device, and storage medium. The processor scheduling method is applied to an electronic device. The processor of the electronic device includes a first processor core and a second processor core, which share a common power domain. The processing power of the first processor core is higher than that of the second processor core. The processor scheduling method includes: if the first processor core meets the conditions corresponding to an idle state and the second processor core is in an operating state, obtaining the current operating frequency of the first processor core as a first frequency; obtaining the operating frequency of the second processor core as a second frequency; if the voltage corresponding to the first frequency is greater than the voltage corresponding to the second frequency, adjusting the operating frequency of the first processor core to a third frequency, wherein the voltage corresponding to the third frequency is less than the voltage corresponding to the second frequency. This method can reduce the power consumption of the electronic device.

A method of scheduling a naphtha decomposition center by at least one processor of the present invention may comprise the steps of: acquiring input information; determining storage tank information by using a first agent according to the input information; using a second intelligent agent to determine mixing tank combination information; and determining decomposition furnace starting information by using the third agent.

The invention discloses a real-time multiprocessor scheduling method based on boundary proportional fair optimization, aims to solve the problems of high context switching overhead and implementation complexity of a PFair algorithm in a multiprocessor environment, and aims to optimize a core mechanism of a PD2 algorithm, including reconstruction of a priority tuple and introduction of an intelligent early release rule. The idle time of the processor is obviously reduced by 19%; meanwhile, the system is integrated into a SchedCAT framework, a red-black tree is used for managing a subtask queue to achieve efficient scheduling, a quantum scheduler controls time jitter within 5 microseconds, and the migration cost is reduced in combination with a cache sensing strategy; through comprehensive verification of x86 and ARM platforms, under the harsh condition that the utilization rate of a processor reaches 100%, the context switching overhead is reduced by 18-22%, 32-256 task high-load scenes are supported, the real-time performance is ensured to be stable, the method is suitable for the high-requirement fields such as an automatic driving control module and an industrial real-time system, and finally industrial application landing is promoted through open source implementation (SchedCAT v2.3).

Apparatuses, systems, and techniques to allocate processors to be used by software. In at least one embodiment, one or more of a group of processors used to perform a software program are prevented from being allocated to perform a second software program until at least an expiration of an amount of time.

An information handling system includes a BMC and a processor. The processor provides a guest operating stack and a Realm operating stack. The processor further launches a Realm on the Realm operating stack and loads an application on the Realm. The processor instantiates a Realm management monitor (RMM) on the Realm operating stack. The RMM provides a Realm initial measurement (RIM) for the Realm, generates a Realm attestation token based on the RIM, and provides the Realm attestation token to the BMC. The RIM includes information to identify the application. The BMC determines whether the application is authenticated by a certificate authority based on the Realm attestation token and directs the processor to schedule execution of the Realm when the application is authenticated by the certificate authority.

The application discloses a processor scheduling method and device, and belongs to the technical field of electronic equipment. The method comprises the following steps: obtaining the job cycles of a plurality of tasks to be scheduled; determining the load evaluation window duration corresponding to each task according to the job cycles; taking the load evaluation window duration as a statistical period, respectively performing load statistics on the tasks with the same load evaluation window duration to obtain the aggregated load values corresponding to each load evaluation window duration; and determining the target working frequency of a processor according to the aggregated load values corresponding to all load evaluation window durations.

The invention provides a power system dynamic reconfigurable processor heterogeneous execution body scheduling method and system, and relates to the technical field of network communication and information security. Comprising the following steps: for a dynamic reconfigurable processor in a power system, scheduling each heterogeneous execution body in the dynamic reconfigurable processor to execute a target program and extracting behavior track characteristics in an execution process of each heterogeneous execution body; identifying potential abnormal executors on the basis of deviations between behavior track characteristics of the heterogeneous executors and behavior track characteristics of other heterogeneous executors; determining an abnormal executor based on the identification result of the potential abnormal executor and the execution result of each heterogeneous executor for the target program; and controlling the abnormal execution body to perform cleaning recovery operation until the abnormal execution body recovers to a normal state, and rescheduling the abnormal execution body in the normal state to participate in execution decision of the dynamic reconfigurable processor. The problem that safe and stable operation of an electric power system is affected due to high complexity of an existing electric power system mimicry defense processing process is solved.

The invention discloses a dynamic task scheduling method and device for a power grid complex stability control model, and the method comprises the steps: converting a task scheduling problem into a directed acyclic graph, enabling nodes to represent scheduling tasks, enabling edges to represent the scheduling relation between the scheduling tasks, enabling a path to represent a processor scheduling sequence, and enabling high and low priority scheduling tasks to be alternately executed in the scheduling sequence, resource and dependency constraints are met; a task scheduling process is converted into a Markov decision process, a state space is composed of a task state vector and a processor resource vector, an action space is an allocation pair meeting constraints between a scheduling task and a processor, and a reward function is composed of a weighted combination of completion time and a load balancing ratio; a task scheduling strategy is generated through an encoder-decoder neural network, an encoder generates scheduling task final embedding and overall graph embedding through a two-stage multi-head attention mechanism, and a decoder combines mask processing to generate a feasible task scheduling strategy. The task scheduling efficiency, accuracy and resource utilization rate can be improved.

Devices, systems, and methods for allocating processors used by software are disclosed. In at least one embodiment, it is prevented that one or more processors of a group of processors used to execute a software program are assigned to execute a second software program until at least a certain period of time has elapsed.

This application relates to the field of multi-core processor scheduling technology, specifically a task scheduling method, system, and computer-readable storage medium. The method includes: adding a target task to a task ready queue when the task status of the target task meets the task scheduling conditions; obtaining the scheduling record information and first priority of the target task, the scheduling record information including the kernel release time of the target task for the first kernel and the queue addition time of the target task to the task ready queue; if the kernel release time and the queue addition time meet a time threshold condition, obtaining the second priority of the currently executing task on the first kernel; if the first priority is higher than the second priority, scheduling the target task to run on the first kernel. This application considers both priority and timeliness on the first kernel, and prioritizes the execution of the target task on the first kernel, which ensures the convenience of obtaining the target task's running data and improves the execution efficiency of the system task scheduling.

A computer-implemented method schedules a plurality of tasks for execution by a multi-processor system. A first schedule is generated that assigns each task of the plurality of tasks a time window and a processor of the multi-processor system. A contention model for the multi-processor system is queried to determine a contention delay for the assignment of tasks to processors according to the first schedule. The contention delay determined from the contention model is used to generate, from the first schedule, a revised schedule that assigns each task a time window and a processor of the multi-processor system, wherein the revised schedule is determined in dependence on the determined contention delay.

The embodiment of the invention provides a physical machine processor scheduling method, device, system, product and storage medium, the physical machine comprises a physical processor, the physical processor is bound with a target process, and the method comprises the following steps: switching a running host machine operating system from a root mode to a virtualization mode, creating a virtual processor where the target process is located and a new virtual processor in the virtualization mode; obtaining idle time information, wherein the idle time information represents idle time when the target process is in an idle state; and based on the idle time information, quitting the virtual processor where the target process in the idle state is located from the physical processor, and scheduling the physical processor to run the new virtual processor.

According to the key scanning detection device and the contactless electronic trigger type keyboard, the multiple multiplexers and the multiple analog-to-digital converters are controlled to be started through the DMA controller, a connected keyboard matrix is scanned through a full-hardware chain type scanning method, scheduling intervention of a CPU processor is not needed, CPU loads and signal delay time are effectively reduced, and the operation efficiency is improved. Therefore, the key response delay is reduced, and the key scanning frequency is improved; moreover, each task node is automatically triggered through a plurality of timers, high-precision synchronization of each task node can be realized, and the keyboard matrix is ensured to be compulsively scanned in a preset cycle period, so that the key event reporting delay is effectively avoided, the key event reporting moment jitter is avoided, and the user experience is improved. The technical problems that an existing key scanning detection method is too high in CPU load, limited in key scanning frequency, remarkable in key response delay and too large in jitter when a key event is reported are solved.

The application relates to a multi-processor system and a method thereof, an electronic device, a storage medium and a program product. The multi-processor system comprises a scheduler and at least one processor comprising a resource manager. The scheduler is configured to, in response to a logical instance allocation request from an application program, acquire a target processor satisfying the logical instance allocation request according to available hardware resources of each processor in the multi-processor system, and send the logical instance allocation request to a resource manager in the target processor; the logical instance allocation request comprises a priority, a minimum resource requirement and a maximum resource requirement of a logical instance; and the resource manager is configured to allocate an appropriate logical instance for the application program in response to the logical instance allocation request, and dynamically adjust the allocation of hardware resources among a plurality of logical instances according to a preset strategy to preferentially meet the maximum resource requirement of a logical instance with a high priority. The application can improve the resource utilization rate of the processor in the multi-processor system.

A hardware device is communicatively connected to host servers individually supporting a virtual switch and one or more virtual machines and includes a processor input to receive a header of a data packet in the hardware device, a hardware rules processor scheduler to schedule processing of the header among hardware processing cores in the hardware rules processor, a rules processor core scheduled by the hardware rules processor scheduler to receive the header from the hardware rules processor scheduler, the rules processor core to read compiled networking policies from the memory, and to apply the compiled networking policies to the header to yield a modified header for the data packet, and a connection establishment processor to record the networking connection for the data packet based on the modified header in an established connection datastore.

The invention discloses an SIMD architecture-oriented neural network processor intra-core scheduling method and system, and belongs to the technical field of processor scheduling. Through a three-level screening mechanism of the node type priority, the time window priority and the memory influence degree priority, in combination with dependency constraint processing and L0 cache mutual exclusion constraint management, a scheduling sequence which meets a topological sequence and has the minimum peak cache residence amount is generated, idle computing power in a chip is effectively utilized, and the resource utilization rate is improved. On the basis, cache allocation and swap-in and swap-out operation are optimized based on a cost-aware strategy, an optimized scheduling sequence containing swap-in and swap-out operation nodes is generated, swap-in and swap-out memory minimization is achieved, and the scheduling efficiency and the resource utilization rate are further improved. In addition, the method further optimizes the swap-in and swap-out position, and further reduces the total operation time of the operator on the premise of ensuring that the data carrying amount except the total amount is not obviously increased.

The application discloses a heterogeneous processor scheduling method based on federal scheduling, which firstly acquires the running features of multiple tasks running on a heterogeneous processor platform in a real-time system and the workloads of each processor, analyzes the tasks by using a DAG task model to obtain the deadlines of each task, then acquires the running speed of each task on each processor in the heterogeneous processor platform according to the deadline of each task, and subsequently evaluates each processor according to the running speed of each task on the processor to obtain the preference degree of different types of processors to all tasks on the heterogeneous processor platform in the real-time system. The application can solve the technical problem that the existing scheduling method has poor flexibility because it cannot accurately judge the computing tasks in the real-time system before the tasks are completed.

A configuration method of a computing task, an execution method of the computing task, and an electronic device. The configuration method of the computing task includes adding a first instruction to an executable instruction sequence corresponding to a first subtask, wherein the first instruction is configured to determine whether the first subtask is activated, and to cause the executable instruction sequence corresponding to the first subtask to perform a corresponding operation when the first subtask is activated; and adding a second instruction to the executable instruction sequence corresponding to the first subtask, wherein the second instruction is configured to set a second subtask to an activated state. In the configuration method and the execution method of the computing task, the first subtask and the second subtask are automatically triggered to execute, and the second subtask does not need to be actively activated in a control flow by a host-side processor when the second subtask is executed, thereby simplifying an application layer control flow, reducing a burden caused by control layer code, increasing performance, saving an overhead of scheduling of the host-side processor for a high-throughput and low-latency exclusive application scenario.