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6 results about "Processor scheduling" patented technology

Launching authenticated content on arm realm management mode architecture systems

An information handling system includes a BMC and a processor. The processor provides a guest operating stack and a Realm operating stack. The processor further launches a Realm on the Realm operating stack and loads an application on the Realm. The processor instantiates a Realm management monitor (RMM) on the Realm operating stack. The RMM provides a Realm initial measurement (RIM) for the Realm, generates a Realm attestation token based on the RIM, and provides the Realm attestation token to the BMC. The RIM includes information to identify the application. The BMC determines whether the application is authenticated by a certificate authority based on the Realm attestation token and directs the processor to schedule execution of the Realm when the application is authenticated by the certificate authority.
Owner:DELL PROD LP

Processor scheduling method and apparatus

The application discloses a processor scheduling method and device, and belongs to the technical field of electronic equipment. The method comprises the following steps: obtaining the job cycles of a plurality of tasks to be scheduled; determining the load evaluation window duration corresponding to each task according to the job cycles; taking the load evaluation window duration as a statistical period, respectively performing load statistics on the tasks with the same load evaluation window duration to obtain the aggregated load values corresponding to each load evaluation window duration; and determining the target working frequency of a processor according to the aggregated load values corresponding to all load evaluation window durations.
Owner:VIVO MOBILE COMM CO LTD

Multi-processor system and method thereof, electronic device, storage medium, and program product

PendingCN122261792AResource allocationProcessor schedulingMulti processor
The application relates to a multi-processor system and a method thereof, an electronic device, a storage medium and a program product. The multi-processor system comprises a scheduler and at least one processor comprising a resource manager. The scheduler is configured to, in response to a logical instance allocation request from an application program, acquire a target processor satisfying the logical instance allocation request according to available hardware resources of each processor in the multi-processor system, and send the logical instance allocation request to a resource manager in the target processor; the logical instance allocation request comprises a priority, a minimum resource requirement and a maximum resource requirement of a logical instance; and the resource manager is configured to allocate an appropriate logical instance for the application program in response to the logical instance allocation request, and dynamically adjust the allocation of hardware resources among a plurality of logical instances according to a preset strategy to preferentially meet the maximum resource requirement of a logical instance with a high priority. The application can improve the resource utilization rate of the processor in the multi-processor system.
Owner:NANJING TIANSHU ZHIQI TECHNOLOGY CO LTD

Hardware rules processor for packet filtering

PendingUS20260140761A1Program initiation/switchingTransmissionData packProcessor scheduling
A hardware device is communicatively connected to host servers individually supporting a virtual switch and one or more virtual machines and includes a processor input to receive a header of a data packet in the hardware device, a hardware rules processor scheduler to schedule processing of the header among hardware processing cores in the hardware rules processor, a rules processor core scheduled by the hardware rules processor scheduler to receive the header from the hardware rules processor scheduler, the rules processor core to read compiled networking policies from the memory, and to apply the compiled networking policies to the header to yield a modified header for the data packet, and a connection establishment processor to record the networking connection for the data packet based on the modified header in an established connection datastore.
Owner:MICROSOFT TECHNOLOGY LICENSING LLC

A heterogeneous processor scheduling method and system based on federal scheduling

ActiveCN116382864BProcessor schedulingWorkload
The application discloses a heterogeneous processor scheduling method based on federal scheduling, which firstly acquires the running features of multiple tasks running on a heterogeneous processor platform in a real-time system and the workloads of each processor, analyzes the tasks by using a DAG task model to obtain the deadlines of each task, then acquires the running speed of each task on each processor in the heterogeneous processor platform according to the deadline of each task, and subsequently evaluates each processor according to the running speed of each task on the processor to obtain the preference degree of different types of processors to all tasks on the heterogeneous processor platform in the real-time system. The application can solve the technical problem that the existing scheduling method has poor flexibility because it cannot accurately judge the computing tasks in the real-time system before the tasks are completed.
Owner:HUNAN UNIV +1

Computing task configuration method, computing task execution method, and electronic device

ActiveCN115543447BComputer architectureProcessor scheduling
A configuration method of a computing task, an execution method of the computing task, and an electronic device. The configuration method of the computing task includes adding a first instruction to an executable instruction sequence corresponding to a first subtask, wherein the first instruction is configured to determine whether the first subtask is activated, and to cause the executable instruction sequence corresponding to the first subtask to perform a corresponding operation when the first subtask is activated; and adding a second instruction to the executable instruction sequence corresponding to the first subtask, wherein the second instruction is configured to set a second subtask to an activated state. In the configuration method and the execution method of the computing task, the first subtask and the second subtask are automatically triggered to execute, and the second subtask does not need to be actively activated in a control flow by a host-side processor when the second subtask is executed, thereby simplifying an application layer control flow, reducing a burden caused by control layer code, increasing performance, saving an overhead of scheduling of the host-side processor for a high-throughput and low-latency exclusive application scenario.
Owner:SHANGHAI BIREN TECH CO LTD