405 results about "Compiler" patented technology

The invention discloses a reciprocal calculation instruction sequence generation method oriented to a heterogeneous processor, and belongs to the field of compilation optimization and code generation. Aiming at the problems of instruction redundancy, weak precision control, poor hardware adaptation and high manual dependence of an existing method in a heterogeneous environment, characteristics of a reciprocal instruction and an operand are accurately identified by linearly scanning heterogeneous object codes (including vectorization, scalar and complex instruction sequences); in combination with hardware characteristics of RISC / SIMD / VLIW / DSP and the like, a multi-round iteration precision improvement and temporary register optimization allocation strategy is adopted, differential generation logic is formulated, and a high-precision low-redundancy instruction sequence is generated. The method comprises linear code scanning classification, reciprocal instruction and operand identification, cross-architecture generation logic rule formulation, instruction sequence generation and legality verification. Full-process automation is achieved, manual intervention is reduced, the execution efficiency and precision of reciprocal calculation of the heterogeneous processor are improved, and the method is suitable for embedded systems, high-performance calculation and other scenes.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

The invention provides an equipment debugging system based on a serial port, which relates to the technical field of data processing, and comprises a server side and a client side which are in communication connection through the serial port, the server side comprises a memory, a command parser, a command distributor and a function executor; the memory is used for storing a debugging command registry; the command parser is used for parsing a protocol data packet which is transmitted through a serial port and comes from a client side, querying a debugging command registry and determining a debugging function corresponding to a command ID; the command distributor is used for distributing debugging functions to the function executor; the function executor is used for executing operation corresponding to the debugging function; the client side comprises a compiler, a description file analyzer and a graphical user interface; the compiler is used for generating a debugging description file after compiling the MCU program; the description file analyzer is used for analyzing the debugging description file, generating a protocol data packet and sending the protocol data packet to the server side through a serial port; the graphical user interface is used for displaying debugging information.

An image processing system includes one or more processors operative to receive a graph application programming interface (API) call to add a complex node to a graph. The graph includes at least the complex node connected to other nodes by edges that are directed and acyclic. The one or more processors are further operative to process, by a graph compiler at compile time, the complex node by iteratively expanding the complex node into multiple nodes with each node corresponding to one operation in an image processing pipeline. The system further includes one or more target devices to execute executable code compiled from each node to perform operations of the image processing pipeline. The system further includes memory to store the graph compiler and the executable code.

The invention provides an automatic design method and equipment of a storage circuit and a storage medium. The method comprises the following steps: acquiring demand parameters input by a user in a compiler; importing a plurality of circuit units after the standard memory circuit is disassembled into a compiler; determining a target circuit architecture according to the demand parameters; calling a plurality of corresponding circuit units from a compiler according to the demand parameters; and splicing the called circuit units to positions corresponding to the target circuit architecture to obtain a target storage circuit meeting the demand parameters. On this basis, the demand parameters of the user and the plurality of circuit units obtained by disassembling are input into the compiler, and the target circuit architecture is determined through the compiler, the plurality of corresponding circuit units are called, and the splicing of the plurality of circuit units is executed, that is, the whole design of the target storage circuit can be automatically completed in the compiler. The manual participation degree is reduced, the overall efficiency is high, the possibility of manual misjudgment can be completely eradicated, and the reliability of the whole circuit design is ensured.

The invention discloses a cross-language migration-based low-resource programming language corpus enhancement method, which comprises the following steps of: receiving a source language code, and driving a large language model to generate an initial target language code through a two-way retrieval mechanism fusing example guidance and knowledge constraint; secondly, constructing an automatic iterative repair closed loop by utilizing the feedback of a compiler, and carrying out self-correction on codes which fail to be compiled; thirdly, high-quality codes are screened out through automatic quality gating and fed back to a corpus and a knowledge base, and self-enhancement circulation of data and knowledge is formed; finally, the method further comprises an offline model evolution step based on grammar and semantic alignment driven by a compiler, a big language model is trained by collecting preference data generated by an online process, and the ability of the big language model to understand a target language is improved fundamentally. According to the method, the core problems of low quality, poor efficiency and lack of self-evolution ability of a low-resource programming language in code migration are solved.

The invention provides a storage unit type selection method and device, electronic equipment and a computer storage medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: establishing a storage unit specification general table which can be generated by a target compiler, wherein the specification general table comprises a plurality of sub-tables; receiving a target depth and a target bit width of the storage unit required by a user; respectively generating a candidate scheme capable of realizing a target depth and a target bit width based on each sub-table to obtain a plurality of groups of candidate schemes; on the basis of a preset model selection principle, determining the candidate schemes, which can be matched with the target depth and the target bit width in a splicing mode, in all the candidate schemes as feasible schemes; based on a preset back-end physical constraint condition, selecting a global optimal scheme from the feasible schemes; the compiling general table is established in advance, multiple sets of candidate schemes are automatically established for each sub-table in the compiling general table, then layer-by-layer screening is performed according to a preset rule to determine a global optimal scheme, and the layout efficiency is improved.

A computer-implemented method for a machine learning based rules compiler, the method comprising receiving machine learning generated ripple down rules, the ripple down rules comprising exception rules for tags in a tag set, the exception rules comprising tag string comparisons. The method further comprises compiling the ripple down rules into optimized computer code. Compiling the rules into computer code further comprises generating an enumeration statement for an enumeration containing the tag set, translating the exception rules for each tag in the tag set into if-else statements for a respective tag, including replacing the tag string comparisons with the enumeration; and generating a switch case statement for a current tag, the switch case statement having cases corresponding the tags in the tag set and including the if-else statements for the respective tag. The optimized computer code comprises the enumeration statement and the switch case statement.

The invention discloses a Java-to-Cangjie code translation method based on a large model and compilation feedback, and particularly belongs to the technical field of software engineering program language processing, and the method comprises the following steps: step 1, performing structured semantic pre-training by constructing a grammar knowledge base of a target language, and injecting grammar prior knowledge of the target language; step 2, performing semantic enhanced supervision fine tuning training by constructing a high-quality data set containing semantic information, and enhancing semantic alignment and cross-language migration ability of the model; 3, introducing an AST structure perception embedded prompt mechanism in a parallel corpus supervision fine tuning training stage, and guiding the model to perform structure perception translation; and 4, establishing a compiler feedback repair loop, and iteratively correcting output based on error information to form a self-optimized closed-loop system. According to the method, an efficient training path is constructed, dependence on large-scale parallel corpora is effectively reduced, and an extensible and high-reliability technical path is provided for cross-language code translation of low-resource programming languages.

Aspects of the present disclosure relate generally to systems and methods for optimizing an implementation of a quantum chemistry task in a quantum circuit. The method includes obtaining a chemistry task presented as a Hamilton to implement in a Variational Quantum Eigensolver (VQE) circuit. The method also includes mapping the chemistry task to a qubit space of the VQE circuit with Unitary Coupled Cluster with Single and Double excitations (UCCSD) ansatz. The method also includes decomposing the fermionic excitations to Givens rotations and controlled-Z (CZ) gates by passing exponentiated Pauli forms in the VQE circuit to a cloud compiler. The method further includes after commuting the CZ gates through Givens rotations, cancelling the commuted CZ gates. The method further includes dropping CZ gates at the beginning and the end of the quantum circuit.

The invention provides a real-time incremental RAG method and system based on a dual-tense knowledge graph, and belongs to the technical field of artificial intelligence and knowledge graphs. The method comprises the following steps: through dual-tense decoupling modeling of event effective time and system input time, constructing a versioned knowledge graph and establishing a tense index; efficient retrieval is carried out by adopting a time sequence pruning algorithm based on indexes, and dynamic expansion of a graph pattern is realized through a declarative compiler; realizing abstract-free high-precision result sorting by utilizing a multi-modal concurrent retrieval and attention fusion mechanism; incremental updating of the knowledge graph is realized through streaming data processing and a distributed engine; and closed-loop optimization is formed according to user feedback. The system effectively solves the problems that a traditional RAG scheme is high in data updating delay, tense information is lost, retrieval efficiency is low and expansibility is poor, tense query accuracy, retrieval efficiency and system throughput are remarkably improved, and meanwhile operation and maintenance complexity is reduced.

A compiler of a computing device is described that identifies a sequence of neural network models frequently invoked by an application of the computing device, compiles the models in that sequence, and loads a static random access memory (SRAM) of a hardware accelerator with the compiled models only when the same compiled models—from another, but same, sequence that was previously invoked—are not already present in the SRAM. This prevents unnecessary reloading of compiled models into the SRAM, thereby increasing runtime speed and conserving computational energy.

The invention relates to the technical field of processors, in particular to a memory access system, electronic equipment and a memory access method. In the system, when a first processor operates a compiler in a software form to compile a code and a pointer appearing in the code meets a first preset condition, an identifier of a storage space actually pointed by the pointer is written into a universal address pointed by the pointer; generating a memory access instruction and sending the memory access instruction to a distribution front end in a hardware form, wherein the memory access instruction carries the universal address pointed by the pointer; the distribution front end determines a target rear end from a plurality of memory access rear ends in a hardware form according to an identifier in a general address carried by the memory access instruction, and distributes the memory access request to the target rear end; when the memory access rear end serves as the target rear end, the memory access request is executed, and the storage space corresponding to the universal address is accessed. According to the memory access system disclosed by the embodiment of the invention, the storage space actually accessed by the instruction is determined in a software and hardware cooperation manner, so that the compiling complexity, the hardware cost and the memory access delay are relatively small.

The invention provides a multi-language-oriented source code automatic verification method and system, and relates to the technical field of computers.The method comprises the steps that multi-language source codes are obtained; compiling the multi-language source code through an LLVM compiler to generate an intermediate file; the intermediate file is optimized; analyzing the optimized intermediate file through an IR analyzer to generate a symbolic execution model; performing simulation execution operation on the symbolic execution model; and performing security verification on the symbolic execution model after simulation execution operation to obtain a verification report. Unified verification of multi-language source codes can be achieved, the verification environment building and development cost is greatly reduced, and the overall verification efficiency is improved; and the analysis capability of the intermediate file can be enhanced, the logic constraint relationship in the code can be accurately captured, the comprehensiveness and reliability of the verification work can be practically guaranteed, and diversified software security verification requirements can be met.

According to the SIMT architecture branch processing system and method based on the structured nodes, explicit node marks are inserted into branch codes through a compiler, accurate control over active masks of all threads in the program execution process is achieved, and part of branch codes, not needing to be executed currently, of the threads are shielded; a full-branch consistent detection unit is designed to judge three mask states of'all true / all false / divergence 'of current active masks of the same group of threads, so that the operation of instructions of irrelevant branches is directly skipped under a full-branch consistent scene (all true / all false), all instructions of all branches are normally executed under a divergence scene, and all the instructions of all the branches are normally executed under the divergence scene. The active masks control which instructions are executed by each thread, and the state of the active mask of each thread is accurately controlled through node marks.

The invention discloses a method for dynamically constructing a UDF based on a large model. The method comprises the following steps: S1, constructing a multi-dimensional requirement cue word of a user-defined function according to characteristics and use requirements of a target platform; s2, the multi-dimensional requirement cue words are input into a pre-trained large language model for code generation, the large language model is subjected to multi-round iteration based on the multi-dimensional requirement cue words, and an optimal code sequence for achieving the user-defined function is output; s3, code style standardization is carried out on the optimal code sequence, and a compiler or an interpreter and a static analysis tool are respectively called to carry out grammar check and static analysis on the optimal code sequence, and constructing an optimization cue word according to an error log output by the compiler or the interpreter and a static analysis result output by the static analysis tool, and inputting the optimization cue word into the large language model to carry out iterative optimization on the optimal code sequence.

The invention discloses an optimization option difference-based MLIR compiling framework test method. The method comprises the following steps of identifying and repairing undefined behaviors possibly causing unpredictability of an execution result by analyzing an operator document and calling a large language model; constructing a model based on a graph neural network, learning a dependency relationship between IR data flow structure features and optimization options, and completing model training; calling the trained model to predict and insert optimization options at random positions in the option sequence, so as to construct various option sequences; for the same test case, a plurality of option sequences are respectively applied to obtain a plurality of calculation results, the results are compared, and whether an inconsistency defect exists or not is judged based on the consistency of the results. In an MLIR compiler inconsistency defect detection scene, effective management and control of undefined behavior interference are realized to ensure the accuracy of a differential test, and an option application strategy is optimized to improve an option trigger rate, maximize the effect of a test case and reduce resource loss.

Techniques for automatically orchestrating, generating, and / or deploying a multi-agent are disclosed. A super agent ingests metadata describing a use case to identify workflows and tasks. A task assigner agent assigns the tasks to task agents. A task performer agent performs a basic task. A vertical agent performs a task using vertical resources of a system. A specialized task agent performs specialized tasks, such as those performed using a specialized language model. An orchestration agent arranges task agents into an orchestration according to a graph representation of a workflow. A compiler agent packages the orchestration into an executable. The executable is called to perform the workflow. An orchestration engine automatically selects task agents used to complete the workflow and compiles them into the executable. The system collects feedback based on the results of the executable and uses the feedback to optimize the super agent and / or the task assigner agent.

The invention discloses an optimization sensitive test system and method for an AI compiler, and belongs to the technical field of software testing. The method mainly comprises the following steps: firstly, automatically extracting an IR sub-graph mode capable of triggering specific optimization Pass from an existing test of a compiler through dynamic instrumentation; secondly, through a strategy of multiplexing compatible nodes or creating new nodes, the optimization modes are intelligently synthesized into a diversified seed calculation graph context, and a large number of test cases capable of effectively triggering compiler optimization are generated; and finally, efficiently revealing the defects of the AI compiler in the optimization stage by taking crash detection and reasoning consistency comparison as test predictions. The defect that an existing random generation or grammar generation method is insufficient in test coverage rate in the optimization stage is overcome, the deep optimization defect in the AI compiler can be automatically and efficiently detected, and the method has the high error detection rate and good universality.

The invention discloses a memory generation method, electronic equipment and a storage medium, and relates to the technical field of integrated circuit design, and the method comprises the following steps: obtaining basic parameters of a memory; converting the basic parameters into compiler commands; determining a splicing strategy for the physical memory according to the data width, the address depth and the size of the physical memory; a logical memory is generated based on the compiler command and the stitching policy. According to the method, the basic parameters are converted into the compiler commands, and dynamic mapping of the parameters and the compiler commands is realized, so that the basic information, the function information and the performance information of the memory are unified and automatically read, the logic memory is automatically generated, the method has universality, and the generation efficiency of the memory is improved.

The embodiment of the invention generally relates to the technical field of compilers, in particular to an automatic vectorization method and device for mathematical function calling. The method includes determining whether a loop of an objective function includes a vectorizable call for a vectorizable mathematical function. The method further includes, in response to determining that the loop includes a vectorizable call for the vectorizable mathematical function, generating a vector built-in mathematical function corresponding to the vectorizable mathematical function based on the vectorizable mathematical function, where the vector built-in mathematical function includes a function name and a vector type. In addition, the method further comprises the step of converting multiple calls for the vectorizable mathematical function in the target function into one call for the vector built-in mathematical function based on the vector built-in mathematical function. Automatic vectorization of multiple calls of mathematical functions in a program can be achieved, and the parallel computing capacity of a processor is improved.

The invention discloses a compiler for generating reconfigurable executable programs, and particularly discloses apparatuses, systems, and techniques for executing a compiler to generate one or more executable programs that can be configured to be executed by one or more of a plurality of different processor architectures. In at least one embodiment, a compiler generates one or more executable programs based at least in part on the original uncompiled executable programs, which may be configured to be executed by one or more of a plurality of different processor architectures.

The application provides a method and system for optimizing a DSP core simulation based on a SIMD instruction, wherein the method comprises the following steps: firstly, obtaining a DSP simulation project file, and identifying target instructions with CPU occupation time reaching a preset threshold by combining a performance profiling tool; secondly, analyzing the semantics of the target instructions and extracting parallel operations, and matching a host processor SIMD instruction set to determine a corresponding execution function; thirdly, writing a processing function for calling the execution function; fourthly, replacing original simulation logic of the target instructions in the source code with a processing function call, and supplementing a file reference declaration; and finally, recompiling through a compiler adapted to the SIMD instruction set to generate an optimized executable file, namely a target executable file. The application can effectively improve the simulation running speed of a VLIW type DSP core, has strong optimization targeting, and guarantees accurate simulation calculation results.

Implementations of this specification provide data processing methods, apparatuses, and systems. In one implementation, a method includes: obtaining a statement for a data operation, wherein the statement comprises a command field, parsing the statement by a compiler, wherein the compiler is configured to support at least one syntax and provide a field translation relation among different syntaxes, in response to determining that the command field is absent from the at least one syntax supported by the complier, determining a target field in the at least one syntax that corresponds to the command field, and performing the data operation based on the target field.

The invention discloses an electric vehicle V2G intelligent power distribution method based on sequence control, and the method comprises the steps: collecting power grid operation data and vehicle state data, and constructing an energy state data set after preprocessing; the central scheduling layer generates a self-evolution sequence compiler, and optimizes and generates a sequence control byte code; the group coordination layer constructs an energy state coordination game mechanism and executes local coordination and Nash equilibrium search; the edge execution layer loads the three types of strategies and executes consensus consistency verification and correction; the charging pile terminal executes the S-policy script and collects and uploads execution feedback information; and the central scheduling layer retrains a compiler according to feedback, recompiles scripts and updates a control strategy. According to the method, the self-evolution sequence compiler, the energy state collaborative game mechanism and the multi-strategy consensus executor are introduced, so that dynamic scheduling, adaptive optimization and safe consistent execution of the V2G intelligent power distribution process of the electric vehicle are realized.

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and / or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

The invention provides a software testing method and device, electronic equipment and a storage medium. The method comprises the steps that a source code file of to-be-tested software is compiled based on a WebAssembly compiler to obtain a compiling result and first debugging information, and the first debugging information represents the mapping relation between code lines in the source code file and instructions in the compiling result; the compiling result is converted into a to-be-tested binary file based on a format conversion relation, second debugging information is determined according to the first debugging information, the compiling result and the to-be-tested binary file, the format conversion relation is used for converting the WebAssembly binary file into a binary file in a preset format, and the format conversion relation is used for converting the WebAssembly binary file into the to-be-tested binary file. The second debugging information represents a mapping relation between a code line in the source code file and an instruction in the to-be-tested binary file; and running the to-be-tested binary file in a virtual machine used for running the binary file in the preset format, and debugging the to-be-tested binary file based on the second debugging information in the virtual machine.

An apparatus, method, and machine-readable medium are described for automated quantum-classical resource balancing optimizations. For example, one embodiment includes a machine-readable medium having program code stored thereon which, when executed by a machine, implements a plurality of functional components of a quantum compiler, comprising: quantum compiler logic to generate an intermediate quantum circuit representation based on hybrid quantum-classical source code designed for a hybrid quantum-classical system comprising a quantum computing component and a classical computing component; and optimization logic to analyze the intermediate quantum circuit representation and generate an optimized quantum circuit representation based, at least partly, on system-dependent parameters and configuration parameters, the system-dependent parameters associated with characteristics of the quantum computing component and the classical computing component and the configuration parameters to indicate user requirements.

The invention discloses an actuarial calculation engine code compiler, an operation method and a related product. The actuarial calculation engine code compiler comprises an editing layer, an analysis layer and a mapping layer. The editing layer is configured to compile an actuarial process about the target actuarial business by adopting actuarial business terms and actuarial logic in response to the operation of the client; the analysis layer is configured to analyze the actuarial process and identify variables, formulas and time sequences in the actuarial process; generating a main syntax tree comprising target actuarial business semantics and a sub syntax tree comprising operation symbols and functions; and a mapping layer configured to parse the main syntax tree and the sub-syntax tree into machine executable code. In the embodiment of the invention, the actuarial process is edited through the actuarial business terms and the actuarial logic, and the actuarial process is converted into the machine executable code, so that the actuarial process adapts to high professionality and high suitability of professional evaluation of actuarial professionals.