1348 results about "Compiler" patented technology

A method for using a compiler to modify prompts for MLMs used to generate database queries includes receiving, at a query compiler, a first query of a database. The first query is at least in part generated by an MLM. The method includes determining, by the query compiler, whether the first query comprises an uncorrectable error. The method includes, responsive to determining that the first query comprises an uncorrectable error, generating a prompt element that describes the uncorrectable error and that is structured for inclusion in a prompt requesting the MLM to generate a modified first query that corrects the uncorrectable error. The method may include generating the prompt for the MLM, providing the prompt to the MLM, and responsive to providing the prompt, receiving, at the database query compiler, the modified first query that corrects the uncorrectable error.

The invention discloses a PLC code generation and verification method based on a large language model, and the method comprises the steps: generating multi-stage multi-mode input data which is used for representing user demands and formulating a system design scheme according to a demand analysis result; the multiple stages comprise a demand analysis stage and a design stage of a complete engineering cycle; the multi-mode input comprises a Pamp (Passive Amplitude Point); an ID graph and a natural language; then, according to the multi-stage multi-mode input data, a PLC code is generated; then, verification testing is carried out on the generated PLC code, and the verification testing comprises code verification and compiler verification; and finally, after the verification test on the PLC code is completed, deploying the PLC code. The PLC code deployment method is high in accuracy and automation degree, an efficient and accurate PLC code deployment method can be provided for network security researchers, and the PLC code deployment method can be widely applied to the technical field of computers.

The invention relates to an automatic modeling agent system based on an MCP protocol and a large model, and the system comprises a multi-modal input interface module which is used for receiving, analyzing and standardizing modeling instructions or intention descriptions inputted by a user through different media to form structured feature representations; the semantic understanding central module is used for performing semantic analysis on the structured feature representation by using a pre-trained large language model and outputting a user modeling intention; the MCP instruction compiler module is used for converting a user modeling intention into an MCP instruction sequence following an MCP protocol; and the modeling execution engine module is used for analyzing and automatically executing the MCP instruction sequence to complete modeling of the target three-dimensional model. According to the method, three-dimensional modeling can be completed without knowing professional modeling terms and concepts by a user, and the modeling automation and intelligence level is greatly improved.

The invention discloses an instruction execution acceleration method based on a GPGPU and a GPGPU architecture, and relates to the field of high-performance computation.The method comprises the steps that a thread execution task output by a host compiler is received, and the thread execution task is scheduled according to the current idle state of a computing unit; capturing instruction data output by the host compiler, and executing concurrent instruction decoding according to the corresponding instruction type to obtain a machine code corresponding to the instruction data; obtaining an operand corresponding to the instruction data, and generating a to-be-transmitted instruction based on the machine code corresponding to the instruction data and the operand after secondary verification; according to the calculation complexity, determining an optimal calculation unit, and sending the to-be-launched instruction to the optimal calculation unit; and receiving an execution result of the to-be-transmitted instruction, and returning the execution result to the terminal. The thread execution task is dynamically scheduled according to the idle state of the computing unit, so that computing resources can be fully utilized, and the operation efficiency is improved.

A system and method for splitting a machine learning (ML) graph is disclosed. The system includes a compiler configured to receive an ML model. The compiler generates a graph associated with the ML model, wherein the graph is an internal representation of the ML model. The graph is partitioned into a first subgraph and a second subgraph. The first subgraph is associated with an ML hardware, an ML emulator, or a combination thereof, and the second subgraph is associated with a processor different from the ML hardware. A set of low-level instructions associated with the first subgraph is generated. One or more resources in the ML hardware is identified to execute the set of low-level instructions associated with the first subgraph.

The invention relates to the technical field of computer code upgrading, and discloses an automatic code upgrading method and device based on a compiler and a storage medium. The method comprises the steps that firstly, lexical analysis, grammatical analysis and semantic analysis are conducted on a source code, an abstract syntax tree is generated, then a new standard grammatical rule mapping table is constructed, and a new standard grammatical rule mapping table is generated; and traversing the abstract syntax tree, querying whether the nodes of the abstract syntax tree can be queried in the mapping table, outputting the character strings mapped to the queried nodes, and normally outputting codes conforming to node semantics for the nodes which are not queried. The abstract syntax tree of the original code is automatically traversed, and node matching and conversion are performed according to the syntax rule mapping table of the new standard, so that the need of manual intervention is greatly reduced, the automation degree of code migration from an old standard to the new standard is improved, a large amount of manpower and time cost is saved, and the migration problem caused by human errors is reduced.

Apparatuses, systems, and techniques to select optimizations to be performed by compilers. In at least one embodiment, a processor includes one or more circuits to perform a compiler to select one or more optimizations to one or more first versions of a program based, at least in part, on a result of performing said one or more optimizations on one or more second versions of said program.

Apparatuses, systems, and techniques to perform one or more operations using a tensor. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to perform one or more operations using one or more tensors based on at least one or more indications of the plurality of operations by the API, one or more compiler options indicated by the API, and / or one of one or more indications of an amount of storage to be used to perform the one or more operations.

Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the graph includes nodes representing options for implementing each layer of the machine-trained network and edges between nodes for different layers representing different implementations that are compatible. In some embodiments, the graph is populated according to rules relating to memory use and the numbers of cores necessary to implement a particular layer of the machine trained network such that nodes for a particular layer, in some embodiments, represent fewer than all the possible groupings of sets of clusters.

Automated composite agent generation includes generating an agent cooperation graph (ACG) based on machine-human interactions between a user and digital agents pretrained to perform automated tasks. The ACG nodes represent digital agents connected by edges weighted according to cooperation densities. A composite sub-graph (CSG) whose nodes represent cooperating digital agents that cooperatively perform related tasks in response to multiple user requests is generated based on the cooperation densities. A composite agent configured to perform a composite process in response to a composite instruction is generated and includes a composite evaluator and composite actuator. The composite evaluator is generated based on the multiple requests using a language model. The composite actuator is generated using an automated processes compiler that compiles the related automated processes. The composite actuator of the composite agent actuates the composite process, which performs the related automated tasks as a single, integrated process.

A system comprises an array of reconfigurable units including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs), and a compiler configured to receive a tensor including a plurality of memory access patterns of a first type (read) and a second type (write) located in a logical memory of the compiler. Each memory access pattern includes a memory access particular to that type. The compiler is configured to create a plurality of duplicates of the tensor and assign one or more contexts of any type to the duplicate tensors, such that no two contexts of the same type are in the same duplicate tensor. The compiler is configured to trim the duplicate tensors to retain portions including its corresponding assigned contexts remove portions that are inconsequential to the assigned contexts and dispatch the assigned contexts from each duplicate tensor to one or more PMUs.

The invention discloses an automatic compiling and adapting method for an RISC-V extension instruction, and belongs to the technical field of compilers. According to the method, a dynamic DSL (Digital Subscriber Line) for registering a custom instruction, adding register use constraints and defining a specific code mode is designed. The LLVM plug-in is used for automatically integrating the registered custom instruction in the compiling process. The invention relates to a self-defined instruction rapid adaptation mechanism which is specially provided for a continuously provided RISC-V self-defined instruction expansion scene, and by automatically generating correct assembly codes of registered self-defined instructions, correct registers are automatically distributed and reserved according to register use constraints; the method comprises the following steps of: searching a defined specific code mode and semantics, and automatically generating and inserting a registered custom instruction in a program, so as to realize the rapid adaptation of a compiler to an RISC-V custom extension instruction and the automatic use of a program code to the custom instruction, and the whole process does not need a developer to manually modify the compiler or a program source code.

The invention discloses a program analysis method and device, a readable storage medium and electronic equipment. A to-be-analyzed program is determined, an abstract syntax tree of the to-be-analyzed program is determined through a compiler corresponding to a programming language used by the to-be-analyzed program, nodes in the abstract syntax tree are standardized, and a standard syntax tree is determined. And determining each control flow edge and each data flow edge in the standard syntax tree through the standard syntax tree, adding each control flow edge and each data flow edge to the standard syntax tree, and determining the code attribute graph of the program to be analyzed. The abstract syntax tree is converted into the standard syntax tree, the abstract syntax trees of the programs to be analyzed in different programming languages are unified, and the code attribute graph is constructed based on the standard syntax tree, so that the method can be suitable for program analysis of the programs to be analyzed in various programming languages; different analysis algorithms do not need to be developed for different programming languages, the program analysis efficiency is improved, and the development cost is reduced.

According to the abstract syntax tree optimization method based on the ST language, the ST programming language is optimized through the compiler front-end technology, the code structure is optimized from the source, the compiling efficiency is improved, and the execution efficiency of the finally generated instruction is improved. An abstract syntax tree optimization method based on an ST language comprises the steps that 1, an antlr tool is used for conducting lexical analysis and grammatical analysis of the ST language, and a complete abstract syntax tree is created; (2) traversing the abstract syntax tree to carry out constant merging, calculating constant tree nodes in advance, and merging the constant tree nodes into a tree node; (3) traversing the abstract syntax tree to eliminate dead codes, and deleting useless tree nodes; and (4) traversing the abstract syntax tree to calculate characteristic values of the tree nodes, and eliminating sub-expressions according to the similarity of the tree nodes, thereby reducing redundant calculation and improving execution efficiency.

The invention discloses a method, a device, equipment and a medium for realizing multi-service instance configuration, in the method, a Java compiler is called to scan a source code, a class marked with multi-instance container annotations is obtained, the class defines a plurality of service instances, and each service instance is marked with a corresponding multi-instance basic annotation; based on a preset annotation processor, traversing the multi-instance basic annotation corresponding to each service instance, obtaining a class attribute value and a prefix attribute value, and obtaining a first configuration class corresponding to the first automatic assembly class; according to the prefix attribute value, processing the byte code of the first configuration class and the byte code of the first automatic assembly class to obtain a second configuration class and a second automatic assembly class; and adding the second configuration class file and the second automatic assembly class file to the resource directory to realize configuration of the service instance. Thus, by introducing special multi-instance configuration annotations, namely, multi-instance container annotations and multi-instance basic annotations, the official automatic assembly class is expanded and customized, and multi-service instance configuration is achieved.

A data processing system includes an array of reconfigurable units and a compiler configured to generate a pipeline of n computational nodes related to a dataflow graph, interleaved between n+1 buffers on the array of reconfigurable units. Each computational node is coupled to perform calculations based on data received from an immediately preceding buffer of the n+1 buffers and store results of the calculations into an immediately following buffer of the n+1 buffers after a latency. The compiler is further configured to remove a buffer of the n+1 buffers from the pipeline based on a comparison of the latencies of the computational nodes. A corresponding method is also disclosed herein.

The invention relates to the technical field of artificial intelligence and software development, in particular to a context-aware code generation and real-time optimization method and system based on a large language model.The method comprises the following steps that a compiler front-end technology is utilized, input codes are analyzed, and an abstract syntax tree is constructed; function definition, variable declaration and statement block structure information are extracted through an abstract syntax tree, so that syntax and semantic structures of codes are obtained, and basic data support is provided for subsequent code generation and optimization; the method has the beneficial effects that the context graph covering grammar, semantics and runtime behaviors is constructed by fusing static grammar analysis (AST construction) and dynamic execution tracking (such as variable value change and function call time sequence), and the problem of context perception deficiency in a traditional code generation technology is solved. And the compatibility, the maintainability and the expandability of the generated code and the project architecture are improved.

The invention belongs to the technical field of computer system security, and particularly relates to a binary component vulnerability recognition method based on a large language model. The method solves the problems of various equipment types, various instruction set architectures, different compilers, different compiling optimization levels and the like in the current Internet of Things binary component vulnerability recognition, and comprises the following steps: S100: collecting various vulnerability description information of an Internet of Things component, extracting data from the vulnerability description information, and constructing a text information data set; s200, performing text segmentation processing on a long text in the text information data set; s300, inputting the constructed text information data set into a large language model for training and optimization; and S400, detecting the binary component by using the trained vulnerability recognition large model to obtain a binary component vulnerability detection result report.

In various examples, an interactive agent platform that hosts development and / or deployment of an interactive agent may provide an interpreter or compiler that interprets or executes code written in the interaction modeling language, and a designer may provide customized code written in the interaction modeling language for the interpreter to execute. The interaction modeling language may be used to define a flow of interactions that instruct the interpreter what actions or events to generate in response to a sequence of detected and / or executed human-machine interactions. The interaction categorization schema may classify interactions by standardized interaction modality and / or corresponding standardized action category. As such, a flow may be used to model an agent intent or inferred user intent, which a designer may use to build more complex interaction patterns with the interactive agent.

Provided herein are systems and methods comprising one or more virtual machines and a compiler to enable automatic differentiation across a stack. Further provided herein are technologies, integrations, and workflows to allow for automatic differentiation.

A new approach is proposed to support correlating high-level code with low-level instructions of an application running on a hardware. A compiler that compiles a high-level function in the high-level code of the application into a set of low-level instructions to be executed on the hardware is configured to utilize one or more reserved fields of the set of low-level instructions to incorporate one or more IDs and an actionable item. The IDs are mapped to the high-level function, wherein such mapping is programmable by the compiler. Based on the mapped IDs and the actionable item incorporated in the set of the low-level instructions, the runtime performance of the application on the hardware can be monitored and profiled and issues related to the high-level code of the application can be identified for debugging purposes.

The invention discloses a method for executing a virtual instruction set so as to construct an operator library to realize a deep learning accelerator and solve the problem of cross-generation compatibility. The method provides a virtual instruction set execution unit, namely a virtual instruction set, then compiles the virtual instruction set into a vector instruction and / or a dedicated instruction by a compiler, and finally executes the vector instruction and / or the dedicated instruction by the virtual instruction set execution unit. Wherein the virtual instruction set execution unit is used for executing a virtual instruction set and comprises a general vector calculation unit and a special instruction set calculation unit, the general vector calculation unit is used for executing a vector instruction set, and the special instruction set calculation unit is used for executing a special instruction set. The virtual instruction set comprises a first C + + template and a second C + + template, the first C + + template defines a first C + + function, the first C + + function can be compiled by the compiler into vector instructions in the vector instruction set, the second C + + template defines a second C + + function, and the second C + + function can be compiled by the compiler into dedicated instructions in the dedicated instruction set.

A quantum computer, comprising: at least one CPU and at least one QPU. The CPU includes: a branch predictor configured to form one or more result predictions or algorithm branches of a result of a measurement being performed or to be performed by the QPU; a compiler configured to generate respective sets of quantum gates corresponding to each of the one or more result predictions by performing respective one or more compilation tasks, each of the compilation tasks comprising compiling a portion of a hybrid quantum algorithm; and a quantum gate selector configured to receiving the result of the measurement and respond by passing to the QPU a set of quantum gates from the sets of quantum gates that corresponds to the result of the measurement.

The invention provides a retrieval enhancement generation system for instruction compliance alignment. Comprising two parts: an instruction synthesis stage and an instruction query synthesis stage; in the instruction synthesis stage, a seed instruction is handwritten firstly, then instruction combination and verification are carried out, and then the quality of an automatically generated instruction is verified; in the instruction query synthesis stage, firstly, random instruction query combination is performed, then instruction query enhancement and dual verification are performed, a sampling rejection strategy is adopted, and then a dual verification process is performed on instruction query data: based on compiler feedback, the compliance of enhancement output is evaluated by using an existing verification function; and checking the consistency of the large model: finally, automatically obtaining a large-scale and high-quality VIF-RAG-QA data set. The method can be seamlessly connected to diversified instruction following and retrieval enhancement to generate an evaluation benchmark, so that combined evaluation is realized.

The invention discloses an integer linear programming-based scale management method for a homomorphic encryption compiler, and relates to the field of cloud computing. According to the method, the scale management problem of the RNS-CKKS is formalized into an integer linear programming problem, so that the problem can be solved by using an existing mathematical method. Through the scale management method provided by the invention, a programmer can neglect the scale management requirement during programming, and the programmer can perform management automatically without intervention; compared with an existing scale management method in a homomorphic encryption compiler, the method provided by the invention can generate a program with better performance in a shorter time, and is beneficial to popularization of use of homomorphic encryption.

Embodiments of the invention provide a compiling method and apparatus, an electronic device and a readable storage medium. The method comprises the steps of converting a branch instruction in a target function into a control flow pseudo instruction related to an architecture of a compiler; performing a first instruction processing operation on any control flow pseudo instruction, and performing a second instruction processing operation on a vector instruction of which the operand type corresponding to the operand is a first preset type; and under the condition that the operand type corresponding to the operand of the control flow pseudo instruction or the vector instruction is a second preset type, determining a target physical predicate register and replacing the virtual predicate register corresponding to the control flow pseudo instruction or the vector instruction with the target physical predicate register. In this way, the number of the generated instructions is reduced, and the running efficiency of the program is improved to a certain extent. The target physical predicate registers are respectively distributed for different control flows, so that the overall execution efficiency of the program is improved, and the parallel execution capability and throughput of the program are improved.

The invention relates to a modeling and formalized verification method for cache consistency protocol verification, and the method comprises the steps: building a protocol model which comprises a plurality of processor nodes, directory nodes and a communication mechanism through a structured modeling mode, and constructing an asynchronous message mechanism to simulate disordered concurrent communication; protocol behavior rules such as processor requests, directory responses and network receiving are defined, protocol property invariants are set, semantic constraints such as data consistency, confirmation before writing and sharing state legality are covered, model verification is carried out in a state space traversal mode, breadth-first search and a symmetry recognition mechanism are supported, and the method is suitable for the protocol behavior rules. A protocol error or deadlock state is effectively found, a traceable error path is generated, a verifier can automatically generate source codes through a compiler and operate on a host platform, and rapid verification and result output of a protocol model are achieved. The method has good protocol adaptability and model reusability, and is suitable for formalized verification of various cache consistency protocols.

The invention relates to a large language model performance optimization method and device, computer equipment, a readable storage medium and a program product, and belongs to the technical field of deep learning model compilers. The method comprises the steps of obtaining data parameters and processing parameters of language data corresponding to a large language model; the processing parameters are determined according to parameters of to-be-deployed hardware corresponding to the large language model; in response to a programming operation aiming at a preset programming primitive, obtaining a target function representing arithmetic logic of the large language model; according to the data parameters and the processing parameters, compiling the target function to obtain a calculation graph corresponding to the target function; and according to the computational graph and the parameters of the to-be-deployed hardware, generating a plurality of target operators, and updating the large language model based on the plurality of target operators to obtain an optimized large language model. By adopting the method, the performance of the large language model can be improved.

According to the artificial intelligence-based compiler back-end development assisting method and device, fine tuning training is performed on an existing LLM, a large language model specially aiming at compiler back-end development optimization is obtained, and high-precision support can be provided for tasks such as code completion, generation and repair. A retrieval method is designed, an example most similar to user input can be automatically retrieved, and therefore the performance of LLM is improved in the environment that computing resources are limited. According to the method, the automation level of the rear-end development of the compiler is improved, the manual coding workload is reduced, the development efficiency is improved, and the learning cost of developers is reduced.

A method for automatically generating a compiled binary file with fault countermeasures includes compiling, by a compiler, a source code file to a first binary file; analyzing the first binary file to identify one or more fault vulnerabilities in the first binary file, wherein analyzing the first binary file to identify the one or more fault vulnerabilities includes: injecting a set of faults into the first binary file during a symbolic execution of the first binary file to generate a set of faulted states of the first binary file; and identifying the one or more fault vulnerabilities from the set of faulted states, wherein the one or more fault vulnerabilities are fault vulnerabilities that cause the first binary file to violate at least one security requirement; and compiling, by the compiler, the source code file to a second binary file, wherein the compiler inserts a set of fault countermeasures into the second binary file based on the identified one or more fault vulnerabilities, wherein the set of fault countermeasures protect the second binary file against the one or more fault vulnerabilities.