777 results about "Compiler" patented technology

Apparatuses, systems, and techniques to select optimizations to be performed by compilers. In at least one embodiment, a processor includes one or more circuits to perform a compiler to select one or more optimizations to one or more first versions of a program based, at least in part, on a result of performing said one or more optimizations on one or more second versions of said program.

The invention discloses an automatic compiling and adapting method for an RISC-V extension instruction, and belongs to the technical field of compilers. According to the method, a dynamic DSL (Digital Subscriber Line) for registering a custom instruction, adding register use constraints and defining a specific code mode is designed. The LLVM plug-in is used for automatically integrating the registered custom instruction in the compiling process. The invention relates to a self-defined instruction rapid adaptation mechanism which is specially provided for a continuously provided RISC-V self-defined instruction expansion scene, and by automatically generating correct assembly codes of registered self-defined instructions, correct registers are automatically distributed and reserved according to register use constraints; the method comprises the following steps of: searching a defined specific code mode and semantics, and automatically generating and inserting a registered custom instruction in a program, so as to realize the rapid adaptation of a compiler to an RISC-V custom extension instruction and the automatic use of a program code to the custom instruction, and the whole process does not need a developer to manually modify the compiler or a program source code.

The invention relates to the technical field of artificial intelligence and software development, in particular to a context-aware code generation and real-time optimization method and system based on a large language model.The method comprises the following steps that a compiler front-end technology is utilized, input codes are analyzed, and an abstract syntax tree is constructed; function definition, variable declaration and statement block structure information are extracted through an abstract syntax tree, so that syntax and semantic structures of codes are obtained, and basic data support is provided for subsequent code generation and optimization; the method has the beneficial effects that the context graph covering grammar, semantics and runtime behaviors is constructed by fusing static grammar analysis (AST construction) and dynamic execution tracking (such as variable value change and function call time sequence), and the problem of context perception deficiency in a traditional code generation technology is solved. And the compatibility, the maintainability and the expandability of the generated code and the project architecture are improved.

The invention relates to a modeling and formalized verification method for cache consistency protocol verification, and the method comprises the steps: building a protocol model which comprises a plurality of processor nodes, directory nodes and a communication mechanism through a structured modeling mode, and constructing an asynchronous message mechanism to simulate disordered concurrent communication; protocol behavior rules such as processor requests, directory responses and network receiving are defined, protocol property invariants are set, semantic constraints such as data consistency, confirmation before writing and sharing state legality are covered, model verification is carried out in a state space traversal mode, breadth-first search and a symmetry recognition mechanism are supported, and the method is suitable for the protocol behavior rules. A protocol error or deadlock state is effectively found, a traceable error path is generated, a verifier can automatically generate source codes through a compiler and operate on a host platform, and rapid verification and result output of a protocol model are achieved. The method has good protocol adaptability and model reusability, and is suitable for formalized verification of various cache consistency protocols.

Modifications to existing computer hardware, compiler changes or source-to-source transforms performed during the software build process, and a collection of libraries and modifications to existing standard system software and libraries. The invention allows a program author to enforce various kinds of locality of causality in software to provide enforcement of boundaries for the following aspects of a computer program: control, space, time, modularity, reference, initialization, and mutability. Where these properties do not suffice to guarantee a property at static time, dynamic checks may be added and the constraints on control flow prevent such dynamic checks from being avoided by the program.

The invention relates to an anti-reverse confusion method and system for an end-side equipment deep learning model, and the core process comprises the steps: firstly inputting an original model obtained through the training of a model training frame into a deep learning compiling frame, and extracting three types of key information, namely, a model operator, a topological structure, parameters and dimensions, through the characteristics of a compiler; then constructing a feature analysis module to evaluate model features, dynamically matching a confusion scheme from a strategy library, and balancing safety and performance; the confusion module is embedded into a plurality of different levels such as a computational graph level, an operator template level and tensor intermediate expression through a hierarchical compiling mechanism, and a complex scheme can be jointly implemented across multiple levels; and finally, the compiler synchronously completes confusion reinforcement when generating the target code. According to the method, hardware adaptation is not needed, low-overhead confusion is achieved through a native pass mechanism of a compiler, fine-grained customized protection is supported, a model structure, parameters and computational logic can be effectively hidden, reverse engineering attacks can be resisted, and the method is particularly suitable for end-side equipment scenes with limited computing power.

The invention discloses a reciprocal calculation instruction sequence generation method oriented to a heterogeneous processor, and belongs to the field of compilation optimization and code generation. Aiming at the problems of instruction redundancy, weak precision control, poor hardware adaptation and high manual dependence of an existing method in a heterogeneous environment, characteristics of a reciprocal instruction and an operand are accurately identified by linearly scanning heterogeneous object codes (including vectorization, scalar and complex instruction sequences); in combination with hardware characteristics of RISC / SIMD / VLIW / DSP and the like, a multi-round iteration precision improvement and temporary register optimization allocation strategy is adopted, differential generation logic is formulated, and a high-precision low-redundancy instruction sequence is generated. The method comprises linear code scanning classification, reciprocal instruction and operand identification, cross-architecture generation logic rule formulation, instruction sequence generation and legality verification. Full-process automation is achieved, manual intervention is reduced, the execution efficiency and precision of reciprocal calculation of the heterogeneous processor are improved, and the method is suitable for embedded systems, high-performance calculation and other scenes.

Disclosed are an apparatus and method for monitoring the optimization performance of a deep learning compiler. The method includes calculating metric information for the evaluation of the performance of a compiler, calculating a score function value corresponding to resource optimization policy information, set in the artificial intelligence (AI)-based optimizer of the compiler, based on the metric information, and providing performance analysis results of the AI-based optimizer based on the score function value.

The invention provides a code analysis method, system and equipment based on a multi-programming language sandbox and a medium, and belongs to the technical field of code analysis and detection.The method specifically comprises the steps that an input code and a corresponding unit test sample are obtained, and a programming language type specified by the code is determined; sending the code and the unit test sample to a sub sandbox environment of a corresponding language for execution; a compiler in the sub sandbox reports a missing library according to a code compiling result and prompts a user to install the missing library; calling an analysis tool of a code analysis module to analyze the code; compiler feedback of the sub sandboxes and various analysis results generated by the code analysis module are integrated into a large language model; inputting the integration result into a large language model through a preset template; and analyzing and evaluating the code case based on the user instruction. Through multi-language sandbox isolation, automatic analysis tool integration and large language model enhancement, the security, efficiency and quality of a code processing flow are improved.

The invention provides a vector optimization algorithm translation method and device oriented to an RISC-V vector extension platform, and relates to the technical field of computer software cross-architecture translations. The method comprises the steps that source codes of vector optimization algorithms written by other platforms and translation cues are input into a large language model; outputting a translation code of a vector optimization algorithm oriented to the RISC-V vector extension platform; the translated codes are input into a compiler to be compiled; under the condition that compiling succeeds, a compiling product is linked to the test suite to obtain an executable program, and unit testing is conducted on the executable program on the RISC-V vector extension device; and under the condition that the unit test is passed, determining that the translation code is a first version of correct translation code of a vector optimization algorithm oriented to the RISC-V vector extension platform. According to the method, a vector optimization algorithm written by using a special vector language for other platforms is efficiently translated to the RISC-V vector extension platform.

This application provides a task processing method and chip, relating to the field of computer technology. The task processing method includes: placing all instructions in an instruction sequence used to implement a task into multiple instruction queues corresponding one-to-one with multiple execution units; determining the processing state of a second instruction queue that the first instruction queue depends on in the data dependency relationship indicated by the relation identifier based on a relation identifier corresponding to a restricted instruction at the head of a first instruction queue; and, if the processing state is complete, retrieving the restricted instruction corresponding to the relation identifier from the first instruction queue to execute the instructions following the restricted instruction; wherein the processing state is updated according to the relation identifier; and completing the processing of the multiple instruction queues to obtain the task processing result. This application can reduce the compiler burden when different tasks are executed asynchronously, improving task processing efficiency.

A graph-based representation of a source code program is generated in a background process of an edit session of a software development tool. The graph is used to facilitate the construction of a context for a prompt to a large language model that answers a user's query regarding the source code program in the edit session. The graph contains nodes that represent functions, macros, and types of the program and edges that depict a usage or definitional relationship between two connected nodes. The edges are generated from internal data structures generated from compiler-related analyses performed on the source code program in a background process. The graph is traversed to generate a sequence of code directives that provide the model with a structure of the source code program that includes data from the internal data structures not apparent from or contained in the source code program.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

The invention discloses an automatic debugging system and method for deep learning compiler numerical errors, and the system comprises a model analysis module, a semantic matching module, a tracking module and a verification module, the analysis module receives and analyzes a defect model with compilation errors, carries out the extraction of the input of the defect model, sub-functions, and operators of each sub-function, and carries out the verification of the compilation errors. Constructing a symbolic calculation graph and an index table before and after optimization of the defect model; the semantic matching module performs hash processing on each node in the symbolic calculation graph, matches equivalent nodes before and after optimization by comparing the approximation degree of hash values between the nodes, and generates a matching relationship between the nodes and the equivalent nodes; the tracking module compares the data streams of the models before and after optimization according to the matching relationship, generates an error cumulant diagram by tracking the generation and propagation process of errors, and locates the modes causing the errors and compiler optimization transformation causing mode rewriting; and the inspection module inspects the correctness of the positioning result and finally outputs root information after inspection. According to the method, each computing node of the neural network model is quantified into a hash value capable of measuring the distance, compared with an existing positioning technology, the method can better adapt to the scene of a complex deep learning model, and compared with an incremental debugging technology, the error positioning speed and accuracy are remarkably improved.

A system includes a substrate on which a first memory, a neural processing unit (NPU) including a plurality of processing elements (PEs) with multiplier-accumulator circuits, a controller, and a second memory, and a central processing unit (CPU) are disposed. The CPU may be configured to execute a universal compiler to perform a conversion for a particular neural network model into a machine code executable by the NPU and store the machine code in the first memory or the second memory. When the particular neural network model, generated by one among a plurality of machine learning frameworks that are incompatible with each other, is received and stored in the first memory, the universal compiler may perform the conversion based on mapping information indicating mapping between elements of machine learning frameworks and functions or operations executable by the CPU or NPU.

The invention discloses a device and a method for deploying DeepSeek. The device comprises a Weixin H8000 processor, a SW A1 accelerator card, an AI third-party library, an acceleration library, basic software, a compiler, a compiling framework and a DeepSeek large model. The Weixin H8000 processor serves as a core computing unit and is responsible for general computing and resource scheduling; the SW A1 acceleration card provides AI special computing power acceleration; the AI third-party library and the acceleration library optimize the algorithm execution efficiency; the basic software manages system resources; the compiler and the compiling framework are used for adapting software codes to domestic hardware; the DeepSeek large model serves as a top layer AI application, and all component resources of a bottom layer are called; the Weixin H8000 processor and the Shenwei A1 accelerator card construct a heterogeneous computing resource pool to integrate computing power, basic software performs unified scheduling, an AI acceleration library and a compilation framework optimize algorithm execution efficiency, an RDMA high-speed network improves data interaction performance, and a DeepSeek large model cooperatively calls computing power resources of all components to complete an AI computing task. The problem that networked artificial intelligence products lack privacy protection is solved.

Some embodiments construct a set of build dependencies for a program without a full set of build instructions. The build dependency set is constructed without piggy-backing on a build process that would produce an executable version of the program. Representations of the program's structure, such as expression types, call targets, symbol tables, abstract syntax trees, and other internal compiler data structures, are emitted to persistent non-volatile storage instead of being used only as intermediate steps for executable code generation. Security analysis can then utilize the program representations. Licensing analysis can also utilize the dependency set to identify program components and their storage locations.

The invention provides an equipment debugging system based on a serial port, which relates to the technical field of data processing, and comprises a server side and a client side which are in communication connection through the serial port, the server side comprises a memory, a command parser, a command distributor and a function executor; the memory is used for storing a debugging command registry; the command parser is used for parsing a protocol data packet which is transmitted through a serial port and comes from a client side, querying a debugging command registry and determining a debugging function corresponding to a command ID; the command distributor is used for distributing debugging functions to the function executor; the function executor is used for executing operation corresponding to the debugging function; the client side comprises a compiler, a description file analyzer and a graphical user interface; the compiler is used for generating a debugging description file after compiling the MCU program; the description file analyzer is used for analyzing the debugging description file, generating a protocol data packet and sending the protocol data packet to the server side through a serial port; the graphical user interface is used for displaying debugging information.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for compiler optimizations using a compiler optimization network. One of the methods includes receiving an input program, wherein the input program defines a graph of operation modules, wherein each node in the graph is a respective operation module, and each edge between nodes in the graph represents one operation module receiving the output generated by another operation module. The input program is processed by a compiler optimization network comprising a graph-embedding network that is configured to encode operation features and operation dependencies of the operation modules of the input program into a graph embedding representation and a policy network that is configured to generate an optimization action for each of one or more nodes encoded in the graph embedding representation. The compiler optimization network generates an output optimization plan comprising one or more optimization actions for the input program.

The invention discloses a real-time dynamic test optimization method for an embedded environment compiler, which belongs to the technical field of embedded systems and comprises the following steps of: acquiring and processing real-time dynamic data of the embedded environment compiler, and determining real-time dynamic characteristic data of the embedded environment compiler; building a real-time dynamic test identification model of the embedded environment compiler, analyzing the real-time dynamic characteristic data of the embedded environment compiler, automatically identifying potential defects of the embedded system, and determining a real-time dynamic test identification result of the embedded environment compiler; and formulating an embedded system optimization scheme to optimize the embedded system in time. The problems that the running test state of the embedded environment compiler cannot be dynamically monitored and analyzed, potential defects cannot be found and optimized in time, and the running efficiency of an embedded system is reduced in the prior art are solved. According to the method, the running test state of the embedded environment compiler can be dynamically monitored and analyzed, potential defects can be found and optimized in time, and the running efficiency of an embedded system is improved.

Systems and methods for using compiler transforms to transform a non-local function into a local function are disclosed. The systems and methods perform a dynamic inter-procedural analysis before performing reverse-mode automatic differentiation. The dynamic inter-procedural analysis is performed to determine a maximum set of computer program information. A non-local to local transformation is applied to the determined maximum set of computer program information, and each original instruction is mapped to an optic that is represented as an opaque closure in the transformed local function.

An image processing system includes one or more processors operative to receive a graph application programming interface (API) call to add a complex node to a graph. The graph includes at least the complex node connected to other nodes by edges that are directed and acyclic. The one or more processors are further operative to process, by a graph compiler at compile time, the complex node by iteratively expanding the complex node into multiple nodes with each node corresponding to one operation in an image processing pipeline. The system further includes one or more target devices to execute executable code compiled from each node to perform operations of the image processing pipeline. The system further includes memory to store the graph compiler and the executable code.

The invention provides an automatic design method and equipment of a storage circuit and a storage medium. The method comprises the following steps: acquiring demand parameters input by a user in a compiler; importing a plurality of circuit units after the standard memory circuit is disassembled into a compiler; determining a target circuit architecture according to the demand parameters; calling a plurality of corresponding circuit units from a compiler according to the demand parameters; and splicing the called circuit units to positions corresponding to the target circuit architecture to obtain a target storage circuit meeting the demand parameters. On this basis, the demand parameters of the user and the plurality of circuit units obtained by disassembling are input into the compiler, and the target circuit architecture is determined through the compiler, the plurality of corresponding circuit units are called, and the splicing of the plurality of circuit units is executed, that is, the whole design of the target storage circuit can be automatically completed in the compiler. The manual participation degree is reduced, the overall efficiency is high, the possibility of manual misjudgment can be completely eradicated, and the reliability of the whole circuit design is ensured.

The invention provides a large language model and semantic feedback iterative optimization process control program generation method, and belongs to the technical field of automatic control. And generating a preference data set through a compiler and semantic expert feedback, and performing model optimization by using the data set. The training bottleneck of a traditional data-driven model is avoided, and the generation capability of the model can be continuously optimized through dynamic adjustment and feedback under the condition of data scarcity; a dynamic iterative optimization mechanism is constructed by introducing the feedback of a compiler and a semantic expert, and the generated process control program can be checked and corrected in real time. The compiler feeds back to ensure the grammar correctness of the generated program, and a semantic expert evaluates from the aspects of logic and task intention. The problems of grammar errors and semantic mismatching in a traditional method are avoided. According to the method, the compiling passing rate and semantic accuracy of the process control program are effectively improved, and the quality and adaptability of the generated process control program are remarkably optimized.

The invention discloses a cross-language migration-based low-resource programming language corpus enhancement method, which comprises the following steps of: receiving a source language code, and driving a large language model to generate an initial target language code through a two-way retrieval mechanism fusing example guidance and knowledge constraint; secondly, constructing an automatic iterative repair closed loop by utilizing the feedback of a compiler, and carrying out self-correction on codes which fail to be compiled; thirdly, high-quality codes are screened out through automatic quality gating and fed back to a corpus and a knowledge base, and self-enhancement circulation of data and knowledge is formed; finally, the method further comprises an offline model evolution step based on grammar and semantic alignment driven by a compiler, a big language model is trained by collecting preference data generated by an online process, and the ability of the big language model to understand a target language is improved fundamentally. According to the method, the core problems of low quality, poor efficiency and lack of self-evolution ability of a low-resource programming language in code migration are solved.

The invention provides a deep learning compilation optimization method based on active transfer learning, and belongs to the field of deep learning compilation, and the method comprises the following steps: S1, generating operator scheduling, and extracting features as training data; the operator scheduling is to transform the data operation process of operators on deployment hardware; s2, selectively labeling data by adopting an active transfer learning method and pre-training the performance prediction model; the output of the performance prediction model is the expected time required for the operator to execute on the deployed hardware; s3, inputting an operator to be compiled, and performing automatic compiling by using the pre-trained performance prediction model; according to the method, an active transfer learning method is utilized to optimize the automatic compilation process of deep learning, so that the cross-hardware portability of a deep learning compiler is improved, and the deployment cost of a deep learning model on different hardware platforms is reduced.

The invention provides a storage unit type selection method and device, electronic equipment and a computer storage medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: establishing a storage unit specification general table which can be generated by a target compiler, wherein the specification general table comprises a plurality of sub-tables; receiving a target depth and a target bit width of the storage unit required by a user; respectively generating a candidate scheme capable of realizing a target depth and a target bit width based on each sub-table to obtain a plurality of groups of candidate schemes; on the basis of a preset model selection principle, determining the candidate schemes, which can be matched with the target depth and the target bit width in a splicing mode, in all the candidate schemes as feasible schemes; based on a preset back-end physical constraint condition, selecting a global optimal scheme from the feasible schemes; the compiling general table is established in advance, multiple sets of candidate schemes are automatically established for each sub-table in the compiling general table, then layer-by-layer screening is performed according to a preset rule to determine a global optimal scheme, and the layout efficiency is improved.

The invention relates to a quantum bit mapping method based on a cross-graph attention mechanism and a universal compiler, and the training method of a quantum bit mapping model based on the cross-graph attention mechanism comprises the steps: executing an intra-graph adjacency aggregation operation according to hardware node information in a hardware topological graph, and obtaining an updated hardware node vector; executing intra-graph adjacency aggregation operation according to logic node information in the quantum logic circuit to obtain an updated logic node vector; calculating the matching degree of the updated hardware node vector and the logic node vector, and performing cross-graph attention updating on the logic node vector and the hardware node vector based on the matching degree; inputting the hardware node vector and the logic node vector after pooling processing into a quantum bit mapping model to be trained, and outputting a mapping quality prediction value; and constructing a loss function based on the mapping quality true value and the mapping quality predicted value, and training a graph neural network model by adopting a gradient descent method. According to the method, the optimal path combination can be automatically selected to reduce the calculation complexity.

Systems and methods are provided that incorporate a compiler configured to convert interpreted language code (e.g., Python) into native machine code. According to some embodiments, the system generates the native machine code into a format that is consistent with known infrastructure. The native machine code can be converted into a format based on a low level virtual machine “LLVM” infrastructure. In various embodiments, the system enables a compiler framework that improves execution of code for interpreted languages. According to one embodiment, the system can be tailored for execution on specific processors, for example, a graphics processing unit (“GPU”) that is optimized for highly parallel computations.