929 results about "Compiler" patented technology

A method for using a compiler to modify prompts for MLMs used to generate database queries includes receiving, at a query compiler, a first query of a database. The first query is at least in part generated by an MLM. The method includes determining, by the query compiler, whether the first query comprises an uncorrectable error. The method includes, responsive to determining that the first query comprises an uncorrectable error, generating a prompt element that describes the uncorrectable error and that is structured for inclusion in a prompt requesting the MLM to generate a modified first query that corrects the uncorrectable error. The method may include generating the prompt for the MLM, providing the prompt to the MLM, and responsive to providing the prompt, receiving, at the database query compiler, the modified first query that corrects the uncorrectable error.

The invention relates to an automatic modeling agent system based on an MCP protocol and a large model, and the system comprises a multi-modal input interface module which is used for receiving, analyzing and standardizing modeling instructions or intention descriptions inputted by a user through different media to form structured feature representations; the semantic understanding central module is used for performing semantic analysis on the structured feature representation by using a pre-trained large language model and outputting a user modeling intention; the MCP instruction compiler module is used for converting a user modeling intention into an MCP instruction sequence following an MCP protocol; and the modeling execution engine module is used for analyzing and automatically executing the MCP instruction sequence to complete modeling of the target three-dimensional model. According to the method, three-dimensional modeling can be completed without knowing professional modeling terms and concepts by a user, and the modeling automation and intelligence level is greatly improved.

Apparatuses, systems, and techniques to select optimizations to be performed by compilers. In at least one embodiment, a processor includes one or more circuits to perform a compiler to select one or more optimizations to one or more first versions of a program based, at least in part, on a result of performing said one or more optimizations on one or more second versions of said program.

Apparatuses, systems, and techniques to perform one or more operations using a tensor. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to perform one or more operations using one or more tensors based on at least one or more indications of the plurality of operations by the API, one or more compiler options indicated by the API, and / or one of one or more indications of an amount of storage to be used to perform the one or more operations.

The invention discloses an automatic compiling and adapting method for an RISC-V extension instruction, and belongs to the technical field of compilers. According to the method, a dynamic DSL (Digital Subscriber Line) for registering a custom instruction, adding register use constraints and defining a specific code mode is designed. The LLVM plug-in is used for automatically integrating the registered custom instruction in the compiling process. The invention relates to a self-defined instruction rapid adaptation mechanism which is specially provided for a continuously provided RISC-V self-defined instruction expansion scene, and by automatically generating correct assembly codes of registered self-defined instructions, correct registers are automatically distributed and reserved according to register use constraints; the method comprises the following steps of: searching a defined specific code mode and semantics, and automatically generating and inserting a registered custom instruction in a program, so as to realize the rapid adaptation of a compiler to an RISC-V custom extension instruction and the automatic use of a program code to the custom instruction, and the whole process does not need a developer to manually modify the compiler or a program source code.

The invention discloses a program analysis method and device, a readable storage medium and electronic equipment. A to-be-analyzed program is determined, an abstract syntax tree of the to-be-analyzed program is determined through a compiler corresponding to a programming language used by the to-be-analyzed program, nodes in the abstract syntax tree are standardized, and a standard syntax tree is determined. And determining each control flow edge and each data flow edge in the standard syntax tree through the standard syntax tree, adding each control flow edge and each data flow edge to the standard syntax tree, and determining the code attribute graph of the program to be analyzed. The abstract syntax tree is converted into the standard syntax tree, the abstract syntax trees of the programs to be analyzed in different programming languages are unified, and the code attribute graph is constructed based on the standard syntax tree, so that the method can be suitable for program analysis of the programs to be analyzed in various programming languages; different analysis algorithms do not need to be developed for different programming languages, the program analysis efficiency is improved, and the development cost is reduced.

The invention relates to the technical field of artificial intelligence and software development, in particular to a context-aware code generation and real-time optimization method and system based on a large language model.The method comprises the following steps that a compiler front-end technology is utilized, input codes are analyzed, and an abstract syntax tree is constructed; function definition, variable declaration and statement block structure information are extracted through an abstract syntax tree, so that syntax and semantic structures of codes are obtained, and basic data support is provided for subsequent code generation and optimization; the method has the beneficial effects that the context graph covering grammar, semantics and runtime behaviors is constructed by fusing static grammar analysis (AST construction) and dynamic execution tracking (such as variable value change and function call time sequence), and the problem of context perception deficiency in a traditional code generation technology is solved. And the compatibility, the maintainability and the expandability of the generated code and the project architecture are improved.

In various examples, an interactive agent platform that hosts development and / or deployment of an interactive agent may provide an interpreter or compiler that interprets or executes code written in the interaction modeling language, and a designer may provide customized code written in the interaction modeling language for the interpreter to execute. The interaction modeling language may be used to define a flow of interactions that instruct the interpreter what actions or events to generate in response to a sequence of detected and / or executed human-machine interactions. The interaction categorization schema may classify interactions by standardized interaction modality and / or corresponding standardized action category. As such, a flow may be used to model an agent intent or inferred user intent, which a designer may use to build more complex interaction patterns with the interactive agent.

Embodiments of the invention provide a compiling method and apparatus, an electronic device and a readable storage medium. The method comprises the steps of converting a branch instruction in a target function into a control flow pseudo instruction related to an architecture of a compiler; performing a first instruction processing operation on any control flow pseudo instruction, and performing a second instruction processing operation on a vector instruction of which the operand type corresponding to the operand is a first preset type; and under the condition that the operand type corresponding to the operand of the control flow pseudo instruction or the vector instruction is a second preset type, determining a target physical predicate register and replacing the virtual predicate register corresponding to the control flow pseudo instruction or the vector instruction with the target physical predicate register. In this way, the number of the generated instructions is reduced, and the running efficiency of the program is improved to a certain extent. The target physical predicate registers are respectively distributed for different control flows, so that the overall execution efficiency of the program is improved, and the parallel execution capability and throughput of the program are improved.

The invention relates to a modeling and formalized verification method for cache consistency protocol verification, and the method comprises the steps: building a protocol model which comprises a plurality of processor nodes, directory nodes and a communication mechanism through a structured modeling mode, and constructing an asynchronous message mechanism to simulate disordered concurrent communication; protocol behavior rules such as processor requests, directory responses and network receiving are defined, protocol property invariants are set, semantic constraints such as data consistency, confirmation before writing and sharing state legality are covered, model verification is carried out in a state space traversal mode, breadth-first search and a symmetry recognition mechanism are supported, and the method is suitable for the protocol behavior rules. A protocol error or deadlock state is effectively found, a traceable error path is generated, a verifier can automatically generate source codes through a compiler and operate on a host platform, and rapid verification and result output of a protocol model are achieved. The method has good protocol adaptability and model reusability, and is suitable for formalized verification of various cache consistency protocols.

The invention relates to a large language model performance optimization method and device, computer equipment, a readable storage medium and a program product, and belongs to the technical field of deep learning model compilers. The method comprises the steps of obtaining data parameters and processing parameters of language data corresponding to a large language model; the processing parameters are determined according to parameters of to-be-deployed hardware corresponding to the large language model; in response to a programming operation aiming at a preset programming primitive, obtaining a target function representing arithmetic logic of the large language model; according to the data parameters and the processing parameters, compiling the target function to obtain a calculation graph corresponding to the target function; and according to the computational graph and the parameters of the to-be-deployed hardware, generating a plurality of target operators, and updating the large language model based on the plurality of target operators to obtain an optimized large language model. By adopting the method, the performance of the large language model can be improved.

According to the artificial intelligence-based compiler back-end development assisting method and device, fine tuning training is performed on an existing LLM, a large language model specially aiming at compiler back-end development optimization is obtained, and high-precision support can be provided for tasks such as code completion, generation and repair. A retrieval method is designed, an example most similar to user input can be automatically retrieved, and therefore the performance of LLM is improved in the environment that computing resources are limited. According to the method, the automation level of the rear-end development of the compiler is improved, the manual coding workload is reduced, the development efficiency is improved, and the learning cost of developers is reduced.

A method for automatically generating a compiled binary file with fault countermeasures includes compiling, by a compiler, a source code file to a first binary file; analyzing the first binary file to identify one or more fault vulnerabilities in the first binary file, wherein analyzing the first binary file to identify the one or more fault vulnerabilities includes: injecting a set of faults into the first binary file during a symbolic execution of the first binary file to generate a set of faulted states of the first binary file; and identifying the one or more fault vulnerabilities from the set of faulted states, wherein the one or more fault vulnerabilities are fault vulnerabilities that cause the first binary file to violate at least one security requirement; and compiling, by the compiler, the source code file to a second binary file, wherein the compiler inserts a set of fault countermeasures into the second binary file based on the identified one or more fault vulnerabilities, wherein the set of fault countermeasures protect the second binary file against the one or more fault vulnerabilities.

Modifications to existing computer hardware, compiler changes or source-to-source transforms performed during the software build process, and a collection of libraries and modifications to existing standard system software and libraries. The invention allows a program author to enforce various kinds of locality of causality in software to provide enforcement of boundaries for the following aspects of a computer program: control, space, time, modularity, reference, initialization, and mutability. Where these properties do not suffice to guarantee a property at static time, dynamic checks may be added and the constraints on control flow prevent such dynamic checks from being avoided by the program.

The invention relates to an anti-reverse confusion method and system for an end-side equipment deep learning model, and the core process comprises the steps: firstly inputting an original model obtained through the training of a model training frame into a deep learning compiling frame, and extracting three types of key information, namely, a model operator, a topological structure, parameters and dimensions, through the characteristics of a compiler; then constructing a feature analysis module to evaluate model features, dynamically matching a confusion scheme from a strategy library, and balancing safety and performance; the confusion module is embedded into a plurality of different levels such as a computational graph level, an operator template level and tensor intermediate expression through a hierarchical compiling mechanism, and a complex scheme can be jointly implemented across multiple levels; and finally, the compiler synchronously completes confusion reinforcement when generating the target code. According to the method, hardware adaptation is not needed, low-overhead confusion is achieved through a native pass mechanism of a compiler, fine-grained customized protection is supported, a model structure, parameters and computational logic can be effectively hidden, reverse engineering attacks can be resisted, and the method is particularly suitable for end-side equipment scenes with limited computing power.

The invention discloses a reciprocal calculation instruction sequence generation method oriented to a heterogeneous processor, and belongs to the field of compilation optimization and code generation. Aiming at the problems of instruction redundancy, weak precision control, poor hardware adaptation and high manual dependence of an existing method in a heterogeneous environment, characteristics of a reciprocal instruction and an operand are accurately identified by linearly scanning heterogeneous object codes (including vectorization, scalar and complex instruction sequences); in combination with hardware characteristics of RISC / SIMD / VLIW / DSP and the like, a multi-round iteration precision improvement and temporary register optimization allocation strategy is adopted, differential generation logic is formulated, and a high-precision low-redundancy instruction sequence is generated. The method comprises linear code scanning classification, reciprocal instruction and operand identification, cross-architecture generation logic rule formulation, instruction sequence generation and legality verification. Full-process automation is achieved, manual intervention is reduced, the execution efficiency and precision of reciprocal calculation of the heterogeneous processor are improved, and the method is suitable for embedded systems, high-performance calculation and other scenes.

Disclosed are an apparatus and method for monitoring the optimization performance of a deep learning compiler. The method includes calculating metric information for the evaluation of the performance of a compiler, calculating a score function value corresponding to resource optimization policy information, set in the artificial intelligence (AI)-based optimizer of the compiler, based on the metric information, and providing performance analysis results of the AI-based optimizer based on the score function value.

The invention provides a compiler software design method and system supporting multiple memory IP generation, and relates to the technical field of compilers, and the method comprises the steps: calling a corresponding memory IP template file according to memory IP parameters, and based on the memory IP template file, adopting a placeholder replacement mode, filling the corresponding positions of the Verilog code with the memory capacity, the memory frequency and the memory bit width to generate a Verilog source file; calling a Verilog compiler, performing grammar check on the Verilog source file, and generating a netlist file of a memory IP; calling a time sequence constraint file based on the netlist file, performing time sequence constraint and physical constraint, and generating a layout design file of the memory IP; packaging parameters input by a user are received, a packaging script is called, the layout design file and the packaging parameters are input into the packaging script, a GDSII file of the memory IP is generated, and layout and wiring of the memory IP are completed.

The invention provides a code analysis method, system and equipment based on a multi-programming language sandbox and a medium, and belongs to the technical field of code analysis and detection.The method specifically comprises the steps that an input code and a corresponding unit test sample are obtained, and a programming language type specified by the code is determined; sending the code and the unit test sample to a sub sandbox environment of a corresponding language for execution; a compiler in the sub sandbox reports a missing library according to a code compiling result and prompts a user to install the missing library; calling an analysis tool of a code analysis module to analyze the code; compiler feedback of the sub sandboxes and various analysis results generated by the code analysis module are integrated into a large language model; inputting the integration result into a large language model through a preset template; and analyzing and evaluating the code case based on the user instruction. Through multi-language sandbox isolation, automatic analysis tool integration and large language model enhancement, the security, efficiency and quality of a code processing flow are improved.

The invention provides a vector optimization algorithm translation method and device oriented to an RISC-V vector extension platform, and relates to the technical field of computer software cross-architecture translations. The method comprises the steps that source codes of vector optimization algorithms written by other platforms and translation cues are input into a large language model; outputting a translation code of a vector optimization algorithm oriented to the RISC-V vector extension platform; the translated codes are input into a compiler to be compiled; under the condition that compiling succeeds, a compiling product is linked to the test suite to obtain an executable program, and unit testing is conducted on the executable program on the RISC-V vector extension device; and under the condition that the unit test is passed, determining that the translation code is a first version of correct translation code of a vector optimization algorithm oriented to the RISC-V vector extension platform. According to the method, a vector optimization algorithm written by using a special vector language for other platforms is efficiently translated to the RISC-V vector extension platform.

This application provides a task processing method and chip, relating to the field of computer technology. The task processing method includes: placing all instructions in an instruction sequence used to implement a task into multiple instruction queues corresponding one-to-one with multiple execution units; determining the processing state of a second instruction queue that the first instruction queue depends on in the data dependency relationship indicated by the relation identifier based on a relation identifier corresponding to a restricted instruction at the head of a first instruction queue; and, if the processing state is complete, retrieving the restricted instruction corresponding to the relation identifier from the first instruction queue to execute the instructions following the restricted instruction; wherein the processing state is updated according to the relation identifier; and completing the processing of the multiple instruction queues to obtain the task processing result. This application can reduce the compiler burden when different tasks are executed asynchronously, improving task processing efficiency.

Apparatuses, systems, and techniques to identify instructions for advanced execution. In at least one embodiment, a processor performs one or more instructions that have been identified by a compiler to be speculatively performed in parallel.

A graph-based representation of a source code program is generated in a background process of an edit session of a software development tool. The graph is used to facilitate the construction of a context for a prompt to a large language model that answers a user's query regarding the source code program in the edit session. The graph contains nodes that represent functions, macros, and types of the program and edges that depict a usage or definitional relationship between two connected nodes. The edges are generated from internal data structures generated from compiler-related analyses performed on the source code program in a background process. The graph is traversed to generate a sequence of code directives that provide the model with a structure of the source code program that includes data from the internal data structures not apparent from or contained in the source code program.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

The invention discloses an automatic debugging system and method for deep learning compiler numerical errors, and the system comprises a model analysis module, a semantic matching module, a tracking module and a verification module, the analysis module receives and analyzes a defect model with compilation errors, carries out the extraction of the input of the defect model, sub-functions, and operators of each sub-function, and carries out the verification of the compilation errors. Constructing a symbolic calculation graph and an index table before and after optimization of the defect model; the semantic matching module performs hash processing on each node in the symbolic calculation graph, matches equivalent nodes before and after optimization by comparing the approximation degree of hash values between the nodes, and generates a matching relationship between the nodes and the equivalent nodes; the tracking module compares the data streams of the models before and after optimization according to the matching relationship, generates an error cumulant diagram by tracking the generation and propagation process of errors, and locates the modes causing the errors and compiler optimization transformation causing mode rewriting; and the inspection module inspects the correctness of the positioning result and finally outputs root information after inspection. According to the method, each computing node of the neural network model is quantified into a hash value capable of measuring the distance, compared with an existing positioning technology, the method can better adapt to the scene of a complex deep learning model, and compared with an incremental debugging technology, the error positioning speed and accuracy are remarkably improved.

A system includes a substrate on which a first memory, a neural processing unit (NPU) including a plurality of processing elements (PEs) with multiplier-accumulator circuits, a controller, and a second memory, and a central processing unit (CPU) are disposed. The CPU may be configured to execute a universal compiler to perform a conversion for a particular neural network model into a machine code executable by the NPU and store the machine code in the first memory or the second memory. When the particular neural network model, generated by one among a plurality of machine learning frameworks that are incompatible with each other, is received and stored in the first memory, the universal compiler may perform the conversion based on mapping information indicating mapping between elements of machine learning frameworks and functions or operations executable by the CPU or NPU.

Embodiments herein describe using template files for translating an existing (or base) AI model into a new AI model for a model-specific chipset. That is, instead of requiring a developer to use an AI framework to prepare new code for the new AI model, a compiler can receive a template file which indicates a base AI model (e.g., an AI model that has already been executed on the model-specific chipset) and structural parameters for the new AI model. The compiler can use the structural parameters to modify compilation data corresponding to the base AI model. The compiler can then use the modified compilation data to create code for the new AI model that executes on the model-specific chipset.

The invention discloses a device and a method for deploying DeepSeek. The device comprises a Weixin H8000 processor, a SW A1 accelerator card, an AI third-party library, an acceleration library, basic software, a compiler, a compiling framework and a DeepSeek large model. The Weixin H8000 processor serves as a core computing unit and is responsible for general computing and resource scheduling; the SW A1 acceleration card provides AI special computing power acceleration; the AI third-party library and the acceleration library optimize the algorithm execution efficiency; the basic software manages system resources; the compiler and the compiling framework are used for adapting software codes to domestic hardware; the DeepSeek large model serves as a top layer AI application, and all component resources of a bottom layer are called; the Weixin H8000 processor and the Shenwei A1 accelerator card construct a heterogeneous computing resource pool to integrate computing power, basic software performs unified scheduling, an AI acceleration library and a compilation framework optimize algorithm execution efficiency, an RDMA high-speed network improves data interaction performance, and a DeepSeek large model cooperatively calls computing power resources of all components to complete an AI computing task. The problem that networked artificial intelligence products lack privacy protection is solved.

Templates may be generated for exploring models with discrete random variable distributions. Models may be received at a compiler that includes a description or translates to a Directed Acyclical Graph (DAG) that represents a probabilistic model, including one or more random variables. Traces starting from the one or more random variables and leading to a node in the DAG may be generated to convert into a set of groups of traces. Individual traces may be sorted in the groups of traces according to dependencies between traces in the groups of traces and code templates generated that explore a state space of possible sample values drawn from the one or more random variables.

Some embodiments construct a set of build dependencies for a program without a full set of build instructions. The build dependency set is constructed without piggy-backing on a build process that would produce an executable version of the program. Representations of the program's structure, such as expression types, call targets, symbol tables, abstract syntax trees, and other internal compiler data structures, are emitted to persistent non-volatile storage instead of being used only as intermediate steps for executable code generation. Security analysis can then utilize the program representations. Licensing analysis can also utilize the dependency set to identify program components and their storage locations.