657 results about "Compiler" patented technology

Apparatuses, systems, and techniques to select optimizations to be performed by compilers. In at least one embodiment, a processor includes one or more circuits to perform a compiler to select one or more optimizations to one or more first versions of a program based, at least in part, on a result of performing said one or more optimizations on one or more second versions of said program.

The invention discloses an automatic compiling and adapting method for an RISC-V extension instruction, and belongs to the technical field of compilers. According to the method, a dynamic DSL (Digital Subscriber Line) for registering a custom instruction, adding register use constraints and defining a specific code mode is designed. The LLVM plug-in is used for automatically integrating the registered custom instruction in the compiling process. The invention relates to a self-defined instruction rapid adaptation mechanism which is specially provided for a continuously provided RISC-V self-defined instruction expansion scene, and by automatically generating correct assembly codes of registered self-defined instructions, correct registers are automatically distributed and reserved according to register use constraints; the method comprises the following steps of: searching a defined specific code mode and semantics, and automatically generating and inserting a registered custom instruction in a program, so as to realize the rapid adaptation of a compiler to an RISC-V custom extension instruction and the automatic use of a program code to the custom instruction, and the whole process does not need a developer to manually modify the compiler or a program source code.

The invention relates to a modeling and formalized verification method for cache consistency protocol verification, and the method comprises the steps: building a protocol model which comprises a plurality of processor nodes, directory nodes and a communication mechanism through a structured modeling mode, and constructing an asynchronous message mechanism to simulate disordered concurrent communication; protocol behavior rules such as processor requests, directory responses and network receiving are defined, protocol property invariants are set, semantic constraints such as data consistency, confirmation before writing and sharing state legality are covered, model verification is carried out in a state space traversal mode, breadth-first search and a symmetry recognition mechanism are supported, and the method is suitable for the protocol behavior rules. A protocol error or deadlock state is effectively found, a traceable error path is generated, a verifier can automatically generate source codes through a compiler and operate on a host platform, and rapid verification and result output of a protocol model are achieved. The method has good protocol adaptability and model reusability, and is suitable for formalized verification of various cache consistency protocols.

The invention discloses a reciprocal calculation instruction sequence generation method oriented to a heterogeneous processor, and belongs to the field of compilation optimization and code generation. Aiming at the problems of instruction redundancy, weak precision control, poor hardware adaptation and high manual dependence of an existing method in a heterogeneous environment, characteristics of a reciprocal instruction and an operand are accurately identified by linearly scanning heterogeneous object codes (including vectorization, scalar and complex instruction sequences); in combination with hardware characteristics of RISC / SIMD / VLIW / DSP and the like, a multi-round iteration precision improvement and temporary register optimization allocation strategy is adopted, differential generation logic is formulated, and a high-precision low-redundancy instruction sequence is generated. The method comprises linear code scanning classification, reciprocal instruction and operand identification, cross-architecture generation logic rule formulation, instruction sequence generation and legality verification. Full-process automation is achieved, manual intervention is reduced, the execution efficiency and precision of reciprocal calculation of the heterogeneous processor are improved, and the method is suitable for embedded systems, high-performance calculation and other scenes.

Disclosed are an apparatus and method for monitoring the optimization performance of a deep learning compiler. The method includes calculating metric information for the evaluation of the performance of a compiler, calculating a score function value corresponding to resource optimization policy information, set in the artificial intelligence (AI)-based optimizer of the compiler, based on the metric information, and providing performance analysis results of the AI-based optimizer based on the score function value.

The invention provides a code analysis method, system and equipment based on a multi-programming language sandbox and a medium, and belongs to the technical field of code analysis and detection.The method specifically comprises the steps that an input code and a corresponding unit test sample are obtained, and a programming language type specified by the code is determined; sending the code and the unit test sample to a sub sandbox environment of a corresponding language for execution; a compiler in the sub sandbox reports a missing library according to a code compiling result and prompts a user to install the missing library; calling an analysis tool of a code analysis module to analyze the code; compiler feedback of the sub sandboxes and various analysis results generated by the code analysis module are integrated into a large language model; inputting the integration result into a large language model through a preset template; and analyzing and evaluating the code case based on the user instruction. Through multi-language sandbox isolation, automatic analysis tool integration and large language model enhancement, the security, efficiency and quality of a code processing flow are improved.

This application provides a task processing method and chip, relating to the field of computer technology. The task processing method includes: placing all instructions in an instruction sequence used to implement a task into multiple instruction queues corresponding one-to-one with multiple execution units; determining the processing state of a second instruction queue that the first instruction queue depends on in the data dependency relationship indicated by the relation identifier based on a relation identifier corresponding to a restricted instruction at the head of a first instruction queue; and, if the processing state is complete, retrieving the restricted instruction corresponding to the relation identifier from the first instruction queue to execute the instructions following the restricted instruction; wherein the processing state is updated according to the relation identifier; and completing the processing of the multiple instruction queues to obtain the task processing result. This application can reduce the compiler burden when different tasks are executed asynchronously, improving task processing efficiency.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

A system includes a substrate on which a first memory, a neural processing unit (NPU) including a plurality of processing elements (PEs) with multiplier-accumulator circuits, a controller, and a second memory, and a central processing unit (CPU) are disposed. The CPU may be configured to execute a universal compiler to perform a conversion for a particular neural network model into a machine code executable by the NPU and store the machine code in the first memory or the second memory. When the particular neural network model, generated by one among a plurality of machine learning frameworks that are incompatible with each other, is received and stored in the first memory, the universal compiler may perform the conversion based on mapping information indicating mapping between elements of machine learning frameworks and functions or operations executable by the CPU or NPU.

The invention discloses a device and a method for deploying DeepSeek. The device comprises a Weixin H8000 processor, a SW A1 accelerator card, an AI third-party library, an acceleration library, basic software, a compiler, a compiling framework and a DeepSeek large model. The Weixin H8000 processor serves as a core computing unit and is responsible for general computing and resource scheduling; the SW A1 acceleration card provides AI special computing power acceleration; the AI third-party library and the acceleration library optimize the algorithm execution efficiency; the basic software manages system resources; the compiler and the compiling framework are used for adapting software codes to domestic hardware; the DeepSeek large model serves as a top layer AI application, and all component resources of a bottom layer are called; the Weixin H8000 processor and the Shenwei A1 accelerator card construct a heterogeneous computing resource pool to integrate computing power, basic software performs unified scheduling, an AI acceleration library and a compilation framework optimize algorithm execution efficiency, an RDMA high-speed network improves data interaction performance, and a DeepSeek large model cooperatively calls computing power resources of all components to complete an AI computing task. The problem that networked artificial intelligence products lack privacy protection is solved.

Some embodiments construct a set of build dependencies for a program without a full set of build instructions. The build dependency set is constructed without piggy-backing on a build process that would produce an executable version of the program. Representations of the program's structure, such as expression types, call targets, symbol tables, abstract syntax trees, and other internal compiler data structures, are emitted to persistent non-volatile storage instead of being used only as intermediate steps for executable code generation. Security analysis can then utilize the program representations. Licensing analysis can also utilize the dependency set to identify program components and their storage locations.

The invention provides an equipment debugging system based on a serial port, which relates to the technical field of data processing, and comprises a server side and a client side which are in communication connection through the serial port, the server side comprises a memory, a command parser, a command distributor and a function executor; the memory is used for storing a debugging command registry; the command parser is used for parsing a protocol data packet which is transmitted through a serial port and comes from a client side, querying a debugging command registry and determining a debugging function corresponding to a command ID; the command distributor is used for distributing debugging functions to the function executor; the function executor is used for executing operation corresponding to the debugging function; the client side comprises a compiler, a description file analyzer and a graphical user interface; the compiler is used for generating a debugging description file after compiling the MCU program; the description file analyzer is used for analyzing the debugging description file, generating a protocol data packet and sending the protocol data packet to the server side through a serial port; the graphical user interface is used for displaying debugging information.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for compiler optimizations using a compiler optimization network. One of the methods includes receiving an input program, wherein the input program defines a graph of operation modules, wherein each node in the graph is a respective operation module, and each edge between nodes in the graph represents one operation module receiving the output generated by another operation module. The input program is processed by a compiler optimization network comprising a graph-embedding network that is configured to encode operation features and operation dependencies of the operation modules of the input program into a graph embedding representation and a policy network that is configured to generate an optimization action for each of one or more nodes encoded in the graph embedding representation. The compiler optimization network generates an output optimization plan comprising one or more optimization actions for the input program.

The invention discloses a real-time dynamic test optimization method for an embedded environment compiler, which belongs to the technical field of embedded systems and comprises the following steps of: acquiring and processing real-time dynamic data of the embedded environment compiler, and determining real-time dynamic characteristic data of the embedded environment compiler; building a real-time dynamic test identification model of the embedded environment compiler, analyzing the real-time dynamic characteristic data of the embedded environment compiler, automatically identifying potential defects of the embedded system, and determining a real-time dynamic test identification result of the embedded environment compiler; and formulating an embedded system optimization scheme to optimize the embedded system in time. The problems that the running test state of the embedded environment compiler cannot be dynamically monitored and analyzed, potential defects cannot be found and optimized in time, and the running efficiency of an embedded system is reduced in the prior art are solved. According to the method, the running test state of the embedded environment compiler can be dynamically monitored and analyzed, potential defects can be found and optimized in time, and the running efficiency of an embedded system is improved.

An image processing system includes one or more processors operative to receive a graph application programming interface (API) call to add a complex node to a graph. The graph includes at least the complex node connected to other nodes by edges that are directed and acyclic. The one or more processors are further operative to process, by a graph compiler at compile time, the complex node by iteratively expanding the complex node into multiple nodes with each node corresponding to one operation in an image processing pipeline. The system further includes one or more target devices to execute executable code compiled from each node to perform operations of the image processing pipeline. The system further includes memory to store the graph compiler and the executable code.

The invention provides an automatic design method and equipment of a storage circuit and a storage medium. The method comprises the following steps: acquiring demand parameters input by a user in a compiler; importing a plurality of circuit units after the standard memory circuit is disassembled into a compiler; determining a target circuit architecture according to the demand parameters; calling a plurality of corresponding circuit units from a compiler according to the demand parameters; and splicing the called circuit units to positions corresponding to the target circuit architecture to obtain a target storage circuit meeting the demand parameters. On this basis, the demand parameters of the user and the plurality of circuit units obtained by disassembling are input into the compiler, and the target circuit architecture is determined through the compiler, the plurality of corresponding circuit units are called, and the splicing of the plurality of circuit units is executed, that is, the whole design of the target storage circuit can be automatically completed in the compiler. The manual participation degree is reduced, the overall efficiency is high, the possibility of manual misjudgment can be completely eradicated, and the reliability of the whole circuit design is ensured.

The invention provides a large language model and semantic feedback iterative optimization process control program generation method, and belongs to the technical field of automatic control. And generating a preference data set through a compiler and semantic expert feedback, and performing model optimization by using the data set. The training bottleneck of a traditional data-driven model is avoided, and the generation capability of the model can be continuously optimized through dynamic adjustment and feedback under the condition of data scarcity; a dynamic iterative optimization mechanism is constructed by introducing the feedback of a compiler and a semantic expert, and the generated process control program can be checked and corrected in real time. The compiler feeds back to ensure the grammar correctness of the generated program, and a semantic expert evaluates from the aspects of logic and task intention. The problems of grammar errors and semantic mismatching in a traditional method are avoided. According to the method, the compiling passing rate and semantic accuracy of the process control program are effectively improved, and the quality and adaptability of the generated process control program are remarkably optimized.

The invention discloses a cross-language migration-based low-resource programming language corpus enhancement method, which comprises the following steps of: receiving a source language code, and driving a large language model to generate an initial target language code through a two-way retrieval mechanism fusing example guidance and knowledge constraint; secondly, constructing an automatic iterative repair closed loop by utilizing the feedback of a compiler, and carrying out self-correction on codes which fail to be compiled; thirdly, high-quality codes are screened out through automatic quality gating and fed back to a corpus and a knowledge base, and self-enhancement circulation of data and knowledge is formed; finally, the method further comprises an offline model evolution step based on grammar and semantic alignment driven by a compiler, a big language model is trained by collecting preference data generated by an online process, and the ability of the big language model to understand a target language is improved fundamentally. According to the method, the core problems of low quality, poor efficiency and lack of self-evolution ability of a low-resource programming language in code migration are solved.

The invention provides a deep learning compilation optimization method based on active transfer learning, and belongs to the field of deep learning compilation, and the method comprises the following steps: S1, generating operator scheduling, and extracting features as training data; the operator scheduling is to transform the data operation process of operators on deployment hardware; s2, selectively labeling data by adopting an active transfer learning method and pre-training the performance prediction model; the output of the performance prediction model is the expected time required for the operator to execute on the deployed hardware; s3, inputting an operator to be compiled, and performing automatic compiling by using the pre-trained performance prediction model; according to the method, an active transfer learning method is utilized to optimize the automatic compilation process of deep learning, so that the cross-hardware portability of a deep learning compiler is improved, and the deployment cost of a deep learning model on different hardware platforms is reduced.

The invention provides a storage unit type selection method and device, electronic equipment and a computer storage medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: establishing a storage unit specification general table which can be generated by a target compiler, wherein the specification general table comprises a plurality of sub-tables; receiving a target depth and a target bit width of the storage unit required by a user; respectively generating a candidate scheme capable of realizing a target depth and a target bit width based on each sub-table to obtain a plurality of groups of candidate schemes; on the basis of a preset model selection principle, determining the candidate schemes, which can be matched with the target depth and the target bit width in a splicing mode, in all the candidate schemes as feasible schemes; based on a preset back-end physical constraint condition, selecting a global optimal scheme from the feasible schemes; the compiling general table is established in advance, multiple sets of candidate schemes are automatically established for each sub-table in the compiling general table, then layer-by-layer screening is performed according to a preset rule to determine a global optimal scheme, and the layout efficiency is improved.

Systems and methods are provided that incorporate a compiler configured to convert interpreted language code (e.g., Python) into native machine code. According to some embodiments, the system generates the native machine code into a format that is consistent with known infrastructure. The native machine code can be converted into a format based on a low level virtual machine “LLVM” infrastructure. In various embodiments, the system enables a compiler framework that improves execution of code for interpreted languages. According to one embodiment, the system can be tailored for execution on specific processors, for example, a graphics processing unit (“GPU”) that is optimized for highly parallel computations.

This disclosure presents a technique for enhancing the performance of models such as large multimodal models (LMMs) without retraining or fine-tuning. This technique includes an iterative refinement process implemented by three main components: a forward generator, a backward generator, and a discriminator. The forward generator translates a prompt into an output in a different modality, the backward generator translates this output back into the original modality, and the discriminator compares the prompt and the translated prompt to generate a hint for refining the prompt to reduce differences. This cycle continues until the original prompt and the translated prompt match, achieving cycle consistency. The solution offers several advantages, including improving model performance without the need for costly fine-tuning, training data, or expertise. It simplifies system complexity by not relying on external environments like compilers and APIs and uses cycle consistency as a supervisory signal to iteratively refine a prompt.

The invention relates to an NUP-based intelligent control system for a thermal power plant, which combines a DCS with an NPU to construct a novel thermal power control system comprising a control layer, a calculation layer, a communication layer and a management layer. In a calculation layer, traditional control logic is executed in a DCS, and advanced algorithms such as artificial intelligence and the like are executed by an NPU acceleration module; a general compiler is adopted to support a mainstream programming language to construct an algorithm library, and a deep learning framework is combined to improve a function; the data management uses a lightweight database; and the communication layer adopts a high-speed industrial Ethernet and is compatible with a mainstream protocol to realize data interaction. According to the scheme, the defects of insufficient response speed, algorithm processing capability and parallel operation capability when a traditional DCS deals with the problems of new energy fluctuation and the like are solved, and the effects of improving the flexibility and stability of a unit, improving the calculation speed of an AI algorithm, reducing the data query and extraction speed, realizing self-adaptive adjustment of control parameters of the unit and iterative optimization of performance are achieved. And the system has good compatibility and expansibility, and can be seamlessly connected with the existing DCS system.

A computer-implemented method for a machine learning based rules compiler, the method comprising receiving machine learning generated ripple down rules, the ripple down rules comprising exception rules for tags in a tag set, the exception rules comprising tag string comparisons. The method further comprises compiling the ripple down rules into optimized computer code. Compiling the rules into computer code further comprises generating an enumeration statement for an enumeration containing the tag set, translating the exception rules for each tag in the tag set into if-else statements for a respective tag, including replacing the tag string comparisons with the enumeration; and generating a switch case statement for a current tag, the switch case statement having cases corresponding the tags in the tag set and including the if-else statements for the respective tag. The optimized computer code comprises the enumeration statement and the switch case statement.

The invention discloses a Java-to-Cangjie code translation method based on a large model and compilation feedback, and particularly belongs to the technical field of software engineering program language processing, and the method comprises the following steps: step 1, performing structured semantic pre-training by constructing a grammar knowledge base of a target language, and injecting grammar prior knowledge of the target language; step 2, performing semantic enhanced supervision fine tuning training by constructing a high-quality data set containing semantic information, and enhancing semantic alignment and cross-language migration ability of the model; 3, introducing an AST structure perception embedded prompt mechanism in a parallel corpus supervision fine tuning training stage, and guiding the model to perform structure perception translation; and 4, establishing a compiler feedback repair loop, and iteratively correcting output based on error information to form a self-optimized closed-loop system. According to the method, an efficient training path is constructed, dependence on large-scale parallel corpora is effectively reduced, and an extensible and high-reliability technical path is provided for cross-language code translation of low-resource programming languages.

Aspects of the present disclosure relate generally to systems and methods for optimizing an implementation of a quantum chemistry task in a quantum circuit. The method includes obtaining a chemistry task presented as a Hamilton to implement in a Variational Quantum Eigensolver (VQE) circuit. The method also includes mapping the chemistry task to a qubit space of the VQE circuit with Unitary Coupled Cluster with Single and Double excitations (UCCSD) ansatz. The method also includes decomposing the fermionic excitations to Givens rotations and controlled-Z (CZ) gates by passing exponentiated Pauli forms in the VQE circuit to a cloud compiler. The method further includes after commuting the CZ gates through Givens rotations, cancelling the commuted CZ gates. The method further includes dropping CZ gates at the beginning and the end of the quantum circuit.

The invention provides a real-time incremental RAG method and system based on a dual-tense knowledge graph, and belongs to the technical field of artificial intelligence and knowledge graphs. The method comprises the following steps: through dual-tense decoupling modeling of event effective time and system input time, constructing a versioned knowledge graph and establishing a tense index; efficient retrieval is carried out by adopting a time sequence pruning algorithm based on indexes, and dynamic expansion of a graph pattern is realized through a declarative compiler; realizing abstract-free high-precision result sorting by utilizing a multi-modal concurrent retrieval and attention fusion mechanism; incremental updating of the knowledge graph is realized through streaming data processing and a distributed engine; and closed-loop optimization is formed according to user feedback. The system effectively solves the problems that a traditional RAG scheme is high in data updating delay, tense information is lost, retrieval efficiency is low and expansibility is poor, tense query accuracy, retrieval efficiency and system throughput are remarkably improved, and meanwhile operation and maintenance complexity is reduced.

A method, apparatus, and system are disclosed. The method includes constructing a static single assignment (SSA) form and a static single use (SSU) form for a program; setting a single-use disqualifying property locally for each SSU version, and propagating the single-use disqualifying property both forward and backward on an SSU graph uniquely formed from the constructed SSU form so it becomes a global property; transferring results from the SSU form to the SSA form to set a single-use property locally for each SSA version based on an occurrence of any use being associated with a disqualifying SSU version; performing data flow analysis on an SSA graph uniquely formed from the constructed SSA form so the single-use property becomes a global property to identify one or more definitions as dynamic single-use for variables in the program; and generating computer-readable instructions for executing the program based on the one or more definitions identified as dynamic single use for the variables in the program, wherein the one or more definitions identified as dynamic single-use has a defined value used exactly one time during execution of the program.

A compiler of a computing device is described that identifies a sequence of neural network models frequently invoked by an application of the computing device, compiles the models in that sequence, and loads a static random access memory (SRAM) of a hardware accelerator with the compiled models only when the same compiled models—from another, but same, sequence that was previously invoked—are not already present in the SRAM. This prevents unnecessary reloading of compiled models into the SRAM, thereby increasing runtime speed and conserving computational energy.