3results about How to "Speed ​​up the calculation process" patented technology

The present disclosure provides a sampling circuit, a control method and a hardware accelerator applied to a lattice cryptography algorithm, and relates to the technical field of post-quantum cryptography. The sampling circuit comprises a padding module configured to pad a seed according to a hash padding rule; a hash operation module configured to perform a hash operation on the padded seed to generate a pseudo-random sequence; a cache module configured to store the pseudo-random sequence generated by the hash operation module; and a sampling module configured to sample the pseudo-random sequence stored in the cache module to obtain a sampling result. The present disclosure provides the cache module, and in the sampling process, the cache module provides data for sampling to the sampling module without relying on the hash operation module to provide data. Therefore, the sampling module and the hash operation module in the present disclosure are independent of each other and can work simultaneously, thereby improving the operation efficiency of the sampling circuit and effectively accelerating the calculation process of the lattice cryptography algorithm.

The application provides an energy efficiency service deployment and delivery method and system for an edge computing network, and relates to the technical field of edge computing.The method comprises the following steps: extracting multi-dimensional service features, encoding and fusing the extracted multi-dimensional service features to generate a global context feature representation; combining system load dynamic prediction results to adaptively adjust an upper-layer decision time scale based on the global context feature representation; executing service deployment decisions and base station sleep / activation switching decisions under the adjusted upper-layer time scale; executing service delivery decisions and resource allocation decisions based on real-time service requests under a fine-grained lower-layer time scale; and coordinating the decision-making process through a double-time-scale hierarchical learning framework.The method can effectively reduce long-term network overhead, effectively respond to dynamic service requests, improve the processing capacity for time coupling relationships between deployment and delivery cycles, and reduce system costs.

The application provides a switch frequency determination method and device for an LCC resonant converter, the method comprising: obtaining an input voltage and an output voltage of the LCC resonant converter; determining a starting mode in which the LCC resonant converter is currently located by using the output voltage; determining a calculation program corresponding to the starting mode by using the starting mode in which the LCC resonant converter is currently located, wherein the calculation program is an operation logic program designed for the starting mode by using a field programmable logic gate array; inputting the input voltage and the output voltage into the field programmable logic gate array, and calculating the switch frequency of the LCC resonant converter by using the calculation program, so that the switch frequency determination method improves the adjustment rate of the switch frequency of the LCC resonant converter, the rising speed of the output voltage, and further improves the dynamic response speed of an existing power supply.