257 results about "Chip architecture" patented technology

The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.

A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suites, and makefiles. The standard library devices comprise an integrated CPU, a shared memory controller, a peripheral controller, system peripherals, a DMA controller, embedded memory, and general system control. CPU bridges are used to accommodate a variety of processor types and to insulate users from the complexities of interfacing to different kinds of processors. Such CPU bridges further allow the latest processors to be rapidly integrated into existing integration platforms and designs.

A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.

An architecture and a method for a cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables “cell-based” processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed-size “cells.” The fixed-sized cells are then processed and reassembled into packets. The cell-based packet processing architecture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet data or control parameters.

A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM cell and chip architecture. The SOT-MRAM chip architecture includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells. Each memory cell of the plurality of memory cells includes a MTJ and a selector element. These SOT-MRAM cells eliminate the need to pass large currents through the barrier layer of the MTJ and the selector element eliminates the large transistors usually required for selecting a single memory cell without disturbing neighboring memory cells.

An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture and storing corresponding diagnosis data which include an indication of the failure-causing test data and the corresponding test analysis data. Embodiments are provided which enable that the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test, together with respective diagnosis data.

A method, device, system, or article of manufacture is provided for low-power management of multiple sensor chip architecture. In one embodiment, a method comprises, at a computing device that includes a first processor, a second processor and a third processor, receiving, by the first processor, sensor data from a first sensor; determining, by the first processor, a movement by the computing device using the sensor data; receiving, by the first processor, a modality of the computing device; in response to determining that the modality corresponds to a predetermined state, determining, by the first processor, a modality move distance associated with the predetermined state; determining, by the first processor, a move distance of the computing device using the modality move distance; determining, by the first processor, that the move distance of the computing device is at least a move distance threshold; and, in response to determining that the move distance of the computing device is at least a move distance threshold, reporting, by the first processor, to at least one of the second processor and the third processor, that the move distance of the computing device is at least the move distance threshold.

The invention discloses a digital-analog hybrid neural network chip architecture. The architecture comprises a two-dimensional SRAM module, an analog synaptic circuit, a nerve cell circuit, an AER communication module, and a master control digital unit. The two-dimensional SRAM module is taken as a storage unit of neural network connection relation and a synaptic weight value. The analog synaptic circuit and the nerve cell circuit respectively consist of an MOSFET circuit working in a subthreshold section. The AER communication module serves as the input and output interfaces of a chip, and employs an AER protocol for communication. All control circuits in the architecture are synchronous digital circuits. The architecture is low in power consumption, is high in degree of parallelism, and can achieve a neural network algorithm in a reasonable chip area, wherein the neural network algorithm is more complex in nerve cell functions, is larger in network scale, and is more flexible in connection.

A method, device, system, or article of manufacture is provided for low-power management of multiple sensor chip architecture. In one embodiment, a method comprises, at a computing device that includes a first processor, a second processor and a third processor, receiving, at the first processor, first sensor data from a first sensor; determining, at the first processor, a motion state of the computing device using the first sensor data; in response to determining that the motion state corresponds to a predetermined motion state, activating the second processor; receiving, at the second processor, second sensor data from a second sensor; determining, by the second processor, that the motion state corresponds to the predetermined motion state using the second sensor data; and, in response to determining that the motion state corresponds to the predetermined motion state using the second sensor data, sending the motion state to the third processor.

A method of creating a unified chip involves performing front-end processing on a first wafer, the front end processing creating multiple devices on the wafer, performing back-end processing on a second wafer, the back end processing creating layers of interconnected metal traces arranged to interconnect at least some of the multiple devices to each other, and bonding the first wafer to the second wafer such that the multiple devices on the first wafer are interconnected to each other by the metal traces of the second wafer.

A memory package and a chip architecture which includes stacked multiple memory chips is described. In a first aspect, a memory package comprises a substrate and a plurality of memory dies mounted on the substrate. Each die has a separate chip enable. In a second aspect, a chip architecture comprises a printed circuit board (PCB). The PCB includes a footprint. The footprint includes at least one no connect (NC) pad. The chip architecture includes a plurality of stacked memory chips mounted on the printed circuit board. Each of the plurality of stacked memory has a chip enable signal pin and also has at least one NC pin. At least one of the plurality of stacked memory chips utilizes an NC pin of another of the stacked memory chips to route the chip enable pin to at least one NC pad of the footprint. Accordingly, a system and method in accordance with the present invention provides for increased memory density within a particular space constraint by (1) providing multiple dies in a single memory package and (2) by providing stacked memory chips in a single PCB footprint. In so doing, the package/PCB will have increased memory density over a conventional package/PCB within the same space constraints, and the capacity of Flash storage devices is expanded accordingly.

An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture. In particular, the provided approach enables the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test.

A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip/single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.

A depth of field imaging apparatus includes a light field imager and a time of flight imager combined in a single on-chip architecture. This hybrid device enables simultaneous capture of a light field image and a time of flight image of an object scene. Algorithms are described, which enable the simultaneous acquisition of light field images and a time of flight images. Associated hybrid pixel structures, device arrays (hybrid imaging systems), and device applications are disclosed.

The embodiment of the invention relates to a relay protection system and a special multi-core Soc chip architecture thereof. The special multi-core Soc chip architecture comprises a first dual-channelDDR, a second dual-channel DDR, a management processing core, a communication data processing core, a protection locking processing core, a protection logic processing core, a first secondary cache and a second secondary cache which are integrated on a chip. According to the special multi-core Soc chip architecture for the relay protection system, the four processing cores, the first dual-channelDDR, the second dual-channel DDR, the first secondary cache and the second secondary cache are integrally arranged on the chip, so that the original complex multi-chip hardware architecture is simplified; and low operation reliability and stability of the relay protection system caused by unstable connection of a multi-chip hardware structure are also avoided, and the operation reliability and stability of the relay protection system are improved. The technical problem that the operation stability and reliability of a relay protection product are influenced due to the fact that an existing relay protection multi-chip framework adopts a framework that a plurality of chips adopt a plurality of clamping plates and the multi-chip framework is complex is solved.