37 results about "Chip architecture" patented technology

The application discloses a kind of transmitter chip architecture of ultra-low area high output power, it is related to wireless communication circuit technical field.The architecture includes mutually coupled first single-core oscillator OSC1, second single-core oscillator OSC2, driving voltage synthesis transformer TFM1, power amplifier active core PA, output matching transformer TFM2 and parallel capacitor C1-C6.OSC1 and OSC2 are realized same frequency same phase oscillation by electrical or electromagnetic coupling, TFM1 is matched with C1-C4, and two-way oscillation voltage is superimposed in phase, generates amplitude doubling driving voltage, is directly input PA amplification, and is output after completing impedance matching by TFM2 and C5-C6 again.Compared with traditional oscillator, driving amplifier and power amplifier architecture, the application omits driving amplifier and interstage matching transformer, and the area of core circuit is ≤0.038mm 2 , output power reaches 13dBm, realizes the synergistic optimization of ultra-low area and high output power, and adapts miniaturization, high-performance communication demand.

The application belongs to the technical field of computer architecture design, and discloses a unified accelerator design method and accelerator for diversified graph computing applications, which comprises the following steps: by comparing and analyzing the field-specific execution model of classical graph computing applications, observing the common data flow abstraction of different graph computing applications, establishing a graph computing execution model based on a sparse matrix, and abstracting the common part of the graph computing algorithm; based on the sparse matrix execution model, by analyzing the common hardware features of classical graph computing applications such as graph traversal, graph mining and graph learning, a field general chip architecture for graph computing is constructed, and general and efficient support for complex real-world scenarios is realized; by proposing a graph computing instruction set for a "scalar-vector-graph" heterogeneous core, the programmability of the graph computing chip is improved.

This utility model relates to an ultra-wideband radar sensor chip architecture, including a signal generator, a transmit link, and a receive link. The signal generator generates a first clock signal and a second clock signal. The first clock signal is output to the transmit link, and the second clock signal is output to the receive link. The transmit link includes a first pulse generator, a differentiator, and a transmit multiplexer with multiple transmit branch channels. The receive link includes a second pulse generator, a mixer, a receive multiplexer with multiple receive branch channels, a low-pass filter, an automatic gain control amplifier, and an analog-to-digital converter. This ultra-wideband radar sensor chip architecture adopts a multi-transmit, multi-receive approach, allowing each channel to operate independently in a time-division multiplexing manner, improving radar detection accuracy and resolution, and significantly expanding the application range of radar sensors.

This invention discloses a communication gateway, data communication method, and vehicle control chip for inter-core collaboration, belonging to the field of vehicle diagnostic technology. The communication gateway is integrated into the diagnostic processing core. The diagnostic processing core and the bus communication core collaborate through the communication gateway. The communication gateway includes: an inter-core transparent transmission interface connected to the bus communication core, used to acquire the DoCAN data packet carrying the diagnostic request transmitted by the bus communication core when the CAN diagnostic instrument sends a diagnostic request via the CAN bus; and a first reassembly unit connected to the inter-core transparent transmission interface, used to parse the DoCAN data packet and reassemble it into a DoIP data packet; the reassembled DoIP data packet is sent to the diagnostic processing core for diagnostic processing. The beneficial effects of the above technical solution are: reliable transparent transmission of diagnostic data between dual cores in a multi-core heterogeneous SoC chip architecture, support for seamless conversion between dual bus protocols, and meeting the access requirements of diagnostic services under multiple protocols.

The application relates to the chip design technical field, in particular to a chip architecture with shareable storage and private storage. The chip architecture comprises: a plurality of physical storage arrays, each of which comprises a plurality of storage units, each of which can be configured as a storage unit in a shared storage area or a storage unit in a private storage area; a shared storage address conversion module for realizing conversion of a shared storage address into a physical storage address; a register address conversion module for realizing conversion of a register address into a physical storage address; and a judgment module, first and second input ends of the judgment module being connected with the shared storage address conversion module and the register address conversion module respectively, the judgment module being used for judging whether a received physical storage address is sent to a physical storage array according to the configuration of a storage unit corresponding to the received physical storage address. The application can realize flexible configuration of shared storage and private storage in a chip.

The application discloses a multi-dimensional multiplexing hybrid integrated photonic computing core particle system, which comprises a multi-wavelength light source, a wavelength division demultiplexer, a hybrid integrated photonic chip, a filter array and a photodetector array, wherein the multi-wavelength light source encodes a problem to be solved and generates a multi-wavelength encoded optical signal containing the problem to be solved; the wavelength division demultiplexer fans out the multi-wavelength encoded optical signal to different channels and injects the multi-wavelength encoded optical signal into the hybrid integrated photonic chip; the hybrid integrated photonic chip loads weights on the encoded optical signals in the multiple channels to realize multiplication operation, and the processed optical signals enter a femtosecond laser direct writing chip to realize three-dimensional evolution of the optical signals and generate all-optical computing result signals; the filter array selectively filters the all-optical computing result signals containing two computing results, and the computing results are obtained through photoelectric conversion and amplitude determination of the photodetector array. The application realizes distributed computing to effectively solve a complex graph problem through multi-dimensional super-multiplexing of wavelength, three-dimensional space, amplitude and time and combining with optical interconnection technology, dividing a large-scale graph into manageable paragraphs through a three-dimensional femtosecond photonic chip architecture, and distributing the paragraphs to multiple photonic chips, and each chip processes a specific part of the graph.

A method includes providing a first chip having a circuit element layer stack, the circuit element layer stack including a plurality of circuit elements distributed across a plurality of layers. The circuit element layer stack has a sacrificial material filling a space between the plurality of circuit elements in the plurality of layers and a coherent device layer disposed on the circuit element layer stack. The method includes removing the sacrificial material.

This application relates to the field of computer technology, providing a non-intrusive Linux memory barrier modification method and system. The method is applied to scenarios where an information system is migrated from a strong memory model chip architecture to a weak memory model chip architecture. Specifically, it includes: in the newly added adaptation layer, determining the target system calls invoked by the component layer, and constructing a rewritten function with the same name for each target system call. The rewritten function sequentially includes a first memory barrier instruction, an instruction to call the original target system call, and a second memory barrier instruction; compiling the rewritten function into a dynamic link library; and when the business process starts, preferentially loading the custom dynamic library by preloading environment variables to hijack system calls, so that the operating system's dynamic linker redirects the component layer's calls to the target system calls to the rewritten function. This application achieves complete decoupling of business logic and adaptation logic by implanting a memory barrier at the system call layer without modifying the business layer and component layer code.

In one embodiment, an integrated circuit package includes an assembly embedded in the package substrate, comprising a bridge die to interconnect multiple integrated circuit dies of the package and an interposer coupled to the bridge die. The interposer includes vias with a high aspect ratio (e.g., greater than 20:1) and may be made of glass. The assembly may be embedded in a core layer of the package substrate.

The application discloses a high-speed optical pulse neural network computing chip architecture for a classification task, comprising a signal loading unit, including a picosecond light source and a high-speed broadband modulator; the picosecond light source is coupled to an on-chip system and is encoded through the high-speed broadband modulator; a full connection unit distributes the encoded pulse signals to different neurons through a multilayer multimode interferometer, the synapses of the neurons are phase change material weight units, linear weighting of the pulse of each wavelength channel is carried out, and the activation unit of the neuron is realized by a graphene-silicon-based integrated photonic crystal microcavity; a wavelength division device is used to combine the output pulses of each neuron and input to a next full connection unit or an output unit; and the output unit outputs signals through connection to a high-speed detector. The application realizes all-optical computing, reduces the overall power consumption and delay of the network, and improves the integration of a single neuron.

The application discloses a kind of multi-protocol NFC identification and system integration management method, system and equipment.The method comprises: obtaining the physical layer protocol byte of card to be identified, parses the feature bit contained in response to select to determine chip architecture, and loads corresponding logic processing module to operate business application;During the operation of business application, system state parameters are configured based on system authority and key distribution events are intercepted, system interaction components are locked to establish the exclusive running environment of business application;Under the exclusive running environment, receive upgrade package and use hash algorithm to sample verification, after sampling verification, execute system image update, and issue firmware upgrade instruction to the peripheral hardware module obtained by executing physical layer protocol byte to realize firmware synchronous upgrade.The application significantly reduces the risk of terminal equipment misoperation exit, and ensures the safe integration management of the whole process of equipment multi-protocol identification and firmware upgrade through exclusive environment.

This invention discloses an optical quantum neural network computing system based on an optical non-Hermitian evolutionary system architecture, belonging to the field of optical quantum neural network computing technology. It includes an optical quantum processing chip system and a control circuit. The optical quantum processing chip system comprises a quantum light source, an integrated optical quantum computing chip, and a photoelectric processing system. An optical non-Hermitian evolutionary system architecture is integrated on the integrated optical quantum computing chip. This architecture includes a linear unitary transform region, a linear non-unitary transform region, and a nonlinear modulation region. The quantum light source generates quantum state light signals and inputs them to the integrated optical quantum computing chip. The signals are sequentially processed through the linear unitary transform region, the linear non-unitary transform region, and the nonlinear modulation region. The output light signal is read by the photoelectric processing system and returned to the control circuit. This invention achieves a highly efficient optical quantum neural network chip architecture, overcoming the bottleneck of traditional optical quantum neural networks' difficulty in cascading probabilistic gate circuits and nonlinear functions, and possesses the computational advantages of large-scale and deep networks.

This invention discloses a high-performance automotive-grade chip design method, a multi-domain fusion chip architecture, and a vehicle. Based on the functional requirements of the target vehicle, this invention divides the design into multiple independent functional control modules; integrates these multiple functional control modules into a single high-performance system-on-a-chip (SoC); establishes a sharing mechanism within the SoC for real-time data exchange between the multiple functional control modules; and uses a pre-defined packaging process to manufacture and package the designed chip, forming an automotive-grade chip product. This achieves centralized computing power and reduces overall size and weight, as well as the number of operating system maintenance requirements and application software splitting, through integration.

The application relates to the technical field of pulse neural network processing, in particular to a pulse neural network processor with a unified architecture, which comprises an LIF neuron module, a pulse collector module, an SRAM controller module, an SRAM module and a configuration module; the SRAM module comprises a weight SRAM, an entry SRAM and a neuron SRAM; the configuration module is used for realizing configuration of a chip architecture, and the configuration of the chip architecture comprises a sparse architecture and a dense architecture. The sparse architecture and the dense architecture can be simultaneously supported under the same chip architecture, storage and pulse driving calculation of the sparse architecture are used, lower task energy consumption can be realized when a sparse pulse neural network is processed, storage and matrix operation of the dense architecture are used, lower task energy consumption can be realized when a dense pulse neural network is processed, and the advantages of the two architectures can be combined in one chip.

This invention relates to the field of distributed quantum computing technology, and more particularly to a quantum circuit mapping method for distributed quantum computing architectures. It solves the problem of high communication overhead introduced by remote gate operations. The specific steps are as follows: Step S1: Constructing groups; Step S2: Constructing a complete interaction graph; After completing the qubit grouping, a unified model of cross-group interactions in the quantum circuit is performed at the group level; Step S3: Inputting the specific physical topology; Step S4: Subgraph isomorphic matching. The beneficial effects of this invention are: proactively reducing the risk of subsequent communication merging constraints during the mapping and grouping construction stages; achieving global communication cost optimization while satisfying logical communication structure constraints; and improving the versatility and scalability of the mapping and grouping method across different multi-chip architectures.

This invention discloses an implementation method for a universal test chip architecture compatible with multiple SerDes protocols, relating to the field of high-speed communication technology. The method includes: dynamically configuring the working mode of the SerDes IP core based on the target communication protocol and collecting multi-dimensional performance parameters; calling a performance analysis model to perform correlation analysis and generate anomaly diagnostic results containing root cause localization information; based on the target performance, using an optimization algorithm to intelligently search within the configurable parameter space of the SerDes IP core to obtain the optimal parameter combination; reconfiguring the SerDes IP core using the optimal parameter combination and performing verification tests. This invention achieves full-process coverage from automated testing and intelligent diagnosis to parameter optimization, improving the universality, intelligence level, and debugging efficiency of multi-protocol SerDes testing.

The utility model discloses a low power consumption device for mouse provides accurate matching working voltage through multichannel voltage conversion submodule in power management module, and combines the independent time-sharing control of each submodule power supply in sensor module, user input module to the multiple MOSFET switch pipe of power path control submodule realizes, and the static power consumption is reduced greatly, adopts the nRF54L15 main control chip of ultralow power consumption and CH32V305 auxiliary MCU chip architecture, and the cooperation processing is carried out through UART interface, and the task of high real -time requirement is handled by CH32V305 auxiliary MCU chip, so that nRF54L15 main control chip can long -term be in deep sleep mode, and only when the motion interruption of being PAW3950 optical sensor or user operation wakes up quick response, the wireless communication module of nRF54L15 main control chip internal integration supports bluetooth 5.4 and 2.4GHz dual mode wireless communication adopts low duty cycle working mode, and wireless transmission power consumption is further reduced.

Integrated circuit devices, methods, and circuitry for implementing multiple power domains and / or multiple die with power on reset operations are provided. Integrated circuitry may include circuitry that controls operations after a power on reset based on merge circuitry that propagates ready status signals throughout communication circuitry. Power policies may be used herein to control the operations, as well as control isolation circuitry when a respective power domain is powered down.

This invention discloses a simulation calibration method, apparatus, and storage medium for chip models, relating to the field of chip architecture simulation. The method includes: determining the simulation deviation of a specified functional dimension for each target computation graph node based on system-level and operator-level simulation results; filtering target functional dimensions from the specified functional dimensions based on the simulation deviation, and obtaining the parameter set associated with the target functional dimension in the target computation graph node; and performing hierarchical back-annotation on the parameter set based on the simulation deviation of the target functional dimension. The system-level simulation results are used to intelligently filter the operator-level simulation space, avoiding blind traversal of low-value, ineffective configurations. By introducing an error decomposition mechanism, the estimation error is attributed according to dimensions such as computation, memory access, communication, and power consumption, achieving targeted back-annotation instead of traditional global parameter fitting. The hierarchical back-annotation strategy reduces parameter interference between different operator families, enabling the model to adapt to various complex scenarios and avoiding parameter oscillations.

The application relates to an integrated ADS-B IN and Remote ID transceiving module and belongs to the low-altitude monitoring and communication field.The module comprises an ADS-B receiving SoC chip used for receiving and demodulating a 1090MHz ADS-B signal, a Remote ID chip used for broadcasting or receiving a Remote ID signal through a Wi-Fi or Bluetooth frequency band, a GNSS positioning module used for acquiring position and time information, a micro control unit MCU connected with the chips and modules respectively and used for data processing and protocol conversion, and a peripheral circuit comprising a filter, a matching network, a clock circuit, a reset circuit and a power supply conversion unit.The application realizes the ADS-B signal receiving and Remote ID signal transceiving functions of a single module through a double SoC chip architecture, supports independent battery power supply deployment or integration with a flight control, and has the advantages of high integration, low power consumption, small size and flexible deployment, can output fused airspace situation information through a single UART interface, and can be widely applied to low-altitude monitoring, sensing collision avoidance and flight supervision scenes of manned / unmanned aircrafts.

The application discloses a path-driven cleaning optimization method for a micro-fluidic lab-on-chip system, takes a sequence diagram of biochemical assay experiments, a chip architecture and an experiment scheduling strategy as input, calculates an execution program with a cleaning operation as output, minimizes the number of cleaning operations, the total length of a cleaning path and the total execution time of biochemical assay experiments, reduces the influence of the insertion of the cleaning operation on the biochemical assay experiments, and ensures the accuracy of experimental results.

The application relates to an HPLC+HRF dual-mode communication system and method, and belongs to the technical field of communication. The system uses a single micro control unit to replace a multi-chip architecture to dynamically manage hardware resources through a mathematical model, solves the problem of high hardware cost caused by integrating HPLC and HRF chips in a traditional dual-mode communication system, and has the advantages of low hardware cost and high resource utilization. The method is based on an environmental state principal vector, dynamically selects an optimal protocol through a mixed integer nonlinear programming and a variational Bayesian strategy, solves the problems of rigid protocol switching and low success rate of a traditional system in a complex power line environment, can improve the reliability and success rate of a communication link, and has noise identification and modulation mode self-adaptive capabilities.

This specification discloses an instruction decoding module and its generation method, apparatus, and chip architecture simulator. The method for generating the instruction decoding module provides a way to generate the module based on a two-level decoding table using a computing device. This reduces the manpower required and resource consumption during the development of microarchitecture hardware, thereby improving the development efficiency. Specifically, the method first determines the grouped feature codes corresponding to each code position in the instruction encoding from the instruction feature set. Then, it groups the instruction encodings in the two-level decoding table according to the grouped feature codes to obtain an encoding search tree. Finally, the instruction decoding module is generated based on this encoding search tree. The entire generation process is simple and improves the generation efficiency of the instruction decoding module.

A data processing device incorporates a plurality of chiplets having working elements such as processing and memory elements. At least one of the working elements is operative to generate messages directed to working elements of the same chiplet or another one of the chiplets. Each message includes a global address. An evaluation circuit determines whether the global address of a message is within a range of global addresses assigned to the chiplet. If so, the message passes to a translation circuit which translates the message to a local address for routing to a working element of the chiplet. If not, the message is dispatched to one or more other chiplets.

This invention discloses a SoC chip fault location system with adaptive test vector adjustment, belonging to the field of SoC chip fault location technology. It includes modules for multi-dimensional fault feature acquisition, fault feature preprocessing and dynamic weight allocation, improved adaptive Kalman filtering, adaptive test vector adjustment, and feedback verification. These modules are sequentially connected, and the feedback verification module forms a feedback loop with the preceding two modules. The system first acquires multi-dimensional fault feature data from the chip. After preprocessing and dynamic weighting, the improved adaptive Kalman filtering module analyzes the data to obtain fault type and severity parameters. Based on this, the system adaptively adjusts the input amplitude, frequency, and test focus of the test vector. Finally, the adjustment effect is verified, and closed-loop optimization is achieved. Each module uses a standardized interface, adaptable to different SoC chip architectures, improving the specificity and accuracy of fault location and enhancing the system's versatility.

The application relates to the chip design technical field, in particular to a chip architecture with optional cache mode. The chip architecture comprises a cache mode selection switch, which is used for controlling the cache in the chip to execute a cache working mode or a non-cache working mode; when the cache working mode is executed, cache control logic is executed; when the non-cache working mode is executed, the cache does not execute the cache control logic, and uses the body memory in the cache as a memory with a unified coding address, comprising: determining a destination address in a received instruction as the unified coding address, judging whether the destination address is a coding address corresponding to the body memory in the cache, if yes, writing data in a storage position corresponding to the destination address or reading data from the storage position corresponding to the destination address according to the operation type of the instruction; otherwise, transmitting the received instruction to a lower level. The application can solve the problem of low ALU utilization rate of a cache-based processor when the data flow is complex.