398 results about "Chip architecture" patented technology

XCB poly-radio devices as finders, locators, scanners, sensors, and Bluetooth (BT) radio topology reporters as part of a global lost-and-found services system. XCB devices function as “smart objects” and combine dual transceivers operating in the telecommunications and the low power ISM radio spectra, with default power management overrides under local control of the BT modem. “Familiar zones” are defined, and a “familiarity index” versus a “strangeness index” based on meta-analysis of BT radio contact logs are used to assign location. Location, in concert with other sensor data, is coupled to conditional logic rules programmable by the user or the system administrator. Locations, determined by monitoring familiar and unfamiliar BT radio topology, trigger executable commands to smartphones, to smart devices generally, and to remote machines, and can for example, generate alerts to a user if radiotagged assets, children or pets have strayed, are lost, or are left behind. When tied to cloud predictive services or increased edge computing capacity, incipient loss of radiotag objects can be detected before an owner knows the smart object is lost. In another embodiment, XCB devices having a novel chip architecture for improved power management of cellular and MCU circuits mediated by BT radio modem that achieves “situational awareness” by monitoring the BT signal environment around the device.

The invention provides a many-core cache consistency system, a many-core cache consistency method, electronic equipment, a storage medium and a product, and the system is based on a network-on-chip architecture, and a plurality of nodes, corresponding routers and distributed directories deployed in the routers are introduced. Each node comprises one or more processor cores and a distributed last-stage cache, and a memory address is divided into a plurality of address blocks and is associated with the distributed last-stage cache through a dynamic address mapping rule. The distributed directories and the distributed last-stage caches are in one-to-one correspondence and used for recording the states of cache lines, the router is responsible for receiving and responding to requests from local or remote nodes, querying the distributed directories and updating the states of the cache lines, and efficient management of cache consistency is achieved. The technical scheme belongs to the technical field of communication, effectively solves the problems of high load and communication delay of a main node in a traditional cache consistency protocol, and improves data consistency and access efficiency in a multiprocessor system and a large-scale parallel computing environment.

The invention discloses a large model calculation acceleration chip architecture, and relates to the field of large models. Comprising a normalized network-on-chip, an interconnection transmission system, a storage control system and a calculation acceleration core, the storage control system is connected with the Memory video memory group and the external SSD memory based on different built-in storage controllers; the normalized network-on-chip reads on-chip model parameters of a target position based on the storage control system, sends the on-chip model parameters to the calculation acceleration core for calculation, restores on-chip model data, carries out off-chip interaction with an external management server based on the interconnection transmission system, receives an instruction task, reads and restores external model parameters, and sends the external model parameters to the calculation acceleration core for calculation. And performing inter-chip interaction with other computing acceleration chips based on an interconnection transmission system, and reading and restoring inter-chip model parameters. According to the scheme, the hybrid video memory computing chip architecture supports multi-parallel SSD direct connection access, the capacity is expanded at low cost under the condition of keeping the bandwidth, and high cost performance is kept for both large-scale parallel tasks and small-sized low-cost all-in-one machines.

The invention belongs to the technical field of integrated circuit design verification, and particularly discloses an SoC performance verification method and device based on dynamic QoS regulation and control, a medium and equipment, and the method comprises the steps: analyzing a chip architecture, and obtaining a chip resource mapping table; constructing an automatic verification environment based on the chip resource mapping table and performing testing; scene parameter configuration is carried out according to a target application scene and based on the chip resource mapping table; and performing dynamic QoS regulation and control based on the configured scene parameters in a tested automatic verification environment so as to verify the performance of the SoC. According to the invention, the accuracy and efficiency of SoC performance verification and the consistency of the result and the actual application scene can be improved.

The invention discloses a cloud platform resource scheduling optimization method and system for a multi-chip architecture, and relates to the technical field of resource scheduling, and the method comprises the steps: carrying out the real-time monitoring of the multi-chip architecture of a cloud platform, and obtaining the monitoring data of each chip; performing fault risk inspection to obtain a chip cluster; task processing resource scheduling decision making is carried out, and a chip resource scheduling first decision space is established; performing initial optimization, and constructing a second decision space for chip resource scheduling; performing deep optimization to generate a chip resource scheduling optimization strategy; and task processing resource scheduling optimization is carried out. The technical problems of low resource utilization rate and poor task processing efficiency caused by lack of comprehensive management and control in the cloud platform multi-chip architecture in the prior art are solved, the full-process management and control of the cloud platform multi-chip architecture from monitoring, fault risk inspection to task processing resource scheduling optimization are realized, and the task processing efficiency is improved. And the resource utilization rate and the task processing efficiency of the cloud platform are improved.

The invention relates to the field of integrated circuit and chip architecture design, and discloses a storage and calculation integrated chip dynamic reconstruction system supporting multi-precision hybrid calculation, which comprises a fuzzy precision sensing module, a heterogeneous multi-precision calculation array module, a data reconstruction distribution module, an energy consumption prediction control module, a multi-target intelligent scheduling module and a calculation storage mapping module, the system carries out modeling through precision analysis and computing power requirements, calls a heterogeneous array to carry out dynamic precision matching, completes rearrangement and multi-level storage mapping, carries out calculation and storage path joint optimization, evaluates a power consumption load in advance, and carries out balanced scheduling among performance, power consumption and resources through a multi-target scheduling module. Dynamic adaptation of tasks under different precisions, efficient data reconstruction and distribution, intelligent mapping of storage paths and energy consumption control can be achieved, the calculation efficiency and the energy efficiency ratio of the system under a multi-task heterogeneous load are improved, and the method is suitable for edge AI, embedded reasoning and other high-performance low-power-consumption application scenes.

The invention belongs to the technical field of computer software, and particularly relates to a heterogeneous database unified deployment management method based on a cluster management platform, which comprises the following steps: predefining metadata of various database services; the method comprises the following steps: pre-constructing a multi-version program package warehouse, and establishing a structured warehouse directory system; obtaining a chip architecture and an operating system type of the target node, and generating environment fingerprint information; dynamically selecting a database installation package matched with the current environment and a dependency item set of the database installation package by mapping a warehouse directory system; through a unified database adaptation layer, a standardized operation interface is called, and installation, configuration and start-stop operation of the database are executed; a visual deployment and arrangement function based on component roles is provided by expanding a Web service interface of the management platform; and according to a deployment arrangement result and the environment fingerprint information, calling a deployment script to complete automatic deployment and configuration of the database cluster. According to the invention, unified adaptation, deployment and full-life-cycle management of various domestic databases are realized.

The embodiment of the invention provides a chip system, an image processing method and electronic equipment, and is applied to the technical field of chip image processing. The chip system comprises an image processor, a neural network processor and a scheduling circuit. Wherein the image processor is used for outputting a first rendered image according to the image subtask. And the scheduling circuit is used for instructing the neural network processor to acquire the first rendered image according to the scheduling sub-task. And the neural network processor is used for performing neural network algorithm processing on the first rendered image according to the operation subtask and outputting an operation result. And the scheduling circuit is also used for indicating the image processor to obtain an operation result according to the scheduling sub-task. And the image processor is also used for carrying out image processing on the operation result according to the image subtask to obtain a second rendered image. According to the embodiment of the invention, image processing is carried out based on multi-IP linkage so as to improve the imaging quality, the power consumption and the processing complexity of a chip system are reduced, and the method can be suitable for different chip architectures.

According to the storage and calculation integrated chip architecture, the chip stacking packaging structure and the terminal equipment, physical tight coupling of storage and calculation is realized through the 3D stacking design of the first storage unit and the logic calculation unit, the problem of physical separation of traditional storage and calculation is solved, the data carrying distance and the cross-chip communication overhead are remarkably reduced, and the communication efficiency is improved. And the chip area and the packaging process complexity are reduced, and the application scenarios of end-side artificial intelligence reasoning and mass data reading and writing are supported. According to the storage and calculation integrated chip architecture, the first storage unit and the logic calculation unit are directly interconnected through the vertical interconnection technology, the data access delay is reduced, the requirement of end side equipment for low delay is met, and the energy efficiency ratio of the storage and calculation integrated chip architecture is remarkably reduced.

The invention discloses a network architecture based on multi-core transmission, and relates to the field of integrated circuits. The network-on-chip module comprises at least one node ring consisting of M pipeline cascade routing nodes; adjacent routing nodes in adjacent node rings are cascaded according to a longitudinal depth pipeline to form a node matrix; n sending buffers and N receiving buffers are respectively arranged on the node ring on the outermost layer of the node matrix, and each sending buffer and each receiving buffer are respectively connected with the corresponding IP core through directly connected routing nodes; a routing algorithm based on a node matrix is built in the network configuration unit, a target IP core is determined according to data sent into the sending buffer by source IP core data, a node matrix is controlled to plan and generate a data transmission path, and data transmission is executed. The data buffer is added in the network-on-chip architecture, so that the data transmission path is shortened, the feedback is more timely, and the network bandwidth is larger; a routing node adds a data replication realization function to realize multicast and broadcast modes; and the interface complexity of the whole node matrix is reduced.

The invention provides an operator fusion method, system and device and a medium. The method comprises the steps of obtaining acceleration chip configuration information of a current hardware platform and operator type information contained in a computational graph; inputting the acquired acceleration chip configuration information, operator type information and the computational graph to a trained operator fusion model to output a target operator; wherein the operator fusion model adjusts low-rank weight adjustment parameters in the operator fusion model by loading a target first configuration file matched with the acceleration chip configuration information and a target second configuration file matched with the operator type information so as to adapt to a hardware platform and an operator type. By dynamically loading the configuration file related to the current hardware and operator type, the operator is automatically adjusted when facing algorithm and application demand changes and different acceleration chip architectures, and the performance consistency and reliability in different task scenes are ensured.

The invention provides a stacked chip architecture modeling method and a stacked chip architecture modeling system. The method comprises the following steps: dividing an on-chip chip to be modeled into a plurality of core particles; the method comprises the following steps of: modeling a chip by adopting a three-stage joint modeling mode, and respectively executing core size level modeling, medium level modeling and substrate level modeling; arranging the placement positions of the core particles according to the factors of the time sequence of the key path, the bus length and the super-long path; according to the connection relation between the interior and the exterior of the core particle, and according to the weights of the internal netlist and the external netlist of the core particle or user input information, optimizing the positions of the internal elements of the core particle, and adjusting the positions of the micro convex points mapped by the elements; and carrying out automatic wiring based on the arrangement position of each core particle, removing a network with conflicts in wiring, carrying out labyrinth wiring on an area in which wiring is removed, and searching an optimal wiring path. The system is used for implementing the method. The invention provides a one-stop chip design EDA tool, and the design precision of the chip can be improved.

The invention provides a time sequence scene-oriented chip architecture level power consumption evaluation method, which comprises the following steps of: S100, generating an original data set by utilizing micro-architecture design parameters of a chip to be designed and adding simulation excitation; removing redundant data in the original data set, merging to obtain a preprocessed data set, and training a preset LSTM-based power consumption prediction model; and adjusting the micro-architecture design parameters and the ESL model, regenerating input features, and inputting the input features into the trained LSTM-based power consumption prediction model to obtain a power consumption prediction result. According to the method, the multi-dimensional features are introduced, the influence of different workloads and architecture configurations on the power consumption is comprehensively considered, and the time sequence processing capability of the LSTM model is utilized, so that the time dependency relationship in power consumption fluctuation can be effectively captured, and the power consumption prediction precision is remarkably improved, especially in a dynamically changing time sequence scene.

The invention provides a channel decoding method, a confidence information transmission circuit and a reconfigurable chip architecture, and relates to the field of wireless communication, and the method comprises the steps: determining an aggregation level according to computing power information and / or information amount related to a to-be-decoded bit sequence under the condition that the to-be-decoded bit sequence is received; the aggregation level is used for indicating the number of nodes of synchronous iteration; therefore, the speed of synchronous transmission of the confidence information is flexibly adjusted; according to the aggregation level, iteratively calculating confidence information alternately transmitted between each check node and each variable node; and decoding the bit sequence to be decoded according to the confidence information of each variable node to obtain target information. Therefore, the confidence information which needs to be transmitted is determined by performing synchronous calculation on the confidence information received by the plurality of nodes, so that on one hand, the calculation process is simplified, the decoding reconstruction speed is improved, and on the other hand, the decoding performance is improved.

The invention discloses an end-to-end optical computing chip based on multi-mode analog signal fusion processing, and belongs to the optical computing technology. Comprising a multi-mode input fusion front-end module, an optical fiber input interface and an end-to-end reasoning module. The multi-mode input fusion front-end module can convert different types of original analog signals such as images, spectrums and radio frequencies into unified broadband spectrum input signals. The end-to-end reasoning module constructs a deep optical neural network, and the deep optical neural network comprises a sensing-convolution integrated unit realized by an arrayed waveguide grating (AWG). The end-to-end reasoning module further comprises a photoelectric non-linear-pooling integrated unit, the average pooling function and the non-linear activation function are achieved at the same time, and light path loss is effectively compensated through injection of the supply light source. And finally, integrating the signals subjected to multi-layer processing by a full connection layer, and outputting a classification result by an output layer. According to the chip architecture, direct and efficient processing of multi-mode analog signals is realized.

The invention discloses a method for realizing periodic online self-test of a network chip digital component and a chip architecture. The method comprises the following steps: S1, adding a TestPattern generator, a TestPattern response processor, a configuration and state memory sandbox, sandbox mapping logic and output check value logic on the basis of a chip functional architecture; s2, a TestPattern sequence is generated through a TestPattern generator, each TestPattern in the TestPattern sequence comprises a message, configuration and expected checksum information, for each TestPattern, the corresponding configuration is updated to a configuration and state storage sandbox, meanwhile, the TestPattern is notified to respond to the expected checksum information of a processor, and then the corresponding message is sent to a first functional unit of the chip; s3, the messages of the TestPattern sequentially pass through the corresponding functional units according to the processing sequence, when memory access operation is encountered, the memory access operation is mapped to the configuration and state storage sandbox through sandbox mapping logic, read-write operation is executed on the configuration and state storage sandbox, output check sums of the corresponding functional units are obtained through output check value logic, and the output check sums of the corresponding functional units are obtained; the output check sum of the last functional unit is sent to the TestPattern response processor; s4, the TestPattern response processor judges whether a random hardware fault exists or not based on the expected checksum information and the obtained checksum, namely the output checksum of the last functional unit; and S5, all Patterns of the TestPattern sequence are completed in the FDTI, and the TestPattern sequence is executed in a circulating manner.

The invention discloses a reconfigurable AI chip-oriented neural network reasoning deployment method, which comprises the following steps of: exporting a trained model into an ONNX format by using an ONNX library corresponding to a deep learning framework, and analyzing the ONNX format model to obtain a network topology structure, operator information and general control information; dividing each operator according to the operator information to obtain a division result; assembling and splicing operator division results in combination with a network topology structure to obtain task information, and the like. Hardware resources of the reconfigurable AI chip are fully utilized. And finally, organizing general control information and task information of all operators into a final executable file, and efficiently completing reasoning deployment of the neural network model on the reconfigurable AI chip. According to the method and the device, the technical problems of high development threshold and low efficiency of the existing specific AI chip architecture compiler can be solved, and the technical problem that the existing automatic code generation method possibly cannot fully utilize the chip performance can be solved.

The invention provides an arithmetic logic unit parallel processing system and method and electronic equipment, and relates to the field of chip architecture processing, and the arithmetic logic unit parallel processing system comprises an instruction transmitting unit, a write-back unit and a plurality of ALU groups containing a plurality of arithmetic logic units; wherein the instruction transmitting unit is respectively connected with the input end of each ALU group; the output end of each ALU group is connected with the write-back unit; the input end of each ALU group is respectively connected with the input ends of all the arithmetic logic units in the current ALU group; the output end of each ALU group is respectively connected with the output ends of all the arithmetic logic units in the current ALU group; according to the scheme, the reduction instruction and the vector arithmetic logic operation can be realized by using the same arithmetic logic operation component, the number and the area of the vector arithmetic logic operation component are reduced, and the utilization rate of the vector arithmetic logic operation component is improved.

The invention relates to the technical field of chip architecture, in particular to a chain structure access system of a GPU (Graphics Processing Unit) register, which is characterized in that each module in the same module set forms a register access chain, when facing different types of first access requests, the module to receive the first access request is determined through a chain structure, and the first access request is received. According to the method and the device, the first access request and the transmission condition of the first access request along the chain type structure are acquired, so that register access of multiple modules can be realized under the condition that only one first access request needs to be sent, the register access requirement of only one single module is compatible, the number of access requests is effectively reduced under the condition that the access function is not influenced, and the access efficiency is improved. Therefore, the condition of hardware resource competition is avoided, and the access efficiency of the register is effectively improved.

The invention belongs to the technical field of flexible manufacturing production line equipment state monitoring and cooperative control, and particularly discloses an edge side real-time data processing board card for a flexible production line and an implementation method of the edge side real-time data processing board card. The board card adopts an ARM + FPGA heterogeneous system-on-chip architecture, an FPGA end integrates a multi-channel data acquisition module, a Kalman filtering module, a real-time diagnosis module, a 1588 clock synchronization module and a PCIE-DMA module by utilizing hardware parallel characteristics, and data acquisition, preprocessing, fault diagnosis, high-precision synchronization and high-speed data transmission are realized through a pipeline architecture; and the ARM end realizes DDR (Double Data Rate) storage management, POWERLINK protocol communication and instruction scheduling functions based on a real-time operating system. The board cards communicate with a control station through a standard Ethernet interface, a CPCI standard interface is adopted to be embedded into an industrial personal computer, and 5Gbps high-speed data interaction between the board cards is achieved based on a PCIE protocol. According to the invention, hardware acceleration is carried out in the whole process of edge side data acquisition-processing-diagnosis, the cloud load is obviously reduced, and the fault response real-time performance is improved.

The invention relates to the technical field of integrated circuit design, in particular to a wafer-level chip architecture design-oriented heuristic layout method and system, and the method comprises the steps: core particle combination exploration: taking an exchange chip as a center, and generating a plurality of core particle combinations according to the core particle type, the interface type and the communication protocol consistency; a kernel in-group layout algorithm: performing multi-objective optimization layout on each core particle combination based on a genetic algorithm, wherein optimization objectives comprise area utilization rate, total wiring length and corner number; and wafer overall performance evaluation: copying and expanding the core group layout to the whole wafer, calculating a comprehensive performance index, and outputting a plurality of wafer layouts with the highest comprehensive performance index. According to the method, the wafer-level chip layout architecture with the smallest area, the shortest line length, the lowest corner number, the highest computing power and the lowest cost can be efficiently explored in limited time, the chip design efficiency is improved, and the design cost is reduced.

Disclosed are a neuromorphic chip compiling method and compiling system. The compiling method comprises: acquiring a pre-trained model and a data set of a neuromorphic application; generating an initial neuromorphic chip architecture and a network spiking input; performing an optimization and adjustment operation, performing simulation, and evaluating performance; and determining whether an optimization objective is satisfied, and performing loop optimization until an optimal neuromorphic chip architecture is obtained. In the method, by means of iterative optimization and effective evaluation, an optimal neuromorphic chip architecture is efficiently explored in a vast design space, thereby improving design quality and efficiency. The present application further provides a corresponding compiling system, comprising a generator, a simulator, and a compiler, thereby achieving automated compilation and deployment, and providing support for the design of large-scale multi-core neuromorphic chips.

Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

The invention provides an edge-computing-oriented low-power-consumption neural network coprocessor chip architecture, which comprises a core computing layer, a data processing layer and a power consumption and security management layer, and is characterized in that the core computing layer comprises an event-driven computing engine, a storage and computing integrated array and a dynamic reconfigurable internet. Compared with the prior art, the system has the following beneficial effects that by adding the core calculation layer, the data processing layer and the power consumption and safety management layer, the core calculation layer realizes non-zero feature selective activation through the data change threshold comparison circuit, the invalid calculation power consumption is reduced, the data carrying energy consumption is eliminated, and the task scheduler is matched to realize the dynamic path configuration of the calculation unit; the data processing layer matches a data stream with a calculation rhythm, realizes 30%-70% compression ratio of weight data and dynamically switches a calculation mode through a configuration register, and the power consumption and safety management layer dynamically adjusts threshold voltage according to a load, realizes optimal balance of power consumption and performance and outputs 32 / 16 / 8-bit flexible precision data, and can realize low-power-consumption operation.

The invention discloses a cryptographic algorithm adaptation and hardware encryption and decryption acceleration method suitable for a gateway protocol, deep integration of a cryptographic algorithm is realized through protocol stack-level native transformation, software and hardware collaborative design is adopted, and through innovative mechanisms such as multi-thread concurrent encryption, asynchronous interrupt processing and DMA data interaction, the hardware encryption and decryption acceleration of the cryptographic algorithm is realized. The processing capability in a high throughput scene is improved; an intelligent strategy engine is introduced to realize data packet dynamic classification and encrypted resource optimization scheduling, and the system performance is maximized while the security is ensured; according to the technical scheme, key full-life-cycle management and control are achieved through the HSM, the requirement for equal insurance 2.0 is met, multi-platform deployment is supported by adopting modular design, and compared with the prior art, the method can be flexibly adapted to various application scenes such as various domestic chip architectures, embedded devices, security gateways and industrial controllers, and the method is suitable for large-scale popularization and application. The problems of high platform dependence, difficulty in transplantation and the like existing in national secret IPSec implementation are solved, and a better secure communication solution is provided for a localized environment.

The invention provides a read-write data processing method and system based on chip particle interconnection interface address allocation. The method comprises the following steps: mapping a core particle interconnection structure formed by interconnection of a plurality of core particles into a directed graph; determining data streams among a plurality of core particles according to chip product design requirements, and simplifying the directed graph into sub-graphs based on the data streams; allocating an address to each interconnection interface controller from a root node of the sub-graph; and each interconnection interface controller identifies whether the received read-write request is forwarded to the equipment of the current bus or routed to other interconnection interface controllers according to the allocated address. By utilizing the method and the system, chip framework designers can determine the number and the direction of accessing other devices by the main device of each subsystem according to actual product development requirements, so that the degree of freedom of product design is greatly improved, and the data processing efficiency of products is greatly improved.

A unified timing closure system for the simultaneous synthesis of multi-mode clock trees in a system-on-chip architecture, comprising: a timing convergence processor configured to perform simultaneous analysis and optimization of clock distribution paths across a variety of operating modes and process voltage-temperature operating conditions, wherein the timing convergence processor maintains a unified timing graph that correlates all clock sinks with multiple mode vectors representing setup and hold relationships under different conditions; a multitude of distributed computer scaling units distributed across physically distinct sub-areas of the system-on-chip architecture, each distributed computer scaling unit being configured to determine local delay scaling factors corresponding to process variations, voltage fluctuations, and temperature gradients in its respective sub-area, and dynamically adjust the delay buffer characteristics, link impedance, and driver strength in response to the local scaling factors; a clock offset synchronization unit coupled with the timing convergence processor and the numerous distributed clock scaling units, wherein the clock offset synchronization unit is configured to monitor and minimize insertion delay differences between multiple clock sinks by dynamically adjusting capacitive loads and buffer driver strengths throughout the clock network to maintain uniform propagation characteristics across all modes; a multi-mode synchronization processor that is operationally linked to the timing convergence processor and is configured to harmonize clock arrival times across the operating modes of function, test, and power saving by mapping all mode-specific constraints into a unified timing domain, and to correct inter-mode skew divergence by iteratively adjusting clock path latencies; a distributed timing communication interface that establishes a hierarchical interconnection network between the timing convergence processor and the multiple distributed corner scaling units, wherein the distributed timing communication interface is configured to exchange real-time timing information, delay deviation metrics, and control instructions via a synchronized token-based communication protocol; and A physical time-matching circuit consisting of tunable delay lines, programmable capacitive elements and temperature-compensated bias transistors, physically embedded in the clock distribution network, wherein the physical time-matching circuit receives adaptive control signals from the time convergence processor and adjusts local propagation characteristics to achieve time completion simultaneously across all operating modes and process boundaries.

Described herein is a modular parallel processor comprising an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots and a plurality of chiplets vertically stacked on the active base die and coupled with the plurality of chiplet slots of the active base die. The plurality of chiplets is interchangeable during assembly of the modular parallel processor and include a group of hardware logic chiplets having a plurality of different functional units and a group of memory chiplets having a plurality of different memory devices. The hardware logic chiplets and the memory chiplets interconnect via the interconnect logic within the active base die.

The present disclosure relates to a computing-in-memory chip architecture, a packaging method for a computing-in-memory chip, and an apparatus. The computing-in-memory chip architecture includes: one or more first chips each integrated with one or more arrays of computing-in-memory cells of the computing-in-memory chip that are used to compute the received data; a second chip integrated with a peripheral analog circuit IP core and a digital circuit IP core of the computing-in-memory chip; an interposer between the one or more first chips and the second chip; and an interface module configured to communicatively couple the second chip to each first chip via the interposer, where the interface module includes one or more sub-interface modules on each first chip and aligned with each other, and where the interposer includes a first portion aligned with the one or more sub-interface modules on each first chip, and a second portion configured to arrange a communication path between the second chip and each first chip.

A three-dimensional chip architecture is described herein. In one example aspect, an integrated circuit may include an interposer. The integrated circuit may also include: a plurality of random access memory cores stacked on top of the interposer; and a plurality of computing cores. The plurality of computing cores may be stacked on top of respective ones of the plurality of random access memory cores such that the plurality of computing cores may be in electrical communication with the respective ones of the plurality of random access memory cores.