208 results about "Chip architecture" patented technology

The invention belongs to the technical field of integrated circuit design verification, and particularly discloses an SoC performance verification method and device based on dynamic QoS regulation and control, a medium and equipment, and the method comprises the steps: analyzing a chip architecture, and obtaining a chip resource mapping table; constructing an automatic verification environment based on the chip resource mapping table and performing testing; scene parameter configuration is carried out according to a target application scene and based on the chip resource mapping table; and performing dynamic QoS regulation and control based on the configured scene parameters in a tested automatic verification environment so as to verify the performance of the SoC. According to the invention, the accuracy and efficiency of SoC performance verification and the consistency of the result and the actual application scene can be improved.

The invention belongs to the technical field of computer software, and particularly relates to a heterogeneous database unified deployment management method based on a cluster management platform, which comprises the following steps: predefining metadata of various database services; the method comprises the following steps: pre-constructing a multi-version program package warehouse, and establishing a structured warehouse directory system; obtaining a chip architecture and an operating system type of the target node, and generating environment fingerprint information; dynamically selecting a database installation package matched with the current environment and a dependency item set of the database installation package by mapping a warehouse directory system; through a unified database adaptation layer, a standardized operation interface is called, and installation, configuration and start-stop operation of the database are executed; a visual deployment and arrangement function based on component roles is provided by expanding a Web service interface of the management platform; and according to a deployment arrangement result and the environment fingerprint information, calling a deployment script to complete automatic deployment and configuration of the database cluster. According to the invention, unified adaptation, deployment and full-life-cycle management of various domestic databases are realized.

According to the storage and calculation integrated chip architecture, the chip stacking packaging structure and the terminal equipment, physical tight coupling of storage and calculation is realized through the 3D stacking design of the first storage unit and the logic calculation unit, the problem of physical separation of traditional storage and calculation is solved, the data carrying distance and the cross-chip communication overhead are remarkably reduced, and the communication efficiency is improved. And the chip area and the packaging process complexity are reduced, and the application scenarios of end-side artificial intelligence reasoning and mass data reading and writing are supported. According to the storage and calculation integrated chip architecture, the first storage unit and the logic calculation unit are directly interconnected through the vertical interconnection technology, the data access delay is reduced, the requirement of end side equipment for low delay is met, and the energy efficiency ratio of the storage and calculation integrated chip architecture is remarkably reduced.

The invention discloses an end-to-end optical computing chip based on multi-mode analog signal fusion processing, and belongs to the optical computing technology. Comprising a multi-mode input fusion front-end module, an optical fiber input interface and an end-to-end reasoning module. The multi-mode input fusion front-end module can convert different types of original analog signals such as images, spectrums and radio frequencies into unified broadband spectrum input signals. The end-to-end reasoning module constructs a deep optical neural network, and the deep optical neural network comprises a sensing-convolution integrated unit realized by an arrayed waveguide grating (AWG). The end-to-end reasoning module further comprises a photoelectric non-linear-pooling integrated unit, the average pooling function and the non-linear activation function are achieved at the same time, and light path loss is effectively compensated through injection of the supply light source. And finally, integrating the signals subjected to multi-layer processing by a full connection layer, and outputting a classification result by an output layer. According to the chip architecture, direct and efficient processing of multi-mode analog signals is realized.

The invention provides an arithmetic logic unit parallel processing system and method and electronic equipment, and relates to the field of chip architecture processing, and the arithmetic logic unit parallel processing system comprises an instruction transmitting unit, a write-back unit and a plurality of ALU groups containing a plurality of arithmetic logic units; wherein the instruction transmitting unit is respectively connected with the input end of each ALU group; the output end of each ALU group is connected with the write-back unit; the input end of each ALU group is respectively connected with the input ends of all the arithmetic logic units in the current ALU group; the output end of each ALU group is respectively connected with the output ends of all the arithmetic logic units in the current ALU group; according to the scheme, the reduction instruction and the vector arithmetic logic operation can be realized by using the same arithmetic logic operation component, the number and the area of the vector arithmetic logic operation component are reduced, and the utilization rate of the vector arithmetic logic operation component is improved.

The invention relates to the technical field of integrated circuit design, in particular to a wafer-level chip architecture design-oriented heuristic layout method and system, and the method comprises the steps: core particle combination exploration: taking an exchange chip as a center, and generating a plurality of core particle combinations according to the core particle type, the interface type and the communication protocol consistency; a kernel in-group layout algorithm: performing multi-objective optimization layout on each core particle combination based on a genetic algorithm, wherein optimization objectives comprise area utilization rate, total wiring length and corner number; and wafer overall performance evaluation: copying and expanding the core group layout to the whole wafer, calculating a comprehensive performance index, and outputting a plurality of wafer layouts with the highest comprehensive performance index. According to the method, the wafer-level chip layout architecture with the smallest area, the shortest line length, the lowest corner number, the highest computing power and the lowest cost can be efficiently explored in limited time, the chip design efficiency is improved, and the design cost is reduced.

Disclosed are a neuromorphic chip compiling method and compiling system. The compiling method comprises: acquiring a pre-trained model and a data set of a neuromorphic application; generating an initial neuromorphic chip architecture and a network spiking input; performing an optimization and adjustment operation, performing simulation, and evaluating performance; and determining whether an optimization objective is satisfied, and performing loop optimization until an optimal neuromorphic chip architecture is obtained. In the method, by means of iterative optimization and effective evaluation, an optimal neuromorphic chip architecture is efficiently explored in a vast design space, thereby improving design quality and efficiency. The present application further provides a corresponding compiling system, comprising a generator, a simulator, and a compiler, thereby achieving automated compilation and deployment, and providing support for the design of large-scale multi-core neuromorphic chips.

The invention provides an edge-computing-oriented low-power-consumption neural network coprocessor chip architecture, which comprises a core computing layer, a data processing layer and a power consumption and security management layer, and is characterized in that the core computing layer comprises an event-driven computing engine, a storage and computing integrated array and a dynamic reconfigurable internet. Compared with the prior art, the system has the following beneficial effects that by adding the core calculation layer, the data processing layer and the power consumption and safety management layer, the core calculation layer realizes non-zero feature selective activation through the data change threshold comparison circuit, the invalid calculation power consumption is reduced, the data carrying energy consumption is eliminated, and the task scheduler is matched to realize the dynamic path configuration of the calculation unit; the data processing layer matches a data stream with a calculation rhythm, realizes 30%-70% compression ratio of weight data and dynamically switches a calculation mode through a configuration register, and the power consumption and safety management layer dynamically adjusts threshold voltage according to a load, realizes optimal balance of power consumption and performance and outputs 32 / 16 / 8-bit flexible precision data, and can realize low-power-consumption operation.

The invention discloses a cryptographic algorithm adaptation and hardware encryption and decryption acceleration method suitable for a gateway protocol, deep integration of a cryptographic algorithm is realized through protocol stack-level native transformation, software and hardware collaborative design is adopted, and through innovative mechanisms such as multi-thread concurrent encryption, asynchronous interrupt processing and DMA data interaction, the hardware encryption and decryption acceleration of the cryptographic algorithm is realized. The processing capability in a high throughput scene is improved; an intelligent strategy engine is introduced to realize data packet dynamic classification and encrypted resource optimization scheduling, and the system performance is maximized while the security is ensured; according to the technical scheme, key full-life-cycle management and control are achieved through the HSM, the requirement for equal insurance 2.0 is met, multi-platform deployment is supported by adopting modular design, and compared with the prior art, the method can be flexibly adapted to various application scenes such as various domestic chip architectures, embedded devices, security gateways and industrial controllers, and the method is suitable for large-scale popularization and application. The problems of high platform dependence, difficulty in transplantation and the like existing in national secret IPSec implementation are solved, and a better secure communication solution is provided for a localized environment.

The invention provides a read-write data processing method and system based on chip particle interconnection interface address allocation. The method comprises the following steps: mapping a core particle interconnection structure formed by interconnection of a plurality of core particles into a directed graph; determining data streams among a plurality of core particles according to chip product design requirements, and simplifying the directed graph into sub-graphs based on the data streams; allocating an address to each interconnection interface controller from a root node of the sub-graph; and each interconnection interface controller identifies whether the received read-write request is forwarded to the equipment of the current bus or routed to other interconnection interface controllers according to the allocated address. By utilizing the method and the system, chip framework designers can determine the number and the direction of accessing other devices by the main device of each subsystem according to actual product development requirements, so that the degree of freedom of product design is greatly improved, and the data processing efficiency of products is greatly improved.

A unified timing closure system for the simultaneous synthesis of multi-mode clock trees in a system-on-chip architecture, comprising: a timing convergence processor configured to perform simultaneous analysis and optimization of clock distribution paths across a variety of operating modes and process voltage-temperature operating conditions, wherein the timing convergence processor maintains a unified timing graph that correlates all clock sinks with multiple mode vectors representing setup and hold relationships under different conditions; a multitude of distributed computer scaling units distributed across physically distinct sub-areas of the system-on-chip architecture, each distributed computer scaling unit being configured to determine local delay scaling factors corresponding to process variations, voltage fluctuations, and temperature gradients in its respective sub-area, and dynamically adjust the delay buffer characteristics, link impedance, and driver strength in response to the local scaling factors; a clock offset synchronization unit coupled with the timing convergence processor and the numerous distributed clock scaling units, wherein the clock offset synchronization unit is configured to monitor and minimize insertion delay differences between multiple clock sinks by dynamically adjusting capacitive loads and buffer driver strengths throughout the clock network to maintain uniform propagation characteristics across all modes; a multi-mode synchronization processor that is operationally linked to the timing convergence processor and is configured to harmonize clock arrival times across the operating modes of function, test, and power saving by mapping all mode-specific constraints into a unified timing domain, and to correct inter-mode skew divergence by iteratively adjusting clock path latencies; a distributed timing communication interface that establishes a hierarchical interconnection network between the timing convergence processor and the multiple distributed corner scaling units, wherein the distributed timing communication interface is configured to exchange real-time timing information, delay deviation metrics, and control instructions via a synchronized token-based communication protocol; and A physical time-matching circuit consisting of tunable delay lines, programmable capacitive elements and temperature-compensated bias transistors, physically embedded in the clock distribution network, wherein the physical time-matching circuit receives adaptive control signals from the time convergence processor and adjusts local propagation characteristics to achieve time completion simultaneously across all operating modes and process boundaries.

Described herein is a modular parallel processor comprising an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots and a plurality of chiplets vertically stacked on the active base die and coupled with the plurality of chiplet slots of the active base die. The plurality of chiplets is interchangeable during assembly of the modular parallel processor and include a group of hardware logic chiplets having a plurality of different functional units and a group of memory chiplets having a plurality of different memory devices. The hardware logic chiplets and the memory chiplets interconnect via the interconnect logic within the active base die.

Method for transporting packets in a multi-cluster Network on Chip (NoC) interconnect with a transport protocol significantly enhance packet management in complex NoC chip architectures. This approach involves processing a packet within clusters to determine a destination cluster and a destination node, and executing a node lookup for the packet intended for different clusters. This lookup identifies an optimal path for transporting the packet out of the cluster. The multi-cluster NoC interconnect efficiently outlines cluster-to-cluster connections and manages global traffic, incorporating deadlock prevention techniques. Global bridges and boundary bridges facilitate effective traffic management between clusters. Each node includes a programmable path table that dynamically assigns efficient routes. This method significantly improves packet management across multi-cluster NoCs, offering a scalable, efficient, and reliable solution for complex computing environments.

Testing a semiconductor can be time-consuming as the chip architecture becomes more complex. Testing the possible scenarios becomes increasingly difficult. Chip quality characteristics relating to the chips on a wafer can be used to estimate a probability or rating relating to bypassing system-level testing (SLT). A chip can bypass SLT if there is a high likelihood of passing SLT. Thousands of chip characteristics can be received from wafer testing, chip probe testing, environmental parameters, factory parameters, and other parameters. A chip quality model can use chip quality characteristics as input to generate chip group and SLT parameters. The chip quality model can be a machine learning model or other types of machine learning systems. The chip group parameter or the SLT parameter can be used to direct the testing path of a chip where some chips can bypass SLT thereby saving production time.

The invention relates to a network-on-chip architecture (100) characterized by: a plurality of replicable partitions (200), each partition (200) comprising one or more routers (10) suitable for communication, a register, and a pre-built communication link established in a base direction or other direction, and one or more configuration bus nodes (20) arranged in each partition (200) connected to the register (40); a system integrator connecting the system operator (60) to one of the configuration bus nodes (20); wherein the system operator (60) initializes a path map between the configuration bus nodes (20) to form a secondary configuration network, and accesses the registers (40) in each partition to program the registers (40) with routing data. A method of processing data on a network-on-chip architecture (100) is also disclosed herein.

The invention provides a software operation synchronization method and system based on a dual-chip architecture, and abandons a traditional mode depending on a UART / SPI / CAN communication protocol or an additional synchronization circuit. Firstly, a unique PWM duty ratio mapping relation with any difference not smaller than 5% is preset for the initial state, the system self-checking state, the OTA upgrading state, the running state, the fault state, the dormancy preparation state and other running states of the double-chip system, and then a chip A and a chip B continuously output PWM signals matched with the current states of the chip A and the chip B through common GPIO pins in a push-pull output mode. Meanwhile, PWM signals of GPIO pins of the opposite side are collected in real time in a bidirectional mode through respective hardware capture units, the duty ratio is analyzed to obtain the state of the opposite side, response operation is executed according to preset logic, synchronization failures caused by communication delay and data frame error codes of a traditional software protocol are effectively avoided, the system stability is guaranteed, meanwhile, a complex protocol stack does not need to be designed, and the cost is reduced. The CPU load rate is reduced, an additional synchronous circuit is omitted, the chip area and power consumption are reduced, and the hardware cost is reduced.

The invention relates to a silicon substrate network physical topological structure and a silicon substrate chip architecture, the silicon substrate network physical topological structure comprises a central switch and a plurality of calculation core particle groups, each calculation core particle group is connected with the central switch, the central switch is arranged at the center of a wafer, and each calculation core particle group is arranged in a preset area around the central switch on the wafer; the central switch is used as a data routing node and provides a signal path for any two computing core particle groups; the calculation core particle group comprises a plurality of calculation core particles, all the calculation core particles are arranged in a two-dimensional grid form, all the calculation core particles are mutually connected through an on-chip network, and the calculation core particles are used for calculating data. By adopting the silicon substrate network physical topological structure, the balance between communication resources and computing resources can be ensured.

The invention relates to the technical field of integrated circuit design and robots, in particular to a special chip architecture for a sensing-computing-control integrated robot controller, which adopts a multi-core heterogeneous system architecture and comprises a control core, a computing core and a sensing core, and is characterized in that the control core is a high-performance real-time processor core cluster based on an RISC-V instruction set; the calculation core is used for accelerating AI task reasoning calculation of a visual language model, reinforcement learning and target detection; the sensing core is used for gathering and preprocessing data from various sensors; the control core, the calculation core and the sensing core are integrated in a single SoC chip, and integrated fusion of multi-mode sensing, high-throughput calculation and high-real-time control functions is achieved. According to the scheme, multi-mode sensing, complex calculation and real-time control are deeply fused into a single SoC chip through software and hardware collaborative design, so that the comprehensive performance of a robot control system is remarkably improved, and unification of high real-time response, high calculation energy efficiency and high design flexibility is achieved.

The invention discloses a stacked chip architecture of a distributed cache and a chip. The stacked chip architecture comprises a logic calculation unit and a storage unit which are arranged in a stacked manner; the stacked chip architecture further comprises cache units, one cache unit is correspondingly connected with the logic calculation unit and the storage unit, the number of the cache units is multiple, and the multiple cache units are in topological connection; wherein the cache unit is used for storing a data address corresponding to the storage unit, and the logic calculation unit initiates a memory access request to the cache unit; if the memory access request hits the data address stored in the cache unit, returning the storage data of the storage unit to the logic calculation unit; and if the memory access request does not hit the data address stored in the cache unit, forwarding the memory access request to other cache units. According to the technical scheme, the requirement for high-bandwidth communication with the storage unit can be effectively met.

This invention discloses a communication clock and data phase dynamic calibration circuit and method based on a chip architecture, comprising a master control MCU DIE and n controlled ASIC DIEs 1 to 1 controlled ASIC DIEs. n The main control MCU DIE has n+1 global delay modules GDL1 to GDL1. n+1 n controlled ASIC DIEs 1 to n controlled ASIC DIEs n Each of the internal units is equipped with a local phase unit LPU1 to LPU, which correspond to each other. n This invention eliminates data sampling failures caused by timing path differences, achieving a bit error rate of ≤10% in multi-DIE scenarios. ‑9 Reliable communication significantly reduces the bit error rate of multi-DIE synchronous communication data transmission.

The invention belongs to the technical field of CMUT sensor gas detection, and particularly discloses a multi-mode fusion self-compensation gas detection circuit for a CMUT sensor. The circuit is adapted to an integrated CMUT sensor chip architecture comprising a sensing CMUT and a reference CMUT. Two multi-mode front-end detection circuits are designed, each multi-mode front-end detection circuit is used for being connected with a sensing CMUT and a reference CMUT and is used for synchronously collecting at least two different types of multi-path electrical response signals of the sensing CMUT and the reference CMUT, a differential processing circuit is further designed, and the differential processing circuit is used for synchronously collecting the multi-path electrical response signals of the sensing CMUT and the reference CMUT. And the differential processing module is used for performing differential processing on the collected multi-path electrical response signals of the sensing CMUT and the reference CMUT so as to effectively eliminate common-mode environment interference, thereby obtaining pure multi-path electrical response signals. According to the invention, the pure multi-path electrical response signals are uploaded to the upper computer, fused and input into the gas detection model for pattern recognition, so that the capability of distinguishing the mixed gas is improved.

The invention discloses an Internet of Things security chip based on multiple quantum entropy sources, and a security authentication method, device and system. The Internet of Things security chip comprises a static preset quantum entropy unit; a dynamic real-time quantum entropy source circuit; an entropy source fusion and management unit; wherein the entropy source fusion and management unit is configured to support at least two operation modes: (A) a basic service mode: generating a device identifier based on the output of the static preset quantum entropy unit, or providing a true random number based on the output of the dynamic real-time quantum entropy source circuit; (B) a fusion binding mode: taking the output of the static preset quantum entropy unit as an equipment binding parameter, performing cryptographic processing on the output of the dynamic real-time quantum entropy source circuit, and generating a cryptographic material uniquely bound with the equipment; the chip architecture realizes hardware-level binding of equipment identity and password randomness, has the advantages of high security, flexible configuration and controllable cost, and provides an ideal hardware trust root for constructing massive and trusted Internet of Things.

The invention is suitable for the technical field of chips, and particularly relates to a modeling method and system for chip layout planning and related equipment.The method comprises the steps that configuration information of a chip is obtained, and a configuration file is established according to the configuration information; storing the module information in a module corresponding to the module list; establishing a multi-level nested data structure according to the module relation data; performing coordinate calculation and merging on modules of different levels in the nested data structure to obtain module coordinate data with coordinate information of all the modules; and performing shape drawing according to the module coordinate data to obtain a chip layout model. Compared with the prior art, the method has the advantages that real-time iteration can be performed according to the actual progress of chip design, designers are greatly facilitated to deeply think the chip architecture design, more accurately estimate the layout area and better determine the distribution position of the module, and the design efficiency is improved. Therefore, excessive dependence of top layer layout planning work on a traditional EDA tool is eliminated.

A self-configurable traffic generator system in a System-on-Chip architecture includes a transmit special function register circuit configured to receive initial input parameters including frequency, expected bandwidth, periodicity, and latency from a silicon-dump or external target specification. A time-microscale circuit generates micro-level bandwidth targets based on one or more initial input parameters. A target-deviation circuit estimates, for each logical client, deviation between achieved bandwidth and corresponding micro-level bandwidth targets and computes adaptive weights using adaptive learning. A transactional-intelligence circuit controls one or more transaction parameters based on the adaptive weights. A transmit generation core circuit generates traffic for a plurality of clients based on the controlled one or more transaction parameters. A performance monitor circuit captures traffic information.

The invention discloses a low-power-consumption optimization method based on multi-mode switching, a low-power-consumption control core CR5LP, a system mode controller SMC and a power management unit PMU are integrated in a chip architecture, the CR5LP is responsible for logic control of switching from a Run mode to an LPRun mode, the SMC dominates mode switching from the LPRun to a Sleep / Hibernate, and the PMU serves as a power execution unit and is used for realizing on-off control of internal DCDC, LDOLP and SYSCTRL0-1; and the low-power-consumption control core CR5LP, the system mode controller SMC and the power management unit PMU realize data interaction through an internal high-speed bus. The method has the advantages that power consumption dynamic optimization of equipment under different working conditions is realized, the low-power-consumption management efficiency is improved, and an effective solution is provided for improving the energy efficiency of a vehicle-mounted embedded system.

The invention relates to a task processing method and device, equipment, a storage medium and a program product. The method comprises the steps of calling a request standardization interface in response to an equipment management and control request for edge equipment in a cluster, and converting the equipment management and control request to obtain a standard management and control request; wherein the request standardization interface is obtained by processing request processing information associated with a brain-like chip architecture and an embedded architecture in the side-end equipment; according to the request processing logic of the standard management and control request, analyzing the standard management and control request to obtain at least two parallel request processing tasks; and determining a task processing strategy according to the task attribute of each request processing task and the equipment information of the edge equipment, and sending the task processing strategy and each request processing task to the edge equipment so as to execute the corresponding request processing task on each parallel computing unit associated with the brain-like chip architecture in the edge equipment. By adopting the method, the operation reliability of the edge equipment can be improved.

The present disclosure relates to the technical field of memory-computing integrated chips, and in particular, to a memory-computing integrated chip architecture, a packaging method and an apparatus for a memory-computing integrated chip. The memory-computing integrated chip architecture includes: a plurality of first chips, each integrated with one or more arrays of memory-computing integrated cells, wherein the one or more arrays of memory-computing integrated cells are used for computing with received data; and one or more second chips, each integrated with one or more peripheral circuit IP cores, wherein the one or more arrays of memory-computing integrated cells are coupled to the one or more peripheral circuit IP cores via one or more communication paths, and wherein the one or more communication paths are arranged based on one or more of an operation property and an arrangement of the one or more arrays of memory-computing integrated cells of the plurality of first chips.

A glass substrate architecture for mounting RF components may be configured for heat dissipation. Existing millimeter wave radiofrequency (RF) systems mount the radiofrequency integrated circuits (RFICs) on a printed circuit board on the opposite side of a heat sink, making it difficult to dissipate heat away from the RFICs during operation. This architecture mounts the RFICs directly to a back side of a glass waveguide substrate, and thermally couples the top side of the RFICs to a conductive pad on the underlying printed circuit board with a thermal pathway to the heatsink. This leads to a much more effective dissipation of heat away from the RFICs and eliminates the need for additional cooling systems or throttling the performance of the radar system.

The application discloses a kind of dual clutch gearbox controller systems based on functional safety requirements, it is related to gearbox controller technical field, using the dual-chip architecture of main control chip and monitoring chip, the system includes power management module, for providing multiple power supply;Main control chip, for executing control logic;Monitoring chip, for real-time monitoring chip state, power and sensor signal;Motor drive module, for configuring 5 motor drive circuits and feedback rotor position;Communication interface module, for integrating 4 CAN and 1 LIN channel;Signal acquisition module, for collecting multiple sensor signals;Safety state control module, for triggering safety mechanism.The application combines lockstep core design and multiple diagnostic mechanism, redundant monitoring and fault detection of key signals are realized, meet the ASIL D functional safety level requirements in ISO 26262, all chips use domestic chips, with functional safety and cost advantage, adapt to different vehicle communication and sensor configuration requirements.

The application provides a compilation method and device of an operator, equipment and a medium, and relates to the technical field of artificial intelligence. The compilation method of the operator comprises the following steps: obtaining operator source code to be compiled, the operator source code being code written in a domain-specific language based on Triton; converting the operator source code into a Triton dialect, performing hardware-independent optimization, the Triton dialect being a hardware-independent dialect based on an MLIR framework and used to represent the computing logic of the operator source code; converting the Triton dialect into a hardware-specific dialect, the hardware-specific dialect being a hardware-related dialect based on the MLIR framework and used to represent hardware-oriented computing logic; generating source code in a general programming language according to the hardware-specific dialect; and calling an LLVM-based compilation tool corresponding to a target chip to generate target code according to the source code in the general programming language. The operator can be applied to chips with different chip architectures.