Digital-analog hybrid neural network chip architecture

Abstract

The invention discloses a digital-analog hybrid neural network chip architecture. The architecture comprises a two-dimensional SRAM module, an analog synaptic circuit, a nerve cell circuit, an AER communication module, and a master control digital unit. The two-dimensional SRAM module is taken as a storage unit of neural network connection relation and a synaptic weight value. The analog synaptic circuit and the nerve cell circuit respectively consist of an MOSFET circuit working in a subthreshold section. The AER communication module serves as the input and output interfaces of a chip, and employs an AER protocol for communication. All control circuits in the architecture are synchronous digital circuits. The architecture is low in power consumption, is high in degree of parallelism, and can achieve a neural network algorithm in a reasonable chip area, wherein the neural network algorithm is more complex in nerve cell functions, is larger in network scale, and is more flexible in connection.

Description

technical field [0001] The invention relates to a chip architecture, in particular to a digital-analog hybrid neural network chip architecture, which can be used for low-power hardware implementation of neural network algorithms. Background technique [0002] The artificial neural network is a complex network system formed by extensive interconnection of a large number of simple components. It is characterized by distributed storage, asynchronous parallel processing, self-adaptation, self-learning and fault tolerance, which makes it useful in pattern recognition, speech analysis and synthesis. , computer vision and other sensory signal processing has great application prospects. However, the implementation of neural network algorithms needs to consume a lot of computing resources, especially large-scale algorithms, which usually need to resort to GPU or FPGA. [0003] Today, silicon-based VLSI technology is very mature, and research on dedicated neural network chips using C...

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Problems solved by technology

[0004] Dedicated neural network chips based on digital integrated circuits have the disadvantages of low parallelism, low efficiency and high power consumption, and the neuron functions that can be realized are relatively simple

Compared with the traditional neural network algorithm implementation platform, the existing digital-analog hybrid neural network chips may have the characteristics of high parallelism and low power consumption, but the neural network structure is relatively limited; or the neural network structure can be flexibly configured, However, the network scale that can be realized is small; or a large-scale neural network can be realized, but the power consumption is large

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