41 results about "Neuronal circuitry" patented technology

The application discloses a kind of nonvolatile memory-based pulse neuron circuit, it is related to the technical field of pulse neural network.The nonvolatile memory-based pulse neuron circuit includes: voltage dividing resistor network, current mirror circuit and MRAM pulse neuron module with temperature accumulation effect;Wherein, the voltage dividing resistor network receives target synapse array pulse signal and carries out voltage dividing processing to the target synapse array pulse signal, generates voltage dividing signal;The current mirror circuit is connected with the voltage dividing resistor network, and the current signal of the MRAM pulse neuron module is output according to the voltage dividing signal adaptation;The MRAM pulse neuron module is connected with the current mirror circuit, and the current signal is accumulated according to the temperature, and when temperature accumulation reaches threshold temperature, emits pulse signal.

A neural network device according to an embodiment includes a plurality of synapse circuits and a plurality of neuron circuits. A first neuron circuit out of the neuron circuits includes an input circuit, a charge holding circuit, a comparison circuit, a firing circuit, a charge control circuit, and a control signal output circuit. When a determination signal changes from a second value to a first value, the firing circuit outputs a spike signal. The control signal output circuit outputs a control signal indicating a comparison voltage that is based on an excess component of a membrane potential exceeding a threshold potential. In response to acquiring the spike signal from the first neuron circuit, a first synapse circuit out of the synapse circuits that acquires the spike signal from the first neuron circuit outputs a synaptic current of a current amount corresponding to the control signal and a synaptic weight.

Disclosed is a spike neural network circuit according to an embodiment of the present disclosure, which includes a self-correcting control circuit that generates an input signal and a first control code, a bias voltage generation circuit that generates a first bias voltage based on the first control code, a synaptic circuit including a first synaptic column that performs an operation of the input signal and a first weight signal and generates a first operation signal, a neuron circuit including a first neuron that generates a first output signal based on a comparison of the first operation signal and a threshold voltage, and a spike comparison circuit that generates a first comparison signal corresponding to a difference between the first output signal and a reference number, and the self-correcting control circuit further generates a second control code for correcting the first bias voltage.

The present invention relates to a neuromodulation / neurostimulation system (10) for the treatment of spasticity in a mammal, said system (10) comprising: —at least one control unit (12) configured and arranged to provide stimulation data, and—at least one stimulation unit (14), operatively connected to the at least one control unit (12), said at least one stimulation unit (14) being configured and arranged to deliver epidural electrical stimulation to the spinal cord of said mammal, according to said stimulation data, wherein the at least one stimulation unit (14) includes a biocompatible implantable lead (18) configured and arranged to cover at least a portion of the spinal cord of said mammal to deliver epidural electrical stimulation to the dorsal roots innervating the spastic muscles to target neuronal circuitry responsible for spastic episodes.

The present application relates to the field of artificial neuromorphics, and provides an artificial neuron circuit based on a volatile threshold switching device. A membrane potential generation circuit is used for generating different membrane potentials under different input currents and different external reset voltages; a slow variable generation circuit is used for generating a slow variable; a membrane potential reset circuit comprises a volatile threshold switching device and an external reset voltage excitation source; the external reset voltage excitation source is used for providing different external reset voltages, so that the membrane potential and the slow variable are changed, and a spiking behavior of biological neurons is simulated; and the volatile threshold switching device is used for realizing a membrane potential reset function. Compared with traditional CMOS-circuit-based neurons, the neuron circuit provided by the present application requires a greatly reduced number of transistors and reduced hardware and power consumption overhead, has the characteristics of simple structure, high flexibility and rich functions, and is beneficial to large-scale integration in a hardware pulse neural network.

The invention provides a neuron circuit. The neuron circuit comprises n input tubes, an integrating capacitor, an inverted output unit and a reset unit, the input tube is selectively gated based on an input voltage and a control voltage; the integrating capacitor accumulates charges and then releases the charges; the inverted output unit generates an output voltage; the reset unit resets the potential of the integrating capacitor. The invention further provides an activation method of the neuron circuit, and the neuron circuit is activated by controlling the integrating capacitor to accumulate charges and then discharge. The invention further provides a preparation method of the field effect transistor. The source electrode structure, the drain electrode structure and the grid electrode structure are formed on the provided substrate. The invention further provides a neural network which comprises an input layer and an output layer, and the output end of a single neuron circuit of the input layer is connected with the input ends of all or part of neuron circuits of the output layer. The signal processing system comprises an electric signal input device, a reading device and a neural network, the electric signal input device provides input data; the readout device reads the output data.

The invention relates to a gain-adjustable neuron circuit and a control method thereof, the gain-adjustable neuron circuit comprises a memristive element, a capacitor and a resistor, one end of the memristive element is connected with the capacitor in parallel, then is connected with the resistor in series, and is connected with a driving power supply; the memristive element comprises an MIM structure, a heating module for providing a thermal field for the MIM structure and a substrate for providing support for the whole memristive element, the MIM structure comprises a top electrode, a functional layer and a bottom electrode which are sequentially distributed from top to bottom, the heating module comprises a heat conduction layer and a heating layer which are sequentially distributed, and the heating layer is in contact with the MIM structure through the heat conduction layer for heat transfer; the top electrode is connected with driving type voltage input, and the bottom electrode is grounded; one end of the heating layer is connected with modulation type voltage input, and the other end is grounded; and a port, connected with the resistor, of the memristor element is a voltage output end. Compared with the prior art, the pulse response to driving type input can be realized, and the dynamic adjustment of the response gain is also realized.

The invention discloses an adaptive structure LIF neuron circuit, which comprises a current integration module, a voltage amplification module, a voltage positive feedback module, a voltage reset module and an adaptive module, and is characterized in that the current integration module is composed of an input current source Iin and an integration capacitor C1, and the voltage amplification module is composed of two stages of c-OECT inverters in cascade connection; each level of c-OECT phase inverter is composed of a pair of n-OECT and p-OECT, namely M2-M5, the voltage positive feedback module is composed of a capacitor C2, the voltage positive feedback module and the capacitor C1 jointly form a capacitance voltage division network, the voltage reset module is composed of a transistor M1, and the self-adaption module is composed of a resistor R1, a resistor R2, a resistor R3, a capacitor C3, two n-OECTs and a p-OECT. The learning behavior of biological neurons is simulated, a neuromorphic device capable of simulating neurosynaptic plasticity can be developed, an electronic device conforming to neuromorphic calculation characteristics can be developed, and the method can be applied to neuron calculation, brain-like intelligent systems and large-scale neural network development.

The invention relates to the technical field of neuron circuits, and provides a configurable neuron circuit and a control method, and the circuit comprises a mode selection module which selects a corresponding target working mode according to a received neuron configuration signal; the calculation module is connected to the mode selection module, and performs corresponding membrane potential updating according to the target working mode selected by the mode selection module and the received pulse information of the presynaptic neurons to obtain a membrane potential updating result; the comparison module is connected to the calculation module and is used for comparing the membrane potential updating result with a preset threshold value and determining whether the current neuron can generate a pulse or not according to a comparison result; and the pulse generation module is connected to the comparison module, and is used for generating a pulse signal and an AER (Advanced Encryption Register) coding group package and outputting updated membrane potential information when the current neuron is determined to generate the pulse. According to the technical scheme, selection of two neuron models can be achieved, the circuit structure is simplified, and meanwhile more complex behavior modes are achieved.

This invention relates to an event-triggered neuron circuit based on a volatile memristor, comprising: a signal transmission module and an encoding module; the signal transmission module converts a received light signal into an output voltage and transmits the output voltage to the encoding module; wherein the output voltage is positively correlated with the intensity of the light signal; the encoding module obtains an oscillating encoded signal based on the change in the output voltage. This technical solution converts the light signal into a voltage, and by controlling the change in the output voltage, obtains an oscillating encoded signal consistent with the characteristics of LIF neurons. The output voltage can change according to the increase or decrease in light intensity, which is also consistent with the characteristics of event-driven structures. This achieves voltage encoding output of light changes using a simple circuit structure, and to some extent promotes the development of event-driven structure research in neuromorphic computing.

The CMOS neuron-synaptic unit circuit system suitable for the spiking neural network is realized, so that network parameters of the spiking neural network are effectively initialized, and the weight is dynamically adjusted to promote information propagation and learning. The CMOS neuron-synaptic unit circuit system comprises a front LIF neuron circuit module which receives an input pulse signal and generates an output pulse through integration; the synapse circuit receives the output pulse and adjusts the transmission intensity of the signal by adjusting the real-time weight; the STDP circuit adjusts the synaptic weight according to the time difference between the pulse output by the front LIF neuron circuit module and the pulse output by the rear LIF neuron circuit module; the ATML circuit receives the output pulse of the front LIF neuron circuit module and the output pulse of the rear LIF neuron circuit module, and adjusts the weight of the STDP to update the length of a time window by changing the size of a time window length signal Vleak; and the LIF neuron circuit receives the signal from the synaptic circuit module, and simulates the neuron signal integration and pulse generation process again.

The invention discloses a light-magnetic sensing neuron circuit, and relates to the field of neurons, and the light-magnetic sensing neuron circuit comprises a light-sensitive element and two magnetic sensing neurons. Two ends of the photosensitive element are respectively connected with the two magnetic sensing neurons; each magnetic sensing neuron comprises a Josephson junction and a neuron circuit; when the Josephson junction is exposed in a magnetic field, the Josephson junction captures and releases magnetic field energy, and senses the change of the external magnetic field in combination with the neuron circuit; the photosensitive element captures external illumination energy after being activated in an illumination environment so as to simulate the cross-modal response of biological vision and magnetic perception. According to the invention, bimodal sensing and response of light and magnetism are realized.

Neuron circuits are provided for spiking neural network apparatus having multiple such neuron circuits interconnected by links, each associated with a respective weight, for transmission of signals between neuron circuits. A neuron circuit includes a digital transmitter for generating trigger signals, indicating a state of the neuron circuit, on outgoing links of the circuit. The state is encoded in a time interval defined by these trigger signals. The neuron circuit includes a digital receiver for detecting such trigger signals on incoming links of the circuit, and digital accumulator logic. In response to detecting a trigger signal on an incoming link, the digital accumulator logic is adapted to generate a weighted signal dependent on the time interval and to accumulate the weighted signals generated from trigger signals on the incoming links to determine the state of the neuron circuit.

The invention provides a pulse neural network acceleration device based on a hafnium-based ferroelectric memristor. The structure of the device comprises a PC, a power supply circuit, an FPGA core board, a digital-to-analog conversion unit, a coding unit, a switch unit, a memristor array, a signal amplification circuit and an LIF neuron circuit. According to the hafnium-based ferroelectric memristor array, functions needing to be achieved are selected through specific software of the PC, read-write, weight modulation and image recognition of the hafnium-based ferroelectric memristor array can be achieved, image RGB values in the PC are converted into corresponding gray values to be sent to the FPGA core board, the FPGA core board controls and selects memristors needing to be modulated through the coding unit, the digital-to-analog conversion unit and the switch unit, and therefore the memristors needing to be modulated can be modulated. Read-write, weight modulation and image recognition functions of the ferroelectric memristor are realized, and results are output through the LIF neuron circuit.

The invention discloses a method for realizing pattern recognition based on a bistable memristor neuron circuit. A bistable memristor neuron circuit is constructed through a bistable memristor, and under the driving of pulse voltage, the bistable memristor neuron circuit transitions from one discharge behavior to another discharge behavior, so that a neuron discharge behavior with bistability is realized. A transistor-memristor neural network mode identification scheme taking 1T1M as an example is successfully constructed by combining a threshold effect of steady-state switching of a discharge behavior of a memristor neuron circuit. The technical scheme has a wide application prospect in the consumer electronics fields such as voice recognition and image recognition functions in smart home equipment, and is expected to provide a new thought for developing more efficient neuromorphic calculation.

The invention discloses a Schmitt trigger, an artificial neuron circuit and a neuromorphic calculation device.The Schmitt trigger comprises a flexible substrate, a gate electrode, a biocompatible gate dielectric layer, a P-type organic semiconductor and an N-type organic semiconductor, complementary connection is achieved through three top electrodes, the capacitance value of the gate dielectric layer changes along with an electric field, and the gate dielectric layer has the hysteresis characteristic; the device has double threshold voltages in a single structure, and a Schmidt trigger function can be realized without a complex circuit. On the basis, the invention further provides an artificial neuron circuit, and the electric leakage integration-release behavior of the biological neurons is simulated by integrating the Schmitt trigger, the membrane capacitor and the phase inverter. The device has the advantages of simple structure, low power consumption, low preparation cost, excellent flexibility and biocompatibility and the like, and is suitable for an implantable bioelectronic and high-energy-efficiency neuromorphic computing system.

This invention discloses a WTA circuit based on LIF neurons. It includes: a membrane potential accumulation circuit, a waveform shaping circuit, a leakage circuit, a pulse generation circuit, a refractory period circuit, a dual-switching circuit, and logic gate circuits. The memristor LIF neurons of this invention achieve adjustable excitation peak pulse width, peak potential magnitude, and refractory period duration through changes in the resistance of the memristor and the switching characteristics of the MOSFET. This invention controls the memristor LIF neurons through a dual-switching circuit and logic gate circuits to realize the WTA mechanism, effectively improving the speed and accuracy of time-encoded information, enhancing the noise robustness and stability of the nervous system, and performing better in the face of competition from a large number of neurons. Furthermore, the memristor LIF neuron circuit and its WTA circuit of this invention use very few components, which is beneficial for increasing the integration density of neuromorphic chips.

Various 3D cells, array structures, and processes are disclosed. In an embodiment, a memory cell array structure is provided. The memory cell array structure includes memory cells organized into a plurality of rows and a plurality of columns, input lines in which each input line is connected to a memory cell in a selected row, and the input lines form an input line group, and output lines in which each output line is connected to a memory cell in a selected column, and the output lines form an output line group. The array structure further includes a multiplexer having a multiplexer input and a multiplexer output such that the multiplexer input is connected to the set of output lines, and a neuron circuit connected to the multiplexer output, the array of memory cells simulating a neural network, wherein the input line simulates an input layer neuron of the neural network, and the output line simulates an output layer neuron of the neural network.

The application discloses a neuron circuit, comprising: a trigger unit and an oscillation unit; the oscillation unit comprises a first memristor and a second memristor; one end of the first memristor is connected with one end of the second memristor, serving as an output end of the neuron circuit; the other end of the first memristor is connected with an output end of the trigger unit, and the other end of the second memristor is grounded; wherein the first memristor is used for adjusting a threshold value of the neuron circuit; when an input signal input into the trigger unit is greater than or equal to a first threshold value, the neuron circuit starts oscillation; when the input signal input into the trigger unit is less than the first threshold value, the neuron circuit stops oscillation; after continuous oscillation, the resistance value of the first memristor is increased, so that the first threshold value is increased; after the oscillation stops, the resistance value of the first memristor is gradually reduced, and the first threshold value is gradually fallen back, so that a dynamic threshold neuron is realized.

The invention discloses a spiking neuron circuit with temperature stability and a regulation and control method thereof, and relates to the technical field of semiconductors. According to the spiking neuron circuit, the drain electrode of a ferroelectric transistor FeFET is connected with a power supply, and the source electrode of the ferroelectric transistor FeFET is connected with the drain electrode of an MOSFET device; the source electrode of the MOSFET device is grounded; one end of the capacitor C is connected with the source electrode of the ferroelectric transistor FeFET and the drain electrode of the MOSFET device, and the other end of the capacitor C is grounded. The method comprises the following steps: introducing a carrier mobility temperature empirical model and a threshold voltage empirical model into a pre-constructed regulation and control model; by adjusting the grid voltage of the FeFET and the grid voltage of the MOSFET, the pulse neuron circuit and the emission frequency are independently controlled. The carrier mobility temperature empirical model and the threshold voltage empirical model are introduced, so that the functional stability of the whole spiking neuron circuit in a certain temperature range is ensured.

The invention discloses an LIF neuron circuit based on a self-powered threshold switch memristor and a preparation method of the LIF neuron circuit. The LIF neuron circuit comprises a friction nanometer generator, a rectifier bridge, a threshold TS memristor, a fixed value resistor and a capacitor. Dependence of a traditional artificial neuron on an external power supply and overall energy consumption of a system are remarkably reduced, meanwhile, key dynamic characteristics such as leakage, integration, distribution and delay of a biological neuron are efficiently simulated through cooperative charging and discharging behaviors of the memristor and the capacitor, a stimulation intensity-dependent frequency coding function is shown, and the simulation performance of the neuron is improved. And an effective hardware implementation scheme is provided for constructing a low-power-consumption and high-integration-level sensing and computing integrated neuromorphic system.

Disclosed is operation method of an encoder that receives a continuous time-series signal and respectively transmits first to N-th input signals to first to N-th input neuron circuits of spike neural network circuit. The method of operating the encoder includes receiving the continuous time-series signal, generating a plurality of discrete quantum signals by sampling and quantizing the continuous time-series signal, selecting first to N-th discrete quantum signals among the plurality of discrete quantum signals, matching the selected first to N-th discrete quantum signals with the first to N-th input neuron circuits, respectively, identifying discrete quantum signals, each of which has a quantum level different from a quantum level of a previous discrete quantum signal, from among the second to N-th discrete quantum signals, and activating the input signals to be transmitted to the input neuron circuits corresponding to the identified discrete quantum signals and the first discrete quantum signal.

The invention discloses a spiking neuron circuit with a self-resetting characteristic and a design method thereof, and relates to the technical field of spiking neurons. The circuit comprises a ferroelectric field effect transistor L1, a ferroelectric field effect transistor L2, a resistor R1 and a resistor R2, the L1 is used for simulating accumulation and leakage characteristics of biological neurons, a pulse signal transmitted from an input signal port VIN synapse is applied to a metal grid electrode of the L1 after passing through the resistor R1, a source electrode of the L1 is connected with power supply voltage VDD, a drain electrode of the L1 is connected with one end of the resistor R2, and the other end of the resistor R2 is connected with GND; the metal grid electrode of the L2 is connected with the output signal port VOUT, the source electrode of the L2 is connected with the GND, and the drain electrode of the L2 is connected with the resistor R1. According to the spiking neuron circuit with the self-reset characteristic, self-reset time adjustment can be achieved, and the non-stress behavior of the spiking neuron circuit is achieved through the L-FeFET. Compared with a traditional CMOS implementation mode, circuit complexity and power consumption are greatly reduced.

A neural network device according to an embodiment includes a plurality of synapse circuits and a plurality of neuron circuits. Each of the synapse circuits acquires one or more spike signals output from one of the neuron circuits, and, in response to acquiring the spike signals, outputs a synaptic current with a current amount corresponding to an assigned synaptic weight and the spike signals. A first neuron circuit out of the neuron circuits outputs N spike signals as the one or more spike signals. The first neuron circuit includes a spike output circuit to output at least an n-th spike signal out of the N spike signals when the membrane potential is higher than an n-th threshold potential out of the N threshold potentials different from each other.

A neural network device according to an embodiment includes a plurality of synapse circuits and a plurality of neuron circuits. In a first neuron circuit out of the neuron circuits, a synaptic current is supplied to a first terminal from each of one or more first synapse circuits out of the synapse circuits. The first neuron circuit includes a charge accumulation circuit, a spike output circuit, and a cutoff circuit. The charge accumulation circuit accumulates charge corresponding to the synaptic current and generates a membrane potential corresponding to the accumulated charge. The spike output circuit outputs a spike signal when the membrane potential is higher than a preset threshold potential. During a cutoff period that is a predetermined period of time after the output of the spike signal, the cutoff circuit stops the supply of the synaptic current from the first terminal to the charge accumulation circuit.

This invention relates to a low-power neuron circuit supporting multiple encoding methods. The neuron circuit includes a two-stage sensitive amplifier structure and corresponding logic control circuitry. Specifically, the input pulse signal generates an enable signal for the first-stage sensitive amplifier through delay control. The first-stage sensitive amplifier compares the neuron membrane capacitance potential Vmem with the first-stage threshold voltage Vrefs to determine whether to generate an enable signal for the second-stage sensitive amplifier. The output of the second-stage sensitive amplifier generates an output pulse signal through an SR latch. Further, the output pulse signal controls the resetting of the neuron based on the current input configuration signal. Compared with existing technologies, this invention has the advantages of low power consumption and support for multiple encoding methods.

The invention relates to a semiconductor device and an electronic apparatus. The neuron circuit is capable of switching two functions: a function as an input neuron circuit and a function as a hidden neuron circuit. The error circuit can switch two functions: function as a hidden error circuit and function as an output neuron circuit. The switching circuit is configured so as to be capable of changing connections among the neuron circuit, the synapse circuit, and the error circuit. The synapse circuit includes an analog memory storing data corresponding to a connection strength between the input neuron circuit and the hidden neuron circuit or between the hidden neuron circuit and the output neuron circuit, a write circuit that changes data in the analog memory; and a weighting circuit that weights an input signal in accordance with the data of the analog memory and outputs the weighted output signal. The analog memory includes a transistor including an oxide semiconductor with extremely low off-state current.

A method and an apparatus for processing an analog input signal using an analog neural network and generating a corresponding analog output signal are disclosed. An analog input interface is configured to supply a task input signal and a compensation input signal. One or more analog neuron circuits are connected to the analog input interface. An analog parameter storage array modifies task input signals and supplies these to an analog computation circuit that generates an output signal based on a combination of contributions from the modified task input signals and the compensation input signal.

The present invention relates to an integrate-and-fire neuron circuit for signed processing which is characterized by a feedback subcircuit connected to the positive and negative outputs of the circuit. This feedback subcircuit is configured to generate and output positive charge packets to a common line of the neuron circuit on each negative spike output signal and stored weights and to generate and output negative charge packets to the common line based on each positive spike output signal and stored weights. Due to this feedback circuit that is build in the same way as the input weighting circuit, structural matching and therefore higher accuracy and less variation of the behavior over PVT variations is achieved.