151 results about "Neuronal circuitry" patented technology

Disclosed herein are methods for modifying electrical currents in brain circuits through the simultaneous use of focused ultrasound pulse (FUP) and an existing brain-imaging system, such as a functional magnetic resonance imaging (fMRI) system. The methods are used for research, treatment and diagnosis of psychiatric, neurological, and neuroendocrine disorders whose biological mechanisms include brain circuits. The methods include the simultaneous steps of applying FUP to a live neuronal circuit within a brain and monitoring a brain image produced by a brain imaging system during the application of FUP.

The invention discloses a memristor-based neuron circuit, comprising a synaptic circuit, a neuron activation function circuit and a synaptic weight control circuit. In the synaptic circuit, a memristor, under the control of four MOS tubes, changes the memristor value to simulate the change of the synaptic weight in the neuron network. The designed neuron synaptic circuit is capable of being directly connected with a digital logic electrical level so as to achieve convenient and real-time adjustment to the synaptic weight and through the use of the feature that the output voltage of an operational amplifier is restricted by the power supply voltage, the neuron circuit activation function can be realized as a saturated linear function. The neuron synaptic weight change circuit can utilize the existing CMOS micro-controller and at the same time, the micro-controller can be loaded by the neuron network algorithm to change the synaptic weight to realize corresponding functions. According to the invention, a plurality of neuron circuits could be connected into a large-scale neuron network for complicated functions such as mode identification, signal processing, associated memory and non-linear mapping, etc.

The invention discloses a memristor-based neuron circuit. According to the neuron circuit, partially volatile bipolar resistive transition devices are selected and used as memristors of a synapse array, and a volatile resistive transition device is selected and used as a memristor for expressing membrane potential of neurons, so that the neuron circuit is formed; and synapse basis units are arranged. The neuron circuit can realize an integral discharge function in biological neurons and express local graded potentials; and synapses have partial volatility, can express spike-timing-dependent plasticity, and have great similarity with biological neurons and synapses in the aspects of information storage, transmission and processing. According to the neuron circuit, the basic units can be provided for hardware to simulate a cerebral neural network structure; the technical problems of neuron discharge time delay, difficulty in realizing high-density integration and the like in the prior art are solved; and the neuron circuit can be used for constructing a brain-like information processing system, can quickly process a large amount of information in parallel, and has a greatly high application value in realizing a cerebral neurologic calculation network.

To provide a semiconductor device with a small circuit size and low power consumption or an electronic device including the semiconductor device and compressing a large volume of image data. A semiconductor device of a Hopfield neural network is formed using neuron circuits and synapse circuits. The synapse circuit includes an analog memory and a writing control circuit, and the writing control circuit is formed using a transistor including an oxide semiconductor in a channel formation region. Thus, data retention lifetime of the analog memory can be extended and refresh operation for data retention can be omitted, so that power consumption of the semiconductor device can be reduced. The semiconductor device enables judgement whether learned image data and arbitrary image data match, are similar, or mismatch by comparing video data. Thus, motion compensation prediction, which is one of data compression methods, can be employed for image data.

A mobile brain-based device BBD includes a mobile base equipped with sensors and effectors (Neurally Organized Mobile Adaptive Device or NOMAD), which is guided by a simulated nervous system that is an analogue of cortical and sub-cortical areas of the brain required for visual processing, decision-making, reward, and motor responses. These simulated cortical and sub-cortical areas are reentrantly connected and each area contains neuronal units representing both the mean activity level and the relative timing of the activity of groups of neurons. The brain-based device BBD learns to discriminate among multiple objects with shared visual features, and associated “target” objects with innately preferred auditory cues. Globally distributed neuronal circuits that correspond to distinct objects in the visual field of NOMAD 10 are activated. These circuits, which are constrained by a reentrant neuroanatomy and modulated by behavior and synaptic plasticity, result in successful discrimination of objects. The brain-based device BBD is moveable, in a rich real-world environment involving continual changes in the size and location of visual stimuli due to self-generated or autonomous, movement, and shows that reentrant connectivity and dynamic synchronization provide an effective mechanism for binding the features of visual objects so as to reorganize object features such as color, shape and motion while distinguishing distinct objects in the environment.

The invention discloses a control method applicable to a resistance changing memory resistor of a nerve cell circuit. According to the control method disclosed by the invention, two ports of a resistance changing memory resistor are respectively connected with a drain terminal and a source terminal of an MOS (metal oxide semiconductor) transistor, a parallel connection structure is formed, the parallel connection structure is respectively connected with a front nerve cell and a rear nerve cell, and a gate voltage is added on a gate terminal of the MOS transistor. according to the invention, the resistance changing memory resistor is connected with the MOS transistor in parallel, in a study state, the resistance changing memory resistor is set to a preset resistance value by adjusting the gate voltage of the MOS transistor; and in a calculation state, channel resistance of the MOS transistor is controlled by virtue of the gate voltage, thus resistance value of the parallel connection structure of the resistance changing memory resistor and the MOS transistor is accurately controlled, and the resistance of the parallel connection structure is rapidly and accurately adjusted. Area of the MOS transistor can be small, thus being beneficial to large-scale integration; meanwhile, the gate voltage of the MOS transistor is controlled, change of the resistance of the resistance changing memory resistor can be realized, and resistance floating can be accurately controlled.

The invention discloses a pulse coupling based silicon-nanowire CMOS (complementary metal oxide semiconductors ) neuronal circuit, which consists of a dendrite circuit, an integral summer and a pulse generating circuit, and the dendrite circuit, the integral summer and the pulse generating circuit are sequentially connected. The invention is characterized in that the outputs and inputs of the neuronal circuit are all pulse trains, and the components of the neuronal circuit are all silicon-nanowire CMOS transistors; the dendrite circuit is a CMOS circuit consisting of a set of parallelly-connected P-type nanowire MOS (metal oxide semiconductor ) transistors and an N-type nanowire MOS transistor which are connected in series by drain-terminal nodes, and the source terminals of the P-type nanowire MOS transistors input pulse voltage signals; the integral summer consists of a capacitor C sigma, and the capacitor is connected with the drain-terminal nodes of the P-type and N-type nanowire MOS transistors in the dendrite circuit and used for accumulating and weighting currents so as to form trigger voltage signals; and the pulse generating circuit is a feedback loop consisting of a plurality of even numbered serially-connected CMOS phase inverters and a dendrite CMOS circuit, and used for producing and outputting pulse trains, wherein the output frequency of the pulse trains is modulated by the input voltage pulse signals.

The invention discloses a digital-analog hybrid neural network chip architecture. The architecture comprises a two-dimensional SRAM module, an analog synaptic circuit, a nerve cell circuit, an AER communication module, and a master control digital unit. The two-dimensional SRAM module is taken as a storage unit of neural network connection relation and a synaptic weight value. The analog synaptic circuit and the nerve cell circuit respectively consist of an MOSFET circuit working in a subthreshold section. The AER communication module serves as the input and output interfaces of a chip, and employs an AER protocol for communication. All control circuits in the architecture are synchronous digital circuits. The architecture is low in power consumption, is high in degree of parallelism, and can achieve a neural network algorithm in a reasonable chip area, wherein the neural network algorithm is more complex in nerve cell functions, is larger in network scale, and is more flexible in connection.

The embodiment of the invention provides a neural simulation circuit, and the circuit comprises a first circuit, wherein the first end of the first circuit is connected with the input end Vin of a first neuron circuit, and the second end of the first circuit is connected with the output end Vout of the first neuron circuit; a capacitor C1, wherein the first end of the capacitor C1 is connected with the third end of the first circuit, and the second end of the capacitor C1 is connected with the ground; a second circuit, wherein the input end of the second circuit is connected with the third end of the first circuit, the output end of the second circuit is connected with the output end Vout of the first neuron circuit, and the second circuit is switched on when the voltage of the first end of the capacitor C1 is greater than a voltage threshold value; and a switching tube T1, wherein the input end of the switching tube T1 is connected with the third end of the first circuit, the output end of the switching tube T1 is connected with the ground, and the control end of the switching tube T1 is connected with the output end Vout of the first neuron circuit. According to the embodiment of the invention, the circuit can simulate the threshold characteristic of theca cells.

The present invention discloses a time correlation learning neuron circuit based on a resistive memristor and an implementation method thereof. The present invention utilizes switching characteristics of the resistive memristor. When two terminals of the resistive memristor are selected synchronously by two excitation signals, the voltage drop between these two terminals will change the resistance value of memristor, thereby achieving the on-off of a synapse connection and achieving the correction of the two excitation signals. Meanwhile the device also has a memory characteristic. Also, the previous excitation signal can be repeated. That is, the purpose of learning is achieved. Since the resistive memristor has a simple structure and a high degree of integration, it can achieve large-scale physical synapse connection in order to achieve more complex learning and even logic functions. The present invention has a good application prospect in a neuron cell computation.

The invention discloses a nerve cell synapse circuit and a nerve cell circuit, wherein the nerve cell synapse circuit comprises a charging circuit, a discharging circuit and an MOS (metal oxide semiconductor) capacitor, wherein the MOS capacitor is connected with the charging circuit and the discharging circuit; the charging circuit and the discharging circuit are both formed by a plurality of MOS devices, and are connected into a pulse sequence generated by nerve cells before the synapse and a pulse sequence generated by the nerve cells after the synapse; the charging circuit is constructed to charge the MOS capacitor when the pulse sequence generated by the nerve cells before the synapse is reached earlier than the pulse sequence generated by the nerve cells after the synapse so that the simulation voltage for increasing the synapse weight is output; the discharging circuit is constructed to discharge the MOS capacitor when the pulse sequence generated by the nerve cells before the synapse is reached later than the pulse sequence generated by the nerve cells after the synapse so that the simulation voltage for decreasing the synapse weight is output. The nerve cell synapse circuit and the nerve cell circuit provided by the invention have the advantages that the circuit power consumption can be reduced; the integration degree is improved.

A neural network processing system includes at least one synapse and a neuron circuit. The synapse receives an input signal and has an external weighted value and an internal weighted value, and the internal weighted value has a variation caused by an external stimulus. When the variation of the internal weighted value accumulates to a threshold value, the external weighted value varies and the input signal is multiplied by the external weighted value of the synapse to generate a weighted signal. A neuron circuit is connected with the synapse to receive the weighted signal transmitted by the synapse, and calculates and outputs the weighted signal. The present invention can simultaneously accelerate the prediction and learning functions of the deep learning and realize a hardware neural network with high precision and real-time learning.

A neuron circuit in a neural network circuit element includes a waveform generating circuit for generating a bipolar sawtooth pulse voltage, and a first input signal has a bipolar sawtooth pulse waveform. For a period during which the first input signal is permitted to be input to a first electrode of a variable resistance element, the bipolar sawtooth pulse voltage generated within the neural network circuit element including the variable resistance element which is applied with the first input signal from another neural network circuit element is input to a control electrode of the variable resistance element. The resistance value of the variable resistance element changes due to an electric potential difference between the first electrode and the control electrode, the electric potential difference being generated depending on an input timing difference between a voltage applied to the first electrode and the voltage applied to the control electrode.

A method of inhibiting excitotoxicity by indirectly activating α4β2 nicotinic acetylcholine receptors (nAChRs) which indirectly activate synaptic AMPA and NMDA receptors is disclosed. Inhibitors of α7 nACHRs, such as macrocyclic diterpenoids, more specifically cembranoids or methyllycaconitine (MLA), indirectly activate α4β2 nAChRs and can be used to treat neurodegenerative diseases, including, but not limited to, Alzheimer's Disease, Parkinson Disease, AIDS related dementia and the delayed effects of stroke. They can also be used to treat diseases associated with neuronal impairment, including, but not limited to glaucoma caused by optical nerve damage, delayed effects of epilepsy; and multiple sclerosis.

The invention discloses a neuron circuit including memristor elements, a trigger element, feedback elements and AND gates, wherein the memristor element is configured to receive an excitation signal,the trigger element is connected to the memristor element, and receives a clock control signal of the circuit and a signal outputted from the memristor element, the feedback element is used for connecting the output terminal of the trigger element and the input terminal of the memristor element, and controlling the voltage of the input terminal of the memristor element. The AND gate circuit is used for performing AND operation on the output signal of the trigger element and the clock control signal, and the output signal of the AND gate circuit is used as the output signal of the neuron circuit. The invention also relates to a neural network circuit.

Provided is a neuromorphic system using a neuron circuit. The neuromorphic system includes: one or two or more neuron circuits configured to output a firing signal according to signals input from a synapse array; a homeostatic circuit for each neuron circuit; and a global self-controller configured to generate and provide control signals for the neuron circuits by using the firing signal output from the neuron circuits. The neuron circuit includes a neuromorphic device and an output circuit that outputs the firing signal of the neuromorphic device. The global self-controller generates and supplies a reset signal to the neuromorphic device of the fired neuron circuit, and the global self-controller generates and supplies a lateral inhibition signal to the neuromorphic device of the non-fired neuron circuit. The homeostatic circuit alleviates inhibition of other neurons by the neurons with a predominant firing function.

The invention discloses a method for weight control and information integration by utilizing time encoding, which comprises the following steps: utilizing a dendritic circuit to control the spatial distribution of weight; utilizing the dendritic circuit to realize the corresponding relationship between characteristic parameters and the weight; and utilizing the dendritic circuit to control the time distribution of the weight. The invention utilizes the organic combination of input signals distributed in time and space to realize the dynamic distribution control of the weight, utilizes the noise margin characteristics of a CMOS inverter to change the output pulse frequency of a neuron circuit, so that the digital signals increase simulated change parameter. The invention helps to understand and simulate information processing way of biological neurons.

The invention is applicable to the computer technical field and provides a neuron circuit, a chip, a system and a method thereof, and a storage medium. The neuron circuit comprises the following structures: a calculation module; a configuration information storage module, configured to store configuration information of a neuron processing mode; and a control module, configured to control the computing module to adjust to the corresponding computing infrastructure and execute the corresponding neural network layer node data processing according to the processing mode configuration information.In this way, it can meet the fast iteration of complex and diverse neural network computing needs, can be widely used in computing resources are limited, the need for a certain neural network architecture reconfigurable areas, expand the depth of learning chip applications.