5results about How to "Meet computing needs" patented technology

The invention provides a calculation engine and a data processing method thereof, a processing chip and computer equipment, the calculation engine comprises a dot multiplication unit array and a control logic unit, the dot multiplication unit array comprises a plurality of dot multiplication units, and each dot multiplication unit comprises a first calculation unit group and a second calculation unit group, the point multiplication unit supports point multiplication of data equal to or lower than the first precision; a second calculation unit group supporting point multiplication of data equal to or lower than a second precision, the second precision being lower than the first precision; the third calculation unit group supports point multiplication operation of data with third precision, the third precision is lower than the second precision, the control logic unit reads data to be processed according to an obtained control instruction and transmits the data to the point multiplication unit array, and when the data to be processed is the data with the third precision, the point multiplication operation of the data to be processed is carried out. And the control logic unit transmits the data with the third precision to the dot multiplication unit according to a data processing mode.

The application discloses a data processing method and device, and relates to the technical field of computers. A specific implementation manner of the method comprises the following steps: in response to user operation on data, an operation statement of current operation is parsed to obtain a parsing result, and the parsing result comprises an operation object; an operation record file name of last operation of the operation object is acquired; the parsing result and the operation record file name of last operation of the operation object are spliced to generate an operation record of current operation; and the operation record of current operation is saved into a blood relationship database. The implementation manner has the advantages that the data warehouse technical architecture is simple in structure, does not need to perform layered processing on data, the data blood relationship traceability is simple, and operation transaction consistency can be maintained; meanwhile, the construction cost of the data warehouse system is greatly reduced, and the flexibility is high.

The application discloses a low-bit matrix calculation device with a floating-point scaling factor and a calculation method thereof. The device comprises a scaling factor processing module, an input module, a matrix calculation module, a floating-point accumulation module and an output module. The method first groups and quantizes weight and eigenvalue matrices to obtain quantization values and floating-point scaling factors; then, the scaling factor product is calculated in advance with a single accumulation length as a grouping unit; then, matrix multiplication and accumulation operation is performed, the result is multiplied by the scaling factor product after being converted into an fp16 or bfp16 format, and then accumulated into a final result; and finally, the result is output after being dequantized. The application simplifies the group-wise calculation process, saves hardware resources, guarantees calculation accuracy, meets different scene requirements and improves calculation efficiency by sharing the scaling factor product and using fp16 or bfp16 as an accumulator.

The invention discloses a matrix multiplication optimization method and system oriented to an RISC-V architecture, and the method comprises the steps: detecting the hardware characteristics of a target RISC-V platform, and adaptively configuring optimization parameters according to a detection result; performing memory layout and data rearrangement on the input matrix B to realize memory optimization; a multi-level partitioning strategy is adopted to adapt to a memory hierarchical structure, and multi-level partitioning calculation is achieved; carrying out RVV vectorization core calculation by using RISC-V vector instruction extension to realize data-level parallel optimization; the instruction delay is hidden through loop expansion and a software assembly line, and a data prefetching mechanism is adopted to realize instruction-level parallel optimization; performing multi-core parallel computing by using an OpenMP multi-thread technology to realize thread-level parallel optimization; and calculating residual elements by using a vector register to realize tail processing optimization. According to the method, the cache hit rate and the calculation performance degree are improved, the hardware potential is fully excavated, and the method is suitable for edge devices with high requirements.

The present application provides a multi-interferometer assisted unmanned aerial vehicle covert relay-edge computing method and system, comprising: in the unmanned aerial vehicle covert relay and edge computing network, the device-to-unmanned aerial vehicle covert relay rate and the unmanned aerial vehicle-to-server covert relay rate are derived respectively; under the assistance of multiple interferometers, the first minimum detection error rate of the guard against device communication and the second minimum detection error rate of the guard against unmanned aerial vehicle communication are derived; based on the obtained covert relay rate, the first minimum detection error rate and the second minimum detection error rate, the joint optimization model is constructed and solved with the maximum edge computing amount of the minimum device as the target. The present application maximizes the concealment and computing efficiency in the unmanned aerial vehicle edge computing network, can fully utilize the limited wireless communication and hardware computing resources, and can resist the detection of illegal guards while meeting the computing demand of edge devices.