12results about How to "Meet computing needs" patented technology

The invention relates to the field of data processing, in particular to an instruction optimization scheduling method based on a large model and a related device. The method comprises the following steps: for a to-be-processed target model, carrying out dynamic and static analysis on the target model to convert the target model into a calculation task graph; determining a scheduling priority of each instruction in the target model based on a calculation task graph; the scheduling priority is associated with the importance and timeliness of the instruction path of each instruction in the calculation task graph; dynamically adjusting an instruction scheduling strategy in the calculation task graph based on the scheduling priority; and dynamically optimizing the instruction scheduling strategy according to the register pressure state monitored in real time, and executing the optimized instruction scheduling strategy. According to the method, instruction scheduling optimization can be achieved, the resource utilization efficiency is improved, the calculation requirement of a large model is met, and the overall model performance is improved.

The invention provides an image enhancement system and method and a medium. The system comprises (N-1) row cache FIFO (First In First Out) which are connected in series, N row cache registers, a Demosaic module, a G component cache FIFO and a G component cache register. According to the invention, by reasonably controlling the read-write of the row cache FIFO and the register, at least five pixel points are output all the time under the condition that any number of pixel data is transmitted for each row of image data of each clock, so that the calculation requirement of the Demosaic algorithm is met. Under the condition of balancing and optimizing the combinational logic series to be executed in each clock period and the occupation of the total register, in the pipeline design of the Demosaic algorithm, the finiteness of hardware internal resources and the time sequence convergence problem of high clock frequency are fully considered, and by combining the combinational logic series optimization and the pipeline series optimization, the time sequence convergence problem of the high clock frequency is fully solved. In this way, better occupation of various resources of the FPGA is achieved, and efficient calculation is achieved. Based on the calculation strategy provided by the invention, the image enhancement process is finally realized, and the high-quality color display image is obtained.

The invention provides a calculation engine and a data processing method thereof, a processing chip and computer equipment, the calculation engine comprises a dot multiplication unit array and a control logic unit, the dot multiplication unit array comprises a plurality of dot multiplication units, and each dot multiplication unit comprises a first calculation unit group and a second calculation unit group, the point multiplication unit supports point multiplication of data equal to or lower than the first precision; a second calculation unit group supporting point multiplication of data equal to or lower than a second precision, the second precision being lower than the first precision; the third calculation unit group supports point multiplication operation of data with third precision, the third precision is lower than the second precision, the control logic unit reads data to be processed according to an obtained control instruction and transmits the data to the point multiplication unit array, and when the data to be processed is the data with the third precision, the point multiplication operation of the data to be processed is carried out. And the control logic unit transmits the data with the third precision to the dot multiplication unit according to a data processing mode.

The application discloses a data processing method and device, and relates to the technical field of computers. A specific implementation manner of the method comprises the following steps: in response to user operation on data, an operation statement of current operation is parsed to obtain a parsing result, and the parsing result comprises an operation object; an operation record file name of last operation of the operation object is acquired; the parsing result and the operation record file name of last operation of the operation object are spliced to generate an operation record of current operation; and the operation record of current operation is saved into a blood relationship database. The implementation manner has the advantages that the data warehouse technical architecture is simple in structure, does not need to perform layered processing on data, the data blood relationship traceability is simple, and operation transaction consistency can be maintained; meanwhile, the construction cost of the data warehouse system is greatly reduced, and the flexibility is high.

The application discloses a low-bit matrix calculation device with a floating-point scaling factor and a calculation method thereof. The device comprises a scaling factor processing module, an input module, a matrix calculation module, a floating-point accumulation module and an output module. The method first groups and quantizes weight and eigenvalue matrices to obtain quantization values and floating-point scaling factors; then, the scaling factor product is calculated in advance with a single accumulation length as a grouping unit; then, matrix multiplication and accumulation operation is performed, the result is multiplied by the scaling factor product after being converted into an fp16 or bfp16 format, and then accumulated into a final result; and finally, the result is output after being dequantized. The application simplifies the group-wise calculation process, saves hardware resources, guarantees calculation accuracy, meets different scene requirements and improves calculation efficiency by sharing the scaling factor product and using fp16 or bfp16 as an accumulator.

The invention relates to the technical field of integrated circuits, and discloses a hysteresis comparator circuit based on a double-gate field effect transistor and an integrated chip, the hysteresis comparator circuit comprises at least two cascaded phase inverters, each phase inverter at least comprises an input tube and a load tube, the input tube is connected with the load tube, and the load tube is connected with the input tube. The drain electrode of the input tube is connected with the source electrode of the load tube, a connection node is configured as the output end of the phase inverter, and at least one of the input tube and the load tube of each phase inverter is a double-gate field effect tube; the feedback electric wire is connected between the second grid electrode of the double-grid field effect transistor in the first-stage phase inverter and the output ends of the other phase inverters, so that signals on the first grid electrode and the second grid electrode of the double-grid field effect transistor change in an in-phase mode, and positive feedback for achieving the hysteretic effect is formed. According to the hysteresis comparator, the common modulation effect of the two grid electrodes of the double-grid field effect transistor is utilized to form the hysteresis effect, the on-chip integration difficulty of the hysteresis comparator is reduced, and the flexibility of the hysteresis comparator is improved.

The invention discloses a matrix multiplication optimization method and system oriented to an RISC-V architecture, and the method comprises the steps: detecting the hardware characteristics of a target RISC-V platform, and adaptively configuring optimization parameters according to a detection result; performing memory layout and data rearrangement on the input matrix B to realize memory optimization; a multi-level partitioning strategy is adopted to adapt to a memory hierarchical structure, and multi-level partitioning calculation is achieved; carrying out RVV vectorization core calculation by using RISC-V vector instruction extension to realize data-level parallel optimization; the instruction delay is hidden through loop expansion and a software assembly line, and a data prefetching mechanism is adopted to realize instruction-level parallel optimization; performing multi-core parallel computing by using an OpenMP multi-thread technology to realize thread-level parallel optimization; and calculating residual elements by using a vector register to realize tail processing optimization. According to the method, the cache hit rate and the calculation performance degree are improved, the hardware potential is fully excavated, and the method is suitable for edge devices with high requirements.

The present invention discloses a real-time electric and thermal dispatching method and system for a park that is adaptable to a combination of multi-energy equipment in multiple scenarios. The method obtains an equipment parameter table according to the actual operation of the multi-energy park; selects different electric equipment and thermal equipment for actual operation of the multi-energy park; obtains the current actual operation status and real-time operation data of each type of equipment, and obtains the dispatching reference value obtained by the day-ahead dispatching or rolling dispatching calculation in multiple time scales according to the current number of operation periods; performs component modeling on the equipment actually online in the multi-energy park according to the dispatching reference value and the current operation conditions of each equipment in the multi-energy park, and uses a heuristic algorithm to obtain the real-time dispatching control results of each equipment in the multi-energy park; and uses the dispatching correction amount and power reference value of each type of equipment in the real-time dispatching results of the multi-energy park to realize the dispatching control of the equipment in a single period of the day. The method ensures that the equipment in the regional electric and thermal integrated energy system can be flexibly combined and can operate reliably and stably.

The present invention proposes a method and system for intelligent coal mine computing power scheduling based on deep reinforcement learning, the method includes: the equipment terminal of the mining face generates real-time computing tasks and sends real-time status information to the cloud; the cloud establishes a computing power scheduling optimization model that minimizes the computing time based on the status information, adopts a deep reinforcement learning algorithm, considers the location of the terminal device, task requirements, task calculation amount, its own computing power, channel conditions and edge computing server, forms a cloud-edge collaborative computing strategy and a scheduling plan for drones, and sends the task splitting method, unloading strategy, computing power allocation plan and drone hovering position information to the drone and edge computing server. After the deep reinforcement learning training is completed, the present invention can form an efficient task unloading and resource allocation plan, effectively reducing the delay of computing tasks on the mining face.

The application discloses a four-zone arrangement whole-roller type plate shape instrument measurement and control device and method, belongs to the metallurgical rolling equipment automation measurement and control technical field, the device integrates the plate shape measurement and control full-link function in the single standard control cabinet, adopts the four-zone vertical stratification layout from top to bottom, realizes the signal flow and the power flow physical isolation; the control cabinet protection level reaches IP54, integrates the independent dustproof and moistureproof device and the intelligent heat dissipation system; carries the high-performance industrial computer and the double independent gigabit network port, integrates nine big function modules of signal acquisition, channel decoupling, multi-source process error comprehensive compensation, target curve intelligent setting and control amount calculation. The application realizes the hardware compactness, the protection standardization, the data processing high performance and the software function integration, significantly improves the cold-rolled plate shape measurement and control precision and the system operation reliability under the harsh industrial environment.

The present application provides a multi-interferometer assisted unmanned aerial vehicle covert relay-edge computing method and system, comprising: in the unmanned aerial vehicle covert relay and edge computing network, the device-to-unmanned aerial vehicle covert relay rate and the unmanned aerial vehicle-to-server covert relay rate are derived respectively; under the assistance of multiple interferometers, the first minimum detection error rate of the guard against device communication and the second minimum detection error rate of the guard against unmanned aerial vehicle communication are derived; based on the obtained covert relay rate, the first minimum detection error rate and the second minimum detection error rate, the joint optimization model is constructed and solved with the maximum edge computing amount of the minimum device as the target. The present application maximizes the concealment and computing efficiency in the unmanned aerial vehicle edge computing network, can fully utilize the limited wireless communication and hardware computing resources, and can resist the detection of illegal guards while meeting the computing demand of edge devices.

The invention discloses a universal configurable Transformer hardware accelerator and an implementation method thereof. All operation requirements of the entire network layer can be met through a computing engine array, a Softmax operation module and a LayerNorm operation module. The computing engine array improves the computing parallelism in the accelerator, and improves the utilization rate of data loaded into the internal cache of the accelerator while accelerating the computing speed. The storage areas of the on-chip cache module can store feature data, bias matrix data, weight data and parameter data separately, thereby improving the efficiency of subsequent data reading, reducing the delay of the memory access process and improving the operation efficiency. The parallelism of the computing engines, the number of computing engines and the operation parallelism of the nonlinear layer can all be configured through a control module, and the deployment and implementation of the model can be completed according to different computing resources. The invention can be widely applied to the technical field of neural network models.