33 results about "Reconfigurable array" patented technology

The invention discloses a linear polarization scattering reconfigurable array antenna, which belongs to the technical field of antenna manufacturing and comprises an antenna unit, an extension socket, a transmission type phase shifter and an inductor. The antenna unit comprises a radiation patch, a first dielectric substrate, a metal via hole, a metal patch, a second dielectric substrate, a perforated metal floor, a third dielectric substrate, a feed metal column and a radio frequency coaxial connector, the radio frequency coaxial connector is connected with the radiation patch through the feed metal column, and a variable capacitance diode and a capacitor are arranged on the transmission type phase shifter. The transmission type phase shifter is connected with the radiation patch through the feed metal column, the variable capacitance diode is connected with the punching metal floor, the bottom of the third dielectric substrate is provided with a direct current bias line, the direct current bias line is connected with the transmission type phase shifter through the inductor, and the transmission type phase shifter is connected with the radiation patch through the feed metal column. According to the invention, flexible regulation and control of antenna scattering beams can be realized, and the antenna has the characteristics of flexible control, fast response speed and high radiation efficiency.

The invention provides a near-field feed low-complexity reconfigurable antenna system, which belongs to the technical field of millimeter wave communication antennas and comprises a 1-bit phased array, a waveguide feed horn array and an air gap between the 1-bit phased array and the waveguide feed horn array. The 1-bit unit is composed of two magnetoelectric dipoles, and two diodes are integrated in the receiving unit to achieve 1-bit phase control. According to the 1-bit reconfigurable magnetoelectric dipole phased array disclosed by the invention, one horn mouth surface is used as a near-field feed source of the 2 * 2 magnetoelectric dipole sub-array, so that not only is the uniformity of aperture irradiation ensured through near-field coupling, but also the number of required phase shifters is reduced, and the excitation of the 1-bit reconfigurable magnetoelectric dipole phased array is conveniently realized. The waveguide phase shifter is directly integrated in the horn array antenna, by means of the working phase range wide enough, the phase shifter can effectively achieve phase distribution needed by array near-field feed, and mirror lobes in scanning beams are successfully suppressed. The reconfigurable array antenna is high in aperture efficiency, low in profile and simple in structure, and has the broadband scanning capability.

This application belongs to the field of antenna technology and relates to a polarization rotation unit and a beam reconfigurable array antenna. The polarization rotation unit includes a patch layer, a dielectric layer, and a control layer. The patch layer includes a first radiating patch and four spaced arrays of second radiating patches. The first radiating patch is square, and any diagonal of the first radiating patch forms a 45° angle with any diagonal of the dielectric layer. The second radiating patches include two or more rectangles of different sizes, with two sides of any adjacent rectangles collinear, and each rectangle is axially symmetric about one diagonal of the dielectric layer. The first radiating patch and each of the second radiating patches are connected by diodes, with diodes in the same direction having the same direction and diodes in different directions having opposite directions. The control layer is connected to the patch layer to control the on and off states of each diode and supports programmability. This application can realize polarization rotation and state reconfigurability.

The application relates to an inter-cluster multi-task dynamic scheduling controller and method based on a reconfigurable computing array, which comprises a task sliding window unit configured to extract task information from a task queue to form a sliding window; a state register unit configured to receive and store real-time state information fed back by a plurality of reconfigurable array clusters; a scheduling control unit connected with the task sliding window unit and the state register unit respectively and configured to generate a scheduling decision according to the task information in the sliding window and the real-time state information of each reconfigurable array cluster; and a task distribution unit connected with the scheduling control unit and configured to receive a task instruction to be issued and the scheduling decision, modify a cluster addressing field in the task instruction according to target cluster information in the scheduling decision, and issue the modified task instruction to the reconfigurable array cluster indicated by the target cluster information, so as to solve the problem of waste of computing resources in the prior art.

A method for sharing reconfigurable array modes in a MIMO frequency-modulated millimeter-wave radar array is proposed. Based on the echo signal data matrices obtained after analog-to-digital conversion of different modes, range-dimensional Fast Fourier Transform (FFT) and velocity-dimensional FFT are performed on them respectively to obtain the range-Doppler spectrum of different transmit / receive antenna combinations. Different modes with the same gain in the MIMO radar system are combined. Among the combinations with the same gain, the mode corresponding to the largest virtual array aperture in the horizontal and elevation directions under that gain is selected. The angles of these two modes are resolved and matched separately, and then combined to achieve the maximum virtual array aperture resolution. Digital beamforming is used to match the angle information obtained under the maximum aperture virtual array in the horizontal and elevation dimensions. This invention can effectively increase the maximum array aperture in the original modes with the same gain by utilizing the complementary effect between different reconfigurable array modes while using virtual array reconfigurable technology or MIMO technology.

The present disclosure provides a three-dimensional coarse-grained reconfigurable array architecture system and its control method. The system includes multiple first arrays and multiple second arrays, wherein each first array includes multiple first processing elements, multiple first memory units, and multiple first switches, and each second array includes multiple second processing elements, multiple second memory units, and multiple second switches. The system employs an interleaved stacking arrangement for the first arrays and second arrays, and dynamically manages the activation and deactivation states of various units through a configuration controller to execute neural network model computation tasks. The technical solution of the present disclosure can significantly improve data transmission efficiency, increase resource utilization flexibility, and achieve optimal allocation of hardware resources.

The present application relates to the technical field of data cleaning, and more particularly to a stream data cleaning accelerator based on FPGA, which comprises a coarse-grained reconfigurable array cleaning pipeline arranged in a programmable logic region of an FPGA chip and comprising a plurality of processing units; each processing unit is internally provided with an arithmetic logic operation core, a local register stack, a crossbar router and an instruction buffer; a configuration controller is used to issue function configuration instructions to each processing unit in the coarse-grained reconfigurable array cleaning pipeline; a quantitative perception stream neighbor interpolation engine; an interpolation value generation module is used to generate interpolation values according to a precise neighbor set; and a data interface is used to receive original data streams to be cleaned and output cleaned data records. The problems of insufficient throughput of traditional data cleaning schemes and excessively high computational complexity of K-neighbor interpolation methods are effectively solved.

The application relates to a linearly polarized in-band co-polarized scattering reconfigurable array antenna, which comprises antenna modules arranged in an array by a plurality of same antenna units. Each antenna unit adopts a multi-layer stacked structure: from top to bottom, a radiation patch, a first dielectric substrate, a metal patch, a second dielectric substrate, a metal ground plate and a third dielectric substrate are sequentially arranged. A plurality of metalized through holes are arranged on the center line of the first dielectric substrate, and the metalized through holes, the metal patch and the metal ground plate jointly form a resonator. Each unit is also integrated with a reflective phase shifter, which comprises a microstrip transmission line, a feeding metal column, a metal short circuit column and a varactor diode. The feeding metal column penetrates through the layers and is connected with the radiation patch, and the metal short circuit column is connected with the metal ground plate. The varactor diode receives external control through a direct current bias line, the reflection phase of the unit is adjusted by changing the bias voltage, and the in-band co-polarized scattering reconfigurable function of the antenna is realized. The device can realize flexible regulation and control of a wide range and low coupling of scattering characteristics while maintaining high stable radiation characteristics.

The application discloses an electromagnetic wave emission method and a reconfigurable metasurface integrated based on 4D printing, and belongs to the technical field of microwaves. The electromagnetic wave emission method comprises the following steps: obtaining a target voltage; based on the target voltage, controlling the 4D switch to deform towards a target direction, and obtaining an equivalent capacitance corresponding to the 4D switch after deformation; based on the equivalent capacitance, regulating an electromagnetic wave signal and controlling the radiation surface to emit the electromagnetic wave signal. The electromagnetic wave emission method can regulate the electromagnetic wave signal based on the demand voltage, can meet the demand of various application scenarios, reduces the weight and cost of the reconfigurable array antenna, and simplifies the manufacturing process.

The application discloses a linear polarization scattering reconfigurable array antenna and belongs to the technical field of antenna manufacturing, which comprises an antenna unit, an array plug, a transmission type phase shifter and an inductor, wherein the antenna unit comprises a radiation patch, a first dielectric substrate, a metal via, a metal patch, a second dielectric substrate, a perforated metal floor, a third dielectric substrate, a feeding metal column and a radio frequency coaxial connector; the radio frequency coaxial connector is connected with the radiation patch through the feeding metal column; the transmission type phase shifter is provided with a varactor diode and a capacitor and is connected with the radiation patch through the feeding metal column; the varactor diode is connected with the perforated metal floor; the bottom of the third dielectric substrate is provided with a direct current bias line; the direct current bias line is connected with the transmission type phase shifter through the inductor; and the transmission type phase shifter is connected with the radiation patch through the feeding metal column. The application can realize flexible regulation and control of the antenna scattering beam and has the characteristics of flexible control, fast response speed and high radiation efficiency.

The invention provides a high-reliability multi-data flow diagram execution device, which is characterized in that a proxy distribution module is used for storing a pre-generated data flow diagram pool when a current program is executed, and a plurality of data flow diagrams in the data flow diagram pool are loaded to a reconfigurable array in parallel under the control of a feedback control module; when the data flow diagram is wrongly calculated, other data flow diagrams which belong to the same program with the data flow diagram which is wrongly calculated are scheduled; the reconfigurable computing array is used for executing a plurality of heterogeneous data flow diagrams corresponding to the same to-be-executed program in parallel; the strategy judgment module is used for judging whether calculation is correct or not, outputting a result when the calculation is correct, marking a data flow diagram of a calculation error when the calculation result is wrong, and feeding back the data flow diagram to the reconfigurable calculation array and the feedback control module; and the feedback control module is used for controlling the operation of the whole device and sending the received feedback information to the proxy distribution module so as to control the proxy distribution module to schedule and calculate other data flow diagrams, belonging to the same program, of the wrong data flow diagrams in the diagram pool.

The invention provides a common excitation amplitude sparse reconfigurable array synthesis method, and relates to an information transmission and processing technology. The method comprises the following steps: 1) constructing a mathematical optimization model through a radiation characteristic requirement and a null requirement of a to-be-synthesized wave beam, and solving the mathematical optimization model by using particularity of conjugate symmetric excitation and a continuous convex approximation algorithm; 2) utilizing a feasible point tracking algorithm, introducing a slack variable to help to solve a feasible point, and overcoming a non-feasible solution caused by non-convex constraint; the method has the advantages that a plurality of radiation directional diagrams can be formed by one sparse array, so that a plurality of different application scenes can be met; the number of array elements is reduced through the design of a sparse array, so that the system cost is further reduced; due to the characteristic of excitation weight conjugate symmetry, optimization variables are remarkably reduced, and the advantages of the method on a large-scale array are highlighted; the DRR constraint is added, so that the dynamic range and the quantization precision required by the attenuator are reduced, and the hardware complexity is simplified.

Devices and techniques for loading contexts in a coarse-grained reconfigurable array processor are described herein. A system or apparatus may include context load circuitry operable to load context for a coarse-grained reconfigurable array processor, where the context load circuitry is configured to: (a) receive a kernel identifier; (b) access a first registry to obtain a context mask base address; (c) determine a context mask address from the context mask base address and the kernel identifier; (d) access a second registry to obtain a context state base address; (e) determine a context state address from the context state base address and the kernel identifier; (f) use a context mask at the context mask address to determine corresponding active context state; and (g) load the corresponding active context state into the coarse-grained reconfigurable array processor.

The application discloses a kind of wide narrow beam and pointing reconfigurable array antenna and its reconfiguration method, comprising: radiating element array, including first radiating element subarray, second radiating element subarray;Horizontal plane feed network is provided with two output ends, respectively connected to first radiating element subarray, second radiating element subarray in corresponding radiating element;Vertical plane phase shift network is provided with an input end and multiple output ends, and output end is connected to horizontal plane feed network input end and the remaining radiating element in second radiating element subarray;Horizontal plane feed network is driven by horizontal wave adjustment drive mechanism and is adjusted, and vertical plane phase shift network is driven by vertical wave adjustment drive mechanism and is adjusted;Three dimensions of horizontal beam width, horizontal beam pointing and vertical beam pointing are realized independently, continuously reconfigurable, so that a pair of antenna can be flexibly adapted to multiple coverage scenarios, greatly improve the degree of freedom of network planning and optimization, and overall structure is compact, simplifies, easy to control.

The application provides a reconfigurable computing architecture mapping method based on graph convolution and reinforcement learning, comprising the following steps: acquiring a data dependency graph and a coarse-grained reconfigurable array, and calculating a minimum start interval of the data dependency graph; preprocessing the data dependency graph according to the minimum start interval; simplifying a hardware model resource graph according to the structure of the coarse-grained reconfigurable array; taking a node set of the hardware model resource graph as an action space; adopting a reinforcement learning model based on a graph convolution network to map the preprocessed data dependency graph, so as to obtain a mapping result of a data dependency graph node on the hardware model resource graph; calculating a reward value of the mapping result; and when it is judged according to the reward value that the mapping result meets a successful mapping condition, outputting the mapping result. The application optimizes the layout and wiring of a loop on a reconfigurable computing array by using graph convolution and reinforcement learning, improves the parallelism of loop execution, and thus increases the mapping quality and reduces the execution time of image denoising.

The invention relates to the technical field of electromagnetic excitation, discloses an array electromagnetic excitation system capable of adaptively adjusting spatial magnetic field intensity, and aims to solve the problems of non-uniform field distribution, inflexible parameter regulation and control and weak scene adaptability of a traditional electromagnetic excitation system. According to the system, a technical system of'multi-parameter independent regulation and control-adaptive power matching-reconfigurable array collaborative optimization 'is constructed, a distributed intelligent control architecture of'DDS + FPGA + AI algorithms' is adopted, and independent adjustment of electromagnetic parameters of an excitation source is realized in combination with a frequency-band power amplification and dynamic impedance matching technology; a reconfigurable coil array driven by piezoelectricity is matched with a multi-physical field monitoring closed loop of a Hall sensor array and a temperature / stress sensor, and the distribution uniformity of an electromagnetic field is adjusted in combination with a field-structure collaborative optimization algorithm. According to the invention, the energy transmission efficiency and scene adaptability can be improved, and high-precision adjustment of electromagnetic excitation is realized.

The invention discloses a reconfigurable tensor calculation unit, which comprises a pipeline controller, a processor and a processor, wherein the pipeline controller is responsible for analyzing an instruction, configuring a calculation mode and scheduling a task; the matrix calculation module is composed of reconfigurable subarrays and is used for executing multi-precision matrix multiplication and addition operation; the matrix cache module comprises four types of caches; and the AXI bus access module is used for realizing efficient data interaction with an off-chip memory through a DMA (Direct Memory Access) controller. Firstly, a matrix base address, calculation precision, a mixed mode mark and a target dimension are configured through a register; and then the DMA carries the matrix data into a corresponding cache through an AXI bus. The cache carries out dynamic recombination on the data according to the current mode and then sends the data to the reconfigurable array for calculation. After calculation is completed, a result is recombined through the D cache and written back to the memory. By using the tensor accelerator, the defects of an existing tensor accelerator in the aspects of flexibility, energy efficiency and hardware resource utilization rate can be overcome. The method can be widely applied to the field of hardware accelerators.

A field-programmable analog array (FPAA) fabric includes a 6×6 matrix of configurable analog blocks (CABs). The implementation of programmable CABs eliminates the use of fixed analog subcircuits. A unique routing strategy is developed within the CAB units that supports both differential and single-ended mode circuit configurations. The bandwidth limitation due to the routing switches of each individual CAB unit is compensated for through the use of a switch-less routing network between CABs. Algorithms and methodologies facilitate rapid implementation of analog circuits on the FPAA. The proposed FPAA fabric provides high operating speeds as compared to existing FPAA topologies, while providing greater configuration in the CAB units as compared to switch-less FPAA. The FPAA core includes 498 programming switches and 14 global switchless interconnects, while occupying an area of 0.1 mm2 in a 65 nm CMOS process.

This invention discloses a reconfigurable array processing circuit for interpolation algorithms, relating to the field of circuit design. It includes a data buffer system module for receiving raw image pixel data and transmitting the raw image pixel data to a reconfigurable processing operator array module; a state controller module for acquiring a target interpolation algorithm and adjusting the configuration of the reconfigurable processing operator array module according to the target interpolation algorithm; the target interpolation algorithm includes nearest neighbor interpolation, bilinear interpolation, and bicubic interpolation; the reconfigurable processing operator array module, after adjustment by the state controller module, performs interpolation processing on the raw image based on the raw image pixel data to obtain the processed image. This invention can significantly improve processing efficiency and meet bandwidth requirements.

The application provides a user-centered joint optimization method and system of a cell-free MIMO system, and relates to the technical field of wireless communication. The method comprises the following steps: constructing a downlink of a UCCF millimeter wave mMIMO communication system, the mMIMO communication system comprising a plurality of randomly distributed access points AP and user equipment UE, each AP being equipped with a polarized reconfigurable array, and constructing a signal model; based on the signal model, constructing a corresponding channel model; and constructing an initial hybrid beamforming model; based on the channel model, optimizing the channel model with an optimal sum rate as a target; according to an optimal perturbation genetic algorithm, iteratively optimizing an AP-UE clustering matrix A, a polarization mask matrix B of all APs and the hybrid beamforming model to obtain a target joint optimization model. The application solves the problem that the performance of an existing cell-free large-scale MIMO system is limited in a dense user or dynamic network environment.

The invention belongs to the technical field of unmanned aerial vehicles, and discloses a reconfigurable array antenna device for an unmanned aerial vehicle, the reconfigurable array antenna device comprises the unmanned aerial vehicle and an antenna reflection panel assembly, an array arm assembly is arranged below the antenna reflection panel assembly, an abutting arm assembly is arranged at the top of the array arm assembly, and the array arm assembly is driven by the abutting arm assembly, so that the reconfigurable array antenna device is formed. The array arm assembly drives the antenna reflection panel assembly to form an array antenna structure used in an unfolded or folded mode, a locking arm assembly is arranged at the bottom of the abutting arm assembly, and the use state of the antenna reflection panel assembly is locked through the locking arm assembly. The array arm assembly is mounted on the top of the unmanned aerial vehicle in a quick-release mode through the mounting arm assembly, a locking toothed plate is pushed by a locking spring, so that the locking toothed plate abuts against a positioning toothed ring in a meshed mode, then locking of the position of a second movable arm on an array arm seat is achieved, and locking of the use state of the antenna reflection panel assembly is achieved.

The application provides a common excitation amplitude sparse reconfigurable array synthesis method and relates to information transmission and processing technology.The application comprises the following steps: 1) constructing a mathematical optimization model by using the radiation characteristic requirements and the nulling requirements of a beam to be synthesized, and solving the model by using the particularity of conjugate symmetric excitation and a continuous convex approximation algorithm; and 2) introducing a slack variable to help solve the feasible point by using a feasible point tracking algorithm, and overcoming the infeasible solution caused by the non-convex constraint.The application has the advantages that a sparse array can form multiple radiation direction patterns, and meet multiple different application scenarios; the number of array elements is reduced by designing the sparse array, so that the system cost is further reduced; the characteristic of conjugate symmetric excitation weight reduces the optimization variables, so that the application has the advantage on a large array; and the DRR constraint is added, so that the dynamic range and the quantization precision required by the attenuator are reduced, and the hardware complexity is simplified.

This disclosure proposes a three-dimensional coarse-grained reconfigurable array architecture system and its control method. The system includes multiple first arrays and multiple second arrays, wherein each first array includes multiple first computing units, multiple first storage units, and multiple first switches, and each second array includes multiple second computing units, multiple second storage units, and multiple second switches. The system arranges the first and second arrays in an interleaved stack manner and dynamically manages the enable and disable states of each unit through a configuration controller to execute the computational tasks of a neural network model. The technical solution of this disclosure can significantly improve data transmission efficiency, increase resource utilization flexibility, and achieve optimal configuration of hardware resources.

The application discloses a coarse-grained reconfigurable array and a hardware modeling generation method thereof, and belongs to the field of digital circuit design and processing technology. The coarse-grained reconfigurable array comprises a processing unit array of a reconfigurable array formed by M rows and N columns of processing units, a configuration memory for temporarily storing processing unit operation configuration information, a configuration bus and an input / output interface for connecting the configuration memory and the processing units. The modeling generation method comprises generating sub-module design parameters from top to bottom and generating hardware RTL level code from bottom to top by using an input top-level hardware design parameter. The coarse-grained reconfigurable array and the hardware modeling generation method can complete agile modeling and RTL level code generation of the coarse-grained reconfigurable array, realize target redirection of a driving compilation tool by designing a hardware description intermediate representation, and greatly improve the efficiency of hardware design and software stack development of a hardware accelerator.

A mapping approach (“PathSeeker”) for CGRAs analyzes mapping failures and performs local adjustments to a schedule to obtain a mapping. First, instead of backtracking or restarting the mapping as in previous mapping methods, PathSeeker analyzes the predecessor and successor nodes to find the reason behind the failed mapping. Second, PathSeeker explores local transformations for the predecessor and successor of the failed node to achieve a valid mapping. Finally, when local transformations do not yield a valid mapping, different PE positions of the other nodes in the time-slot of the failed node, the predecessor, and successor are iteratively explored, to find a valid mapping.

The application discloses a broadband circularly polarized scattering reconfigurable array antenna based on a varactor loading, which is composed of a plurality of scattering reconfigurable antenna units, and each scattering reconfigurable antenna unit comprises a resonant structure for radiating or receiving signals and a feeding and phase-shifting structure arranged on the lower surface of the resonant structure, wherein the feeding and phase-shifting structure comprises a broadband directional coupler and a reflective broadband phase shifter; when the scattering reconfigurable antenna unit is in a radiation working state, the broadband directional coupler radiates energy to the resonant structure; when the scattering reconfigurable antenna unit is in a scattering working state, the broadband directional coupler transmits energy to the reflective broadband phase shifter, and the reflective broadband phase shifter adjusts the energy of secondary radiation according to a bias voltage applied to an internal varactor. The array antenna provided by the application has a wide working frequency band, and can ensure the radiation performance while realizing the reconfiguration of scattering characteristics.

The invention relates to the technical field of data cleaning, and further relates to an FPGA (Field Programmable Gate Array)-based streaming data cleaning accelerator, which comprises a coarse-grained reconfigurable array cleaning assembly line which is arranged in a programmable logic area of an FPGA chip and comprises a plurality of processing units; an arithmetic logic operation core, a local register file, a crossbar switch router and an instruction buffer area are arranged in each processing unit; the configuration controller is used for issuing a function configuration instruction to each processing unit in the coarseness reconfigurable array cleaning assembly line; a quantitative perception streaming neighbor interpolation engine; the interpolation value generation module is used for generating an interpolation value according to the finely arranged neighbor set; and the data interface is used for receiving the original data stream to be cleaned and outputting the cleaned data record. The problems that a traditional data cleaning scheme is insufficient in throughput and a K neighbor interpolation method is too high in calculation complexity are effectively solved.

A method for automatically placing and routing processing elements (PEs), where each PE has a limited connectivity to its neighbors. The method may obtain placement primitive (PP) location window information, the location window information defining possible locations of a group of PPs within a coarse-grained reconfigurable array (CGRA). The method may obtain hardware constraints regarding the array of PEs, the hardware constraints comprise local connectivity constraints and remote connectivity constraints. The method may receive a computation graph (CG) that represents mathematical expressions to be calculated by the array of PEs. The method may determine a location of the PEs of the array of PEs based on the CG, the PP location window information, and hardware constraints.

This invention provides a method and system for constructing a note-based cache architecture based on a spatially reconfigurable array, comprising: employing column address remapping for tasks with arbitrary granularity; partitioning and storing multiple arrays with different memory access steps, and using stream and array binding for concurrent access of multiple arrays; using static configuration to reduce configuration frequency, and using configuration parameters for address translation. This invention achieves zero waste of on-chip memory and conflict-free interaction between the computing array, DDR, and on-chip memory through a lightweight, scalable, and parameterized column address remapping mechanism. Based on the characteristics of parallel memory access of multiple arrays with varying step sizes, this invention organizes the memory access process of multiple arrays in a stream manner, and achieves concurrent, conflict-free access of multiple arrays through on-chip partitioning and the conversion between logical and physical address spaces.