39 results about "Arithmetic operators" patented technology

An apparatus and method for unifying multiple radio frequency identifications (RFIDs) are provided. The apparatus includes: a data arithmetic operator collecting RFIDs, storing the collected RFIDs, and repeatedly performing the collection and storage when a time out event occurs; a hash arithmetic operator concatenating the RFIDs, hashing the concatenated RFIDs, and outputting a hashed single value; a random number generator generating a random number used as an encryption factor to public-key-encrypt the single value; an RFID tag processor controlling locking / unlocking of the RFID tags; a public key arithmetic operator public-key-encrypting the single value using a predetermined public key and the random number as encryption factors and outputting a cipher text; and a radio frequency communicator converting the cipher text into a radio signal and sending the radio signal to a radio section. Information transmitted to a radio section is a cipher text obtained by public-key-encrypting the single value. Therefore, the number of the RFID tags belonging to a user is not exposed to an eavesdropper, thereby protecting user's privacy.

The invention discloses an image processing method for establishing a mathematical model based on down sampling and interpolation, relates to an image processing method, and solves the prior problem that the image maintains a small amount of information after the down sampling. The invention adopts the steps that firstly, an image FO to be down-sampled is input; next, an interpolation mathematical model, namely, FH is equal to CI (U<H>F<L>U<V>) is established, and then an interpolation method is selected, a predictive model is determined, the arithmetic operator CI of the interpolation method is determined, and simultaneously UH and UV are determined according to the size of the image FO; and then a down sampling mathematical model, namely, FL is equal to DH (CF) DV is established; a predictive model with uniform image element of the interpolation and the down sampling is established, CF is obtained through the identity of the arithmetic operator the CI of the interpolation and the arithmetic operator the CF of the down sampling, and simultaneously the DH and the DV are obtained; finally, the down sampling processing to the image FO is performed through the obtained the FL being equal to the DH (CF) DV; the down sampling is obtained. The invention can be applied to the low code rate compression of images and videos, therefore reducing the amount of calculation of compression algorithm, quickening the processing speed and reducing the time delay, and also obviously improving the quality of restored images.

The invention provides systems and methods for converting high level source code into an arithmetic circuit which represents the functionality expressed in the source code. The invention comprises a translation / interpretation component for performing this conversion. In a preferred embodiment, the source code is a smart contract such as those used in relation to a blockchain platform. The invention could be used in relation to the Bitcoin network, for example. A method in accordance with an embodiment comprises the steps of: processing a portion of high level source code (e.g. a smart contract) to generate an arithmetic circuit. The arithmetic circuit comprises one or more arithmetic gates arranged to represent at least some of the functionality expressed in the source code. The processing involves evaluating one or more constants provided in the source code to produce one or more expressions that include Boolean and / or arithmetic operators. The arithmetic circuit comprises n-bit wires connected to arithmetic gates; it can be used to provide a hardware and / or software circuit. The arithmetic circuit can be used to generate a quadratic program which can be executed upon a processor.

The invention discloses a round sub-pixel detection algorithm based on point Hough transform and Legendre moments, and provides a method for quickly positioning a circular mark in polymerase chain reaction (PCR) visual detection. The method comprises the following steps of: performing edge detection and Hough transform to acquire a circular mark pixel-level reference value by using a Canny arithmetic operator; filtering off noise points in edge points by using the circular mark pixel-level reference value; analyzing a sub-pixel edge positioning method based on Legendre orthogonal moments, and an error; evaluating sub-pixels of the edge points from which the noise points are filtered off by using the Legendre orthogonal moments and an error method; and finally fitting the edge points by a fast least square method to acquire accurate circle center positioning parameter and radius parameter of a round. By the method, the characteristic of high speed of point Hough transform operation is kept; and the method has the characteristics of high positioning accuracy, high noise resistance, accuracy, high speed and robustness and meets the requirements of high accuracy and real-time property in the PCB visual detection.

A display apparatus includes: a display panel configured to display an image frame; an arithmetic operator configured to divide the image frame into blocks, calculate a pixel gradation value of the pixel blocks, and accumulate the calculated pixel gradation values; and a compensator configured to locally reduce a luminance of a corresponding pixel block, of which a respective accumulated pixel gradation value exceeds a threshold value of among the plurality of pixel blocks, and to compensate for a luminance difference between the corresponding pixel block, for which the luminance has been reduced, and surrounding pixel blocks. Accordingly, it is possible to effectively remove an afterimage.

Provided is a magnetic bearing device which allows easy initial adjustment and allows optimal bearing control to be performed by a simple algorithm without increasing a memory capacity of a controller. A pair of square multipliers and an adder acquire respective steady-state current values of a pair of electromagnets which attract a rotor shaft of a magnetic bearing not shown in opposite radial directions, square the respective steady-state current values, and add up the respective squared steady-state current values. Then, to optimally change respective currents in the electromagnets in accordance with a mounting posture of the magnetic bearing, a correction coefficient arithmetic operator calculates a correction gain instruction value acting on the electromagnets from the steady-state current values squared / added up. Then, a gain instruction value obtained by adding the correction gain instruction value to a fundamental gain of a control circuit for the electromagnets is input to a gain amplifier. The gain amplifier generates a corrected current instruction value on the basis of the gain instruction value and optimally controls the magnetic bearing.

The invention discloses a method for implementing an inter-frame predictor for a video encoder. The method comprises the following steps of: mapping each functional block of the inter-frame predictor of the video encoder which is described by a high-level program language algorithm into hardware logic description consisting of arithmetic operator units; and generating a hardware integrated circuit of the inter-frame predictor by the hardware logic description consisting of the arithmetic operator units. By the method, the speed for implementing the integrated circuit of the inter-frame predictor can be increased. The invention also discloses the inter-frame predictor acquired by the method.

Embodiments of the invention propose a formula analysis based complicated index set calculation method and system. The calculation method comprises: determining parameters of a data standardization model, wherein the parameters include a dimension, a measurement value and a derivative value of data in a data set; determining basic data in the data set; determining non-basic data in the data set and representing the non-basic data by arithmetic of at least one or more sub-data; representing each non-basic datum as a tree structure, wherein end points of the tree structure are arithmetic operators for generating the non-basic data, and branches of the tree structure are sub-data for generating the non-basic data; sorting formulae corresponding to all the generated non-basic data to ensure that formulae corresponding to the sub-data cited by the non-basic data are arranged before formulae corresponding to the non-basic data; then generating executable statements according to the sorted formulae; and importing the basic data and then executing the executable statements in sequence.

The invention discloses a one-bit multi-valued digital multiplier (MOS transistor drain control transmission type multi-system and decimal bit weight multiplier) composed of MOS transistors. The one-bit multi-valued digital multiplier is composed of multiple-valued multiplication modules in different forms. The multi-valued multiplication module is provided with a 0 multiplying module, a 1 multiplying module, a 2 multiplying module,..., and an N multiplying module; the module is formed by combining and connecting arithmetic units which are connected in different modes. The unit is formed by permutation and combination of units according to the claim 3 of the patent application 20171111971. X 'a multi-system arithmetic operator of quantitative logic assignment fractal integrated unit circuit '. Drain electrodes of MOS tubes of all units are connected together to serve as a control end and are connected with a numerical value end of one set of bit weight input, grid electrodes of all theunits in the module serve as another set of bit weight data input end, and the formed module is called a leakage control multiplication operation module. The module outputs are divided into two groups, one group is standard output, and the carry systems of the selected circuits are different.

An analog to digital converter is provided. The analog to digital converter includes: an arithmetic operator combining an analog input signal with a feedback signal; a loop filter filtering an output signal of the arithmetic operator; a quantizer quantizing an output signal of the loop filter to output a digital signal; and a feedback converting the digital signal to output a feedback signal, in which the quantizer includes: a plurality of VCOs each receiving a positive output signal and a negative output signal of the loop filter and outputting VCO signals; a plurality of samplers receiving the VCO signals output from the plurality of VCOs, respectively and outputting sampled signals; and a phase detector detecting a phase difference in the sampled signals output from the plurality of samplers, respectively, to detect a phase difference in two VCO signals output from the plurality of VCOs, respectively.