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829 results about "Matrix element" patented technology

Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system

InactiveUS7002591B1Efficient implementationIncrease in texture mapping hardware complexityCathode-ray tube indicators3D-image renderingPattern recognitionProcessing
A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics pipeline renders and prepares images for display at least in part in response to polygon vertex attribute data and texel color data stored as a texture images in an associated memory. An efficient texturing pipeline arrangement achieves a relatively low chip-footprint by utilizing a single texture coordinate / data processing unit that interleaves the processing of logical direct and indirect texture coordinate data and a texture lookup data feedback path for “recirculating” indirect texture lookup data retrieved from a single texture retrieval unit back to the texture coordinate / data processing unit. Versatile indirect texture referencing is achieved by using the same texture coordinate / data processing unit to transform the recirculated texture lookup data into offsets that may be added to the texture coordinates of a direct texture lookup. A generalized indirect texture API function is provided that supports defining at least four indirect texture referencing operations and allows for selectively associating one of at least eight different texture images with each indirect texture defined. Retrieved indirect texture lookup data is processed as multi-bit binary data triplets of three, four, five, or eight bits. The data triplets are multiplied by a 3×2 texture coordinate offset matrix before being optionally combined with regular non-indirect coordinate data or coordinate data from a previous cycle / stage of processing. Values of the offset matrix elements are variable and may be dynamically defined for each cycle / stage using selected constants. Two additional variable matrix configurations are also defined containing element values obtained from current direct texture coordinates. Circuitry for optionally biasing and scaling retrieved texture data is also provided.
Owner:NINTENDO CO LTD

Method for optimizing space between broad band phased array elements and measuring frequency and direction of frequency domain multiple targets

InactiveCN101349742AImproved DF resolutionSolve the direction finding ambiguity problemRadio wave finder detailsRadio wave direction/deviation determination systemsFrequency measurementsArray element
The invention discloses a method for matrix element distance optimization and frequency domain multi target frequency and direction measurement of wideband phased arrays, for realizing the direction measurement of multiple targets having narrow band coherence and irrelevance of a wideband receiver, resolving the contradiction between the direction measurement resolution and unambiguous direction measurement of sparse array, and realizing more accurate target detection under a certain channel error. The method comprises the steps of: first using uneven array, using genetic algorism to optimize the distance of array elements to satisfy the higher direction measurement resolution and high direction measurement accuracy of spatial unambiguous condition; based on the optimized array, realizing the frequency domain multi target frequency and direction measurement algorism as a DOA evaluation algorism which processes frequency domain accumulation, frequency domain check and frequency measurement for the data of each array element channel and realizes frequency automatic match. The algorism adopts array optimization, frequency domain peak snapshot frequency and direction measurement joint algorism. The invention can be applied for the multi narrow band target accurate frequency and direction measurement of wideband receivers in the airborne and satellite-borne electronic reconnaissance.
Owner:XIDIAN UNIV

Matrix fully homomorphic encryption method

InactiveCN103259643AInput protectionSatisfy the requirement of full homomorphismSecuring communicationComputer hardwareCiphertext
The invention discloses a matrix fully homomorphic encryption method. The matrix fully homomorphic encryption method comprises an initialization module, an encryption module, a decryption module and a matrix fully homomorphic module. The initialization module is used for generating secret keys needed by encryption and decryption according to dimensions of matrices to be encrypted, encryption types and ranges of matrix element values. The encryption module is used for utilizing encryption algorithms and the secret keys to conduct encryption on plaintext matrices and outputting ciphertext matrices according to the given plaintext matrices. The decryption module is used for utilizing the secret keys and decryption algorithms to conduct decryption on ciphertext matrices and outputting the plaintext matrices according to the given ciphertext matrices. According to the matrix fully homomorphic module, additive operation and multiplying operation of the matrices meet homomorphic properties of the matrices, output generated by the additive operation and the multiplying operation of the matrices still meets the homomorphic properties, namely, fully homomorphic properties of the matrices are met. The matrix fully homomorphic encryption method has the advantages of meeting safety requirements, meeting fully homomorphic requirements of the matrices and remarkably increasing the operating rate of the ciphertext matrices.
Owner:SUZHOU UNIV

Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics pipeline renders and prepares images for display at least in part in response to polygon vertex attribute data and texel color data stored as a texture images in an associated memory. An efficient texturing pipeline arrangement achieves a relatively low chip-footprint by utilizing a single texture coordinate / data processing unit that interleaves the processing of logical direct and indirect texture coordinate data and a texture lookup data feedback path for “recirculating” indirect texture lookup data retrieved from a single texture retrieval unit back to the texture coordinate / data processing unit. Versatile indirect texture referencing is achieved by using the same texture coordinate / data processing unit to transform the recirculated texture lookup data into offsets that may be added to the texture coordinates of a direct texture lookup. A generalized indirect texture API function is provided that supports defining at least four indirect texture referencing operations and allows for selectively associating one of at least eight different texture images with each indirect texture defined. Retrieved indirect texture lookup data is processed as multi-bit binary data triplets of three, four, five, or eight bits. The data triplets are multiplied by a 3×2 texture coordinate offset matrix before being optionally combined with regular non-indirect coordinate data or coordinate data from a previous cycle / stage of processing. Values of the offset matrix elements are variable and may be dynamically defined for each cycle / stage using selected constants. Two additional variable matrix configurations are also defined containing element values obtained from current direct texture coordinates. Circuitry for optionally biasing and scaling retrieved texture data is also provided.
Owner:NINTENDO CO LTD

Fast decoupled flow calculation method for power systems

The invention discloses a fast decoupled flow calculation method for power systems, which comprises the following steps of: inputting original data and initializing voltage; forming an admittance matrix; forming correction equation coefficient matrixes B' and B'' and performing factor table decomposition; performing P-theta iteration, and correcting a voltage phase angle; performing Q-V iteration, and correcting voltage amplitude; judging whether the iteration is converged; and calculating node power and branch power. The method requires that the P-theta iteration and the Q-V iteration are all converged in the same iteration and the iteration process is finished, so that the algorithm frame is simpler, and the flow is clearer. The sparse matrix technology is not adopted, so the matrix elements are convenient to access and calculate, and the programming is simple; the correction equation coefficient matrixes are stored according to n order, number change of nodes is avoided, and the programming difficulty is reduced; and the calculation amount is reduced through reasonable logic judgment, the calculation speed is obviously improved and the requirement of scientific research can be completely met. The fast decoupled flow calculation method also can process power systems with a plurality of balance nodes.
Owner:DALIAN MARITIME UNIVERSITY

Inverse operation method for lower triangle complex matrix with any order

The invention relates to an inverse operation method for a lower triangle complex matrix with any order. The inverse operation method comprises the following steps that (1) a reciprocal obtaining unit is set, and is used for carrying out reciprocal obtaining operation on a diagonal element of an N-order matrix L, and outputting a matrix obtained after reciprocal obtaining operation is accomplished; (2) a multiplication and accumulation unit is set and is used for receiving the matrix obtained after reciprocal obtaining operation is accomplished, and multiplication and accumulation operation is carried out on the first element to the (i-1)th element in the ith row in the matrix; (3) a reciprocal multiplication obtaining unit is set and is used for receiving the accumulation result corresponding to the elements in the ith row of the matrix, reciprocal obtaining operation is carried out on the accumulation result, and then the accumulation result processed through reciprocal obtaining operation is multiplied by a diagonal element in the ith row so that a matrix element of the ith row of an inverse matrix L-1 can be obtained. In the whole process, a plurality of multiplication and accumulation units are used for carrying out parallel calculation. The inverse operation method for the lower triangle complex matrix with any order has the advantages that the inverse operation of the lower triangle complex matrix with any order can be achieved, and restriction caused by the number of operation units does not exist; only the design of a multiply-accumulator with one plural adder and one plural multiplier is adopted, hardware resources are saved, and operation efficiency is ensured through an effective parallelization mode.
Owner:NANJING UNIV
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