54 results about "Quantum logic" patented technology

A computer program product for use in conjunction with a computer system, the computer program product comprising a computer readable storage medium and a computer program mechanism embedded therein. The computer program mechanism comprises a quantum computing integrated development environment (QC-IDE) module and a compiler module. The QC-IDE module is used to design a quantum logic for a plurality of qubits. The QC-IDE module includes instructions for generating a time resolved set of operators. The compiler module includes instructions for compiling the time resolved set of operators into a set of quantum machine language instructions.

In one embodiment, the disclosure relates to a method and apparatus for controlling the energy state of a qubit by bringing the qubit into and out of resonance by coupling the qubit to a flux quantum logic gate. The qubit can be in resonance with a pump signal, with another qubit or with some quantum logic gate. In another embodiment, the disclosure relates to a method for controlling a qubit with RSFQ logic or through the interface between RSFQ and the qubit.

In one embodiment, the disclosure relates to a method and apparatus for controlling the energy state of a qubit by bringing the qubit into and out of resonance by coupling the qubit to a flux quantum logic gate. The qubit can be in resonance with a pump signal, with another qubit or with some quantum logic gate. In another embodiment, the disclosure relates to a method for controlling a qubit with RSFQ logic or through the interface between RSFQ and the qubit.

The invention discloses a low-complexity quantum circuit simulation system, and belongs to the field of quantum computing. The low-complexity quantum circuit simulation system overcomes the technicalproblems in the prior art that the quantum circuit simulation storage space is too large and the calculation time is too long. The system comprises an input module, a storage module and an output module, the storage process of the storage module for data is as follows: (1) a mathematical model is established to represent the operation of a quantum state and quantum logic gate; (2) quantum bits aregrouped and the serial numbers of the quantum bits are rearranged; (3) degree reduction is conducted on a total operation matrix U0, and an output state is calculated. According to the system, a matrix element of a quantum state vector is directly operated by using an connotative inherent law of a quantum logic gate, at the same time, the method has expandability, in the future, a supercomputer can be used to simulate a quantum computer with more bits.

A superconducting logic cell includes at least one quantum phase-slip junction (QPSJ) for receiving at least one input and responsively providing at least one output, each QPSJ being configured such that when an input voltage of an input voltage pulse exceeds a critical value, a quantized charge of a Cooper electron pair tunnels across said QPSJ as an output, when the input voltage is less than the critical value, no quantized charge of the Cooper electron pair tunnels across said QPSJ as the output, where the presence and absence of the quantized charge in the form of a constant area current pulse in the output form two logic states, and the at least one QPSJ is biased with a bias voltage. The superconducting logic cell further includes at least one Josephson junction (JJ) coupled with the at least one QPSJ to perform one or more logic operations.

In a general aspect, randomized compiling techniques for quantum computing are described. In some aspects, an initial quantum-logic gate sequence is received. A modified quantum-logic gate sequence is generated by applying virtual random gates to the initial quantum-logic gate sequence, such that the initial quantum-logic gate sequence is logically equivalent to the modified quantum-logic gate sequence. The modified quantum-logic gate sequence can be provided to a quantum information processor for execution.

A quantum logic gate for qubits, suitable for receiving as inputs at least two polarization-encoded qubits, includes at least one partially polarizing beam splitter (PPBS), the beam splitter comprising a first waveguide and a second waveguide which are constructed in integrated optics, the first and second waveguides having a refractive index contrast of between 0.1% and 6% and a birefringence of between 10−6 and 6*10−5.

A system, method and apparatus for executing a bioinformatics analysis on genetic sequence data includes a quantum computing device formed of a set of hardwired quantum logic circuits interconnected by a plurality of superconducting connections to process information represented as a quantum state that is configured as a set of one or more qubits. The hardwired quantum logic circuits may be arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired quantum logic circuits to perform one or more steps in the bioinformatics analysis on the reads of genomic data. Each subset of the hardwired quantum logic circuits may be formed in a wired configuration to perform the one or more steps in the bioinformatics analysis.

A method for quantum computing with a quantum system comprising a first energy level, a second energy level, and a third energy level. The first energy level and said second energy level are capable of being degenerate with respect to each other. In the method a signal is applied to the quantum system. The signal has an alternating amplitude at an associated frequency such that (i) the frequency of the signal correlates with an energy level separation between the first energy level and the third energy level or (ii) the frequency of the signal correlates with an energy level separation between the second energy level and the third energy level. The signal induces an oscillation in the state of the quantum system between the first energy level and the second energy level.

A superconducting logic cell includes at least one quantum phase-slip junction (QPSJ) for receiving at least one input and responsively providing at least one output, each QPSJ being configured such that when an input voltage of an input voltage pulse exceeds a critical value, a quantized charge of a Cooper electron pair tunnels across said QPSJ as an output, when the input voltage is less than the critical value, no quantized charge of the Cooper electron pair tunnels across said QPSJ as the output, where the presence and absence of the quantized charge in the form of a constant area current pulse in the output form two logic states, and the at least one QPSJ is biased with a bias voltage. The superconducting logic cell further includes at least one Josephson junction (JJ) coupled with the at least one QPSJ to perform one or more logic operations.

The invention discloses a processing method and device of a quantum circuit, a storage medium and an electronic device. The method comprises the following steps: when the operation of the double quantum logic gates in the quantum circuit to be converted is controlled by a single quantum logic gate, the control bits of the double quantum logic gates are stored in a preset variable; a double quantumlogic gate whose control bit number is greater than or equal to 1 in a preset variable is decomposed to obtain a quantum logic gate whose control bit number is less than 1; a target quantum circuit is output, wherein the target quantum circuit includes a quantum logic gate having a control number of bits less than 1, and the target quantum circuit supports a quantum chip instruction set. The invention solves the technical problem that the two-bit logic gate of the quantum circuit cannot be converted in the related art.

The invention discloses a data structure representing a quantum program, the data structure includes: quantum circuit class, quantum program class, Node Class, Quantum Logic Gate Node Class, Control node class, Determine Expression Node Class, the quantum circuit class is used for storing a set of quantum logic gates using a container, the quantum program class is used for storing a set of node classes using a container, The node class is a quantum circuit class, a quantum program class, a quantum logic gate node class, and a parent class of the control node class. The quantum logic gate nodeclass is used for storing the qubits of the operation of the quantum logic gate, the unitary matrix corresponding to the quantum logic gate, and the judgment expression node class is used for storingthe related information of the judgment expression. The invention has the advantages that the execution sequence of the recordable quantum instructions, the reusable quantum circuit, the condition judgment expression input by the developer can be recorded by the control node type, and finally the executable quantum circuit of the quantum program can be judged according to the final result.

The invention discloses a calibration method belonging to the field of quantum computing, in particular to a single quantum logic gate operation. The calibration method comprises the following steps:determining that the modulation amplitude signal is a product of an adjustable proportion constant and a first digital signal; determining a plurality of pulse modulated signals having different modulated amplitude signals by changing the adjustable proportional constant; obtaining a distribution probability value corresponding one-to-one to each of the pulse modulated signals having different modulated amplitude signals; Taking the adjustable proportional constant as an independent variable and the distribution probability value as a dependent variable, performing wave oscillation exponentialattenuation fitting, and obtaining a wave oscillation period according to the fitting result, and recording the period as a standard period; the target quantum logic gate operation to be calibrated is determined, and the value of the adjustable proportion constant of the pulse modulation signal corresponding to the target quantum logic gate operation is determined according to the rotation angleand the standard period of the target quantum logic gate operation. The invention can realize the calibration of the operation of the single quantum logic gate.

The invention discloses a construction method of a quantum logic circuit for aiming at multiplication operation in an encryption technology field. The method comprises the following steps of constructing a base module, namely using a basic control Not gate and an exchange gate in the quantum logic circuit as a construction gate base of a basic circuit, and packaging the constructed basic circuit for forming a U device, thereby realizing add operation and multiplication operation; and constructing a high-grade circuit module. According to the construction method, a reversible logical design is utilized, and power consumption and behavior attribute of an electromagnetic field cannot be obtained through a traditional manner, thereby effectively preventing side channel attacks, and greatly reducing possibility of illegal crack. Better encryption effect of encryption technology is realized. Reversibility of the circuit can realize an encryption effect of 2n logic synthesis.

The invention relates to a designing method for quantum image edge detection based on a Sobel operator, which establishes 9 quantum image sets by using a basic quantum logic gate, designs a quantum black box to calculate an image gradient value, classifies the gradient by a threshold operation, and finally obtains the edge of the quantum image. The complexity of the quantum circuit for the edge detection of the entire quantum image is at most, which the quantum image edge detection of the classic Sobel operator cannot achieve. The invention has great significance to the improvement and popularization of the application of the quantum computation theory.

The invention belongs to the technical field of quantum chip testing, and particularly discloses a method for generating quantum bit control signals. The method includes the steps that a first tag code and a first standard signal of each basic quantum logic gate in a corresponding reference quantum gate set sent by an upper computer are received; the first standard signals are stored, and first address codes for identifying the storage positions of the first standard signals are obtained; a target tag code and a target time code of each basic quantum logic gate in a corresponding target quantum program sent by the upper computer are received; first standard signals corresponding to the basic quantum logic gates in the target quantum program are obtained according to the target tag codes and the target time codes to serve as to-be-processed signals, the to-be-processed signals are processed, and the quantum bit control signals are obtained. The multi-bit quantum bit testing requirementscan be met, and the quantum bit control signal requirements needed by multi-bit quantum bit testing are provided.

A system, method and apparatus for executing a bioinformatics analysis on genetic sequence data includes a quantum computing device formed of a set of hardwired quantum logic circuits interconnected by a plurality of superconducting connections to process information represented as a quantum state that is configured as a set of one or more qubits. The hardwired quantum logic circuits may be arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired quantum logic circuits to perform one or more steps in the bioinformatics analysis on the reads of genomic data. Each subset of the hardwired quantum logic circuits may be formed in a wired configuration to perform the one or more steps in the bioinformatics analysis.

The invention discloses a single-amplitude quantum computing simulation method. The method comprises the following steps of for each computing node of a distributed cluster, obtaining a target quantumprogram; constructing an undirected graph corresponding to the target quantum program; wherein the vertex of the undirected graph represents the quantum state of the operated quantum bit before or after the quantum logic gate is operated, and one edge of the undirected graph corresponds to one tensor; obtaining a quantum state corresponding to a to-be-measured target single amplitude, and calculating sub-amplitudes of the quantum state based on the quantum state and the undirected graph in cooperation with the GPU corresponding to the calculation node; wherein the sub-amplitudes are amplitudes corresponding to the undirected graph; and returning the sub-amplitudes to a main node of the distributed cluster so that the main node reduces each sub-amplitude to obtain the amplitude of the quantum state as a target single amplitude. The method is advantaged in that quantum computation simulation involving 50 or more quantum bits can be realized.

A quantum logic gate utilizes an inter-polarization (dipole-dipole) interaction between excitons having polarization in semiconductor quantum well structures, or a spin exchange interaction between spin polarized excitons in the semiconductor quantum well structures. Problems associated with conventional semiconductor quantum well structures are solved in that a phase relaxation time is very short because of using inter-subband electrons, and that there is no usable ultrashort optical pulse laser technology because a subband transition wavelength is in a far-infrared region and hence ultra fast control is impossible.

In a general aspect, randomized compiling techniques for quantum computing are described. In some aspects, an initial quantum-logic gate sequence is received. A modified quantum-logic gate sequence is generated by applying virtual random gates to the initial quantum-logic gate sequence, such that the initial quantum-logic gate sequence is logically equivalent to the modified quantum-logic gate sequence. The modified quantum-logic gate sequence can be provided to a quantum information processor for execution.

Systems and methods for optimized testing of partially symmetric quantum-logic circuits. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to organize the circuit's inputs into two or more mutually exclusive blocks of inputs. The system computes a wreath product of a set of groups associated with the blocks in order to generate an invariance group that contains one or more invariant permutations of the circuit's inputs. These invariant permutations can be used to reduce the number of tests required to fully verify the circuit for all possible input vectors. Once one specific input vector has been verified, there is no need to test other vectors that can be generated by performing any one of the invariant permutations upon the previously verified vector.

This invention concerns a method to switch on and off the exchange interaction J between electron spins bound to donor atoms. The electron spins have the role of ‘qubits’ to carry quantum information, and the exchange interaction J has the role of mediator for two-qubit quantum logic operations. The invention aims at exploiting the existence of a further magnetic interaction, the hyperfine interaction A, between each electron spin and the nuclear spin of the donor atom (301, 302) that binds the electron. The hyperfine interaction A, together with the ability to read out (504) and control the state of the nuclear spins, is used to suppress the effect of the exchange interaction J at all times, except while a quantum logic operation is being performed. In this way, the result of the quantum logic operation is not distorted after the operation has taken place. In a further aspect, the invention concerns an electronic device where the method can be practically implemented, and a large scale device made up of many of the devices.

A method for preparing a tunneling diode of quantum logic component includes applying gas phase epitaxial process to grow single crystal silicon (SCS) film and gas phase deposition process to grow silicon quantum dot film, using semiconductor quantum conveying means to simulate tunneling current character of tunneling diode component for making further regulation on folding character of tunneling current, growing p type of SCS film on heavy doped p type of single crystal silicon substrate first then growing n type of silicon quantum dot film on formed p type of film by gas phase epitaxial unit.

The invention belongs to the field of quantum computing, and particularly discloses an MPI multi-process-based single quantum logic gate implementation method, which comprises the following steps that: configuring N quantum bits, wherein the number of each quantum bit is bit n, the N is a positive integer, and the n is greater than or equal to 0 and less than or equal to N-1; determining quantum states and subscript values of the quantum states, the total number of the quantum states being 2N, and the subscript values being decimal values corresponding to the quantum states; initializing the quantum states; configuring 2M MPI communication-based processes, and sequentially and uniformly storing all the quantum states to the processes according to the subscript values, wherein M is an integer greater than or equal to 1, and N is greater than or equal to M + 1; and performing operation of the single quantum logic gate according to the bit of the quantum bit to be acted by the single quantum logic gate and the plurality of processes based on the MPI. According to the invention, the calculation capability and calculation efficiency of quantum calculation based on the single quantum logic gate can be improved.

A quantum logic gate utilizes an inter-polarization (dipole-dipole) interaction between excitons having polarization in semiconductor quantum well structures, or a spin exchange interaction between spin polarized excitons in the semiconductor quantum well structures. Problems associated with conventional semiconductor quantum well structures are solved in that a phase relaxation time is very short because of using inter-subband electrons, and that there is no usable ultrashort optical pulse laser technology because a subband transition wavelength is in a far-infrared region and hence ultra fast control is impossible.