192 results about "Quantum error correction" patented technology

The invention relates to a transdermal analyte monitoring system comprising a medium adapted to interface with a biological membrane and to receive an analyte from the biological membrane and an electrode assembly comprising a plurality of electrodes, wherein the medium is adapted to react continuously with the analyte, an electrical signal is detected by the electrode assembly, and the electrical signal correlates to an analyte value. The analyte value may be the flux of the analyte through the biological membrane or the concentration of the analyte in a body fluid of a subject. The medium may comprise a vinyl acetate based hydrogel, an agarose based hydrogel, or a polyethylene glycol diacrylate (PEG-DA) based hydrogel, for example. The surface region of the electrode may comprise pure platinum. The system may include an interference filter located between the biological membrane and the electrode assembly for reducing interference in the system. The system may comprise a processor programmed to implement an error correction method that corrects for sensor drift.

Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. Predefined gears correspond to different predefined ECC schemes. Based on an observed bit error rate, a gear from a set of predefined gears is selected for use for a particular region of memory. Each gear of the set of predefined gears includes a lower-latency ECC decode option and one or more higher-latency ECC decode options.

This invention concerns quantum error correction, that is the correction of errors in the transport and processing of qubits, by use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site. The temporal process comprises the following steps: Creating a logical qubit in a section of the array by initialising an equal plurality of physical data and ancilla qubits at respective sites of the first and second lines within the section. Clocking each physical qubit site in the section at the same time. Permitting the physical data and ancilla qubits to move to an adjacent site in a clock cycle, provided that no site may contain more than one physical qubit at any time. Controlling the sites to achieve movement of ancilla qubits in the array to bring pairs of the ancilla qubits to respective first and second physical gate sites of logic function gates over the course of a number of clock cycles. Permitting logic operations to be performed at logic function gates which have both of their gate sites occupied by a physical ancilla qubit. Controlling the gate sites of the logic function gate to achieve the logic operation. Controlling the sites to achieve movement of the qubits in the array to bring pairs of all the data and ancilla qubits to respective logic function gates over the course of a number of clock cycles. Controlling the gate sites of the logic function gate to achieve the logic operation between each pair of data and ancilla qubits. Controlling the sites to achieve movement of the qubits in the array to bring all the data and ancilla qubits to respective sites where they can be read out. And, Using the values of the ancilla qubits read out to correct errors arising in the data qubits they have been gated with.

A non-volatile memory controller for a solid state drive includes a soft-decision LDPC decoder. The soft-decision LDPC decoder includes a probability generation module. A processor reads collected statistics collated from decoded frames and tunes the performance of the soft-decision LDPC decoder performance. Additional parameters may also be taken into account, such as the scramble seed and the type of non-volatile memory. An asymmetry in errors may also be detected and provided to a hard-decision LDPC decoder to adjust its performance.

The invention provides a method for correcting error-prone words in voice interaction. The method comprises the steps of context recognition, automatic error correction based on semantic restriction, and artificial error correction based on semantic feedback. Through voice interaction with users and perception and recognition of the context of a topic, automatic error correction of an entity with a specific meaning can be achieved by using the named entity recognition technology within the limited semantic range, additional semantics can be obtained through artificial feedback so as to conduct error correction, and higher input efficiency and more convenient wrong word correction than existing voice recognition software are realized.

In a quantum key distributing method of the present invention, a communication apparatus on a reception side performs error correction using parity check matrixes for an LDPC code that have an extremely high error correction ability. In the quantum key distributing method of the present invention, a cyclic code syndrome generated by a communication apparatus on a transmission side and an estimated cyclic code syndrome generated based on an estimated word after error correction are compared to perform error detection for the estimated word.

An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.

The invention provides a method and a system for query error correction. The method includes: converting an query sentence into a character sequence, and judging whether the length of the character sequence is larger than a preset threshold value delta or not; simultaneously performing forward and reverse error correction to the character sequence with the length larger than delta until the number of characters under overlap processing reaches a threshold value M, and obtaining forward and reverse candidate sentence item set; and splicing candidate sentences where rear M characters in the forward candidate sentence item set are identical with front M characters in the reverse candidate sentence item set, spliced candidate sentence items form an error correction candidate item set. The method supports query sentences with Chinese and English characters mixed and allows for parallel forward and reverse query error correction to long queries, and by the parallel processing mode, accuracy is guaranteed while processing time of query error correction is saved.

The invention discloses a wind power forecast method based on an error correction and promotion wavelet combination forecast model. According to the method, wind power history data is processed through utilization of a promotion wavelet decomposition technology, main characteristics of a power data sequence can be improved, frequency components with relatively obvious characteristics can be obtained, and the denoising effect can be achieved, thereby applying to various forecast algorithms. A suitable forecast model is selected according to the characteristics of high and low frequency components, the deficiency of a single forecast method can be removed, and the forecast precision can be greatly improved. According to the method, processing errors are corrected through utilization of an error layered analysis method. Compared with the method of obtaining a next moment error forecast value by directly using the forecast model, the method has the advantage that under the condition that relatively high fluctuation occurs in the errors, the next moment error condition and compensation strength can be analyzed precisely, the errors resulting from an error forecast process can be reduced, and the errors of the integrated forecast method can be reduced.

Methods, apparatus and systems for error correction of n-valued symbols in (p,k) codewords including Reed Solomon codes of p n-valued symbols with n>2 and k information symbols have been disclosed. Coders and decoders using a Linear Feedback Shift Registers (LFSR) are applied. An LFSR can be in Fibonacci or Galois configuration. Errors can be corrected by execution of an n-valued expression in a deterministic way. Error correcting methods using Galois arithmetic are disclosed. Methods using Cramer's rule are also disclosed. Deterministic error correction methods based on known symbols in error are provided, making first determining error magnitudes not necessary. An error location methods using up and down state tracking is provided. Methods and apparatus executing the methods with binary circuits are also disclosed. Systems using the error correcting methods, including communication systems and data storage systems are also provided.

A cloud-based ETL system provides error detection, error correction and reporting of data integration flows hosted by cloud services. Categories of errors are identified using one or more checks at different points of a data integration flow and one or more actions selected based at least in part on the error category. A determination can be made whether the error category is fault tolerant and one or more actions can be selected based at least in part on the error fault tolerance to correct the error, restart a flow, or generate a notification assisting a user to correct the error.

A system that facilitates error correction within a register file in a central processing unit (CPU). During execution of an instruction by the CPU, the system retrieves a dataword and an associated syndrome from a source register in the register file. Next, the system uses information in the dataword and the associated syndrome to detect, and if necessary correct, an error in the dataword or associated syndrome. This error detection and correction takes place in parallel with using the dataword to perform a computational operation specified by the instruction. If an error is detected, the system prevents the instruction from performing a writeback to a destination register in the register file. The system also writes a corrected dataword to the source register in the register file. Next, the system flushes the instruction pipeline, and restarts execution of the instruction so that the corrected dataword is retrieved for the computational operation.

The invention discloses a periodic self-checking recovery method of a random access memory, which can perform error tolerance and correction design on the random access memory. The method comprises the steps of firstly performing redundancy processing on the random access memory, performing three-evaluation and two-judgment and consistency comparison on redundancy output results through a design judgment module, taking judgment results as error correction input data, and taking consistency comparison results as error correction enabling data. Simultaneously an address generating module periodically generates memory read addresses, so as to realize error detection control. The invention can provide an error detection and correction method for the random access memory which easily generates error caused by external causes (such as space radiation environment and the like), and improves the problem of error accumulate invalidation of the traditional redundancy error tolerance technology, the error correction capability is not limited by error correction and detection algorithm, and the memory is effectively protected.

The invention discloses a scalable low-latency feedback control device for quantum bits. The device realizes the feedback control of the quantum states of multiple quantum bits by means of digital signal processing technology and a quantum mechanical principle based on a high-speed microwave baseband signal transceiving hardware circuit board. The quantum feedback control device designed in the present invention is different from the feedback control applied in the classic field, and can generate synchronous microwave pulses for operating superconducting quantum bits, can accurately define thenumber of times, the time and the strength of quantum measurement, demodulates measurement signals in real time, deploys a quantum feedback algorithm on an FPGA, and has extremely low feedback delayand excellent scalability so as to accurately control a system integrating multiple quantum bits and to satisfy a requirement for running a measurement-based quantum error correction algorithm on a quantum chip.