133 results about "Quantum error correction" patented technology

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting errors in computations executed by a quantum computer. In one aspect, a method includes obtaining error correction data for each of a plurality of time steps during the calculation; and processing a respective input for each of a plurality of update time steps using one or more machine learning decoder models to generate a prediction of whether an error has occurred in the computation, where each update time step corresponds to one or more of the time steps, and where each update time step corresponds to one or more of the time steps. The respective input for each of the plurality of updated time steps is generated from the error correction data for the corresponding one or more time steps.

A quantum computing system comprises a classical computing entity, a controller, and a quantum processor. The controller is configured to control operation of the quantum processor and communicate with the computing entity. The controller causes performance of syndrome circuit segments to generate syndromes of logical qubits. The syndrome circuit segment is performed at least partially by causing performance of a sequence of transportation operations and at-least-two-physical-qubits interactions. Each transportation operation of the sequence causes physical transport of at least one of a respective data qubit of the logical qubit or a respective ancilla qubit into a respective interaction zone defined by the quantum processor. A respective at-least-two-physical-qubits interaction is performed within the respective interaction zone. Using the syndrome, at least one quantum error correction is determined; and the controller causes a classical memory to be updated based on the syndrome and / or the quantum error correction.

A decoder apparatus for decoding syndrome data of a quantum error correction code is disclosed. The decoder apparatus is configured to receive position data representing the respective location of defects from the syndrome data in a decoding graph. The decoder apparatus also receives dimension data of the decoding graph and determines the respective location of each of the plurality of defects in the decoding graph based on the position data and the dimension data. The decoder apparatus then decodes the syndrome data using the determined respective location of each of the plurality of defects.

Correcting quantum errors based on quantum error correction caches (QECCs) is disclosed herein. In one example, a processor device of a quantum computing device is to receive an indication of an occurrence of a quantum error that affects a qubit. The processor device identifies a QECC entry within a plurality of QECC entries of a first QECC of the quantum computing device, wherein the QECC entry corresponds to a previous occurrence of the quantum error. The processor device obtains metadata associated with the previous occurrence of the first quantum error from the QECC entry, and determines a corrective action based on the metadata. The processor device performs the corrective action to remedy the quantum error.

A computing system is provided, including one or more processing devices configured to receive an extended stabilizer form of a quantum error correction code. The one or more processing devices are further configured to receive a logical Clifford operation specification of a logical Clifford operation. Based at least in part on the extended stabilizer form, the one or more processing devices are further configured to compute a stabilizer tableau of the quantum error correction code. Based at least in part on the stabilizer tableau and the logical Clifford operation specification, the one or more processing devices are further configured to compute a physical representation matrix of the logical Clifford operation. The one or more processing devices are further configured to output the physical representation matrix.

A method for decoding qubit errors of a quantum computing system that implements a quantum error correction (QEC) code is disclosed. Qubits are subject to a set of error types including a set of non-decomposable error types and a set of decomposable error types. An initial matching graph (MG) is generated based on the non-decomposable error types. The initial MG includes a set of nodes and a set of non-decomposable edges. Non-decomposable edges are associated with non-decomposable error types occurring on qubits. A set of decomposable potential-edges is generated based on the decomposable error types. Decomposable potential-edges are associated with decomposable error types occurring on qubits. An updated MG is generated by applying a local-connectivity test to each decomposable potential-edge. The updated MG includes the set of nodes and a set of updated edges including the set of non-decomposable edges and a set of decomposable edges.

The disclosure is directed to a method performed during an execution of a quantum algorithm, via a quantum computing system (QCS) that includes a set of qubits and a set of classical processor devices. The quantum algorithm includes a quantum error correction (QEC) code that includes a set of qubit measurements over the set of qubits. Prior to the execution of the QA, the classical processor devices generate a matching graph (MG). During the execution of the quantum algorithm, the following operations are interleaved. A current subset of qubit measurements is performed. The qubit measurements are based on the QEC code. The classical processor devices update the MG based on values of the current subset of qubit measurements. The set of classical processor devices decodes one or more qubit errors based on the updated MG.

Disclosed herein is a computer-implemented quantum error correction method for decoding errors in a quantum computer system. The quantum computer system comprises a decoder apparatus and a register of quantum devices. The method comprises receiving, at the decoder apparatus, syndrome data in an initial state, the syndrome data being representative of an error state of the quantum devices in the register of quantum devices, and graph data representative of a graph comprising a plurality of error nodes and a plurality of check nodes. The error nodes represent error mechanisms that can occur on the register of quantum devices. Each check node is associated with one or more measurements which can be performed on the register of quantum devices. The initial state of the syndrome data indicates a check value of marked or unmarked for each check node based on an outcome of its associated one or more measurements. The method further comprises determining, based on a statistical model of error rates associated with the error mechanisms, an error probability associated with each of the one or more error nodes; and generating modified graph data by iteratively performing linear operations on the graph data and syndrome data based on a current state of the syndrome data to determine an independent error node associated with each marked check node. The method also comprises determining, by the decoder apparatus, a correction for the error state based on the modified graph data and, optionally, based on the error probabilities associated with the one or more error nodes.

A method for synthesizing Boolean circuits for an error correction decoder. The method may include: providing one or more input binary variables derived from one or more syndrome measurements; providing a mapping representative of a quantum error correction decoder; for said one or more input binary variables providing corresponding output binary variables representative of one or more recovery operations for qubits, wherein said output binary variables are generated using said mapping; and using said one or more input binary variables and said corresponding output binary variables to synthesize at least one Boolean circuit. A quantum error correction decoder chip comprising one or more Boolean circuits.

Transformer neural network based decoder for decoding Quantum Error Correction Codes (QECC), comprising, an input layer, a plurality of decoding layers, and an output layer. The input layer is adapted to receive initial noise estimation computed by a noise estimator for noise injected to syndrome bits of codewords encoded using QECC and transmitted over transmission channel(s) subject to interference, and create embeddings for the syndrome bits. The decoding layers adapted to compute an estimated logical operator matrix of each codeword, each comprises a self-attention layer constructed according to a mask indicative of a relation between the embeddings derived from a parity-check matrix of the error correction code. The plurality of decoding layers are trained using a combined loss function directed to minimize LER, BER, and error rate of the noise estimator. The output layer is adapted to produce a vector representing predicted soft error of the codeword's logical operator matrix.

Methods, systems, and devices for enhancing decoding using in-phase and quadrature information. In one aspect, a method includes obtaining in-phase and quadrature values for multiple measurement operations in a quantum error correction code for quantum computing; classifying the measurement results of the plurality of measurement operations using the corresponding in-phase and quadrature values; generating a detector graph of nodes and edges, wherein the detector graph marks detection events occurring in the classified measurements; assigning weights to the edges of the detector graph using a posterior probability distribution of the classified measurements to generate a weighted detector graph; and performing a decoding process on the weighted detector graph to calculate a decoded output of the decoding process, where the decoded output predicts an occurrence of an error in the quantum computation.

Error-corrected quantum computation using transversal gates and correlated decoding is provided. A first and second logical qubit is encoded into physical qubits according to a quantum error correcting code. Based on the quantum error correcting code, a bipartite decoding graph is constructed corresponding to the first and the second logical qubits, the bipartite decoding graph comprising a plurality of detector nodes and a plurality of error nodes, each error node corresponding to an error mechanism. A transversal gate is applied to the first and the second logical qubits. Syndrome measurement of the first and the second logical qubits is performed. For each of the plurality of detector nodes affected by the corresponding error mechanism of one of the plurality of error nodes, an edge is generated on the bipartite decoding graph therebetween. A physical error configuration is determined from the bipartite decoding graph.

The invention discloses a multi-mode starting automatic control method and system based on a PC Farm array server, and relates to the technical field of server cluster management.The method comprises the steps that a central node creates a fine-grained strategy instruction and a corresponding mirror image instruction according to deployment requirements, and the fine-grained strategy instruction and the corresponding mirror image instruction are compressed into a mirror image compressed package through LZMA; the edge node extracts the verification label from the mirror image compressed package, analyzes the verification label through quantum error correction control, repairs a bit flipping error, and generates an anti-interference standardized instruction stream; based on the anti-interference standardized instruction stream, generating a quantum code stream data block through Hamming code coding, writing the quantum code stream data block into a configuration interface address, and correcting signal deviation to trigger a reset command; and executing the reset command, collecting a BIOS startup log, and comparing the BIOS startup log with pre-stored features to generate a startup state verification report. According to the method, accurate calibration and sequential control of hardware configuration are realized, the accuracy of starting parameters is ensured, and the high efficiency and stability of automatic deployment are improved.

A method (50) of applying a Crifford circuit to a correction fault in a qubit register (12) of a quantum computer (10) includes receiving (52) circuit data defining the Crifford circuit; receiving (56) additional data identifying one or more measurements for each of a plurality of faces (48) belonging to the lattice (44); issuing (58) a result code based on the circuit data, the result code comprising a series of result checks, each result check corresponding to an expected error syndrome for application of the Crifford circuit to the qubit register; and issuing (60) a topology result code based on the circuit data, the additional data and the result code, the topology result code comprising a series of check operators that support quantum error correction via a topology decoder, thereby enabling fault correction in the application of the Crifford circuit to the quantum bit register.

Technologies for performing error correction in a quantum circuit of a quantum computing system are disclosed. A quantum error correction code (QECC) is selected. The QECC is associated with a codespace. The quantum computing system identifies, based on one or more properties of the QECC, one or more diagonal physical gates in the quantum circuit that induces a target logical gate and preserves the codespace. The quantum computing system configures the quantum computing circuit to implement a quantum error correction protocol using the QECC and at least one of the identified diagonal physical gates.

A quantum error correction system that can realize a scheme which, when the quantum system suffers some noise, the quantum system itself can act on itself to correct itself against this noise is provided. The quantum error correction system includes a quantum material and a bi-chromatic recovery drive generator in communication with the quantum material. The bi-chromatic recovery drive generator sends a waveform to the quantum material.

Systems and methods for distributed quantum computing are disclosed. For example, method is provided for implementing quantum error correction in a quantum computing system, the quantum computing system comprising one or more physically distinct quantum processing units. The method comprises selecting an error correcting code having a multidimensional topology; dividing the topology into a plurality of tiles, each having one or more connections with one or more other tiles; associating each tile with one or more of the quantum processing units; implementing the connections between the tiles by entangling the quantum states of pairs of selected qubits in different quantum processing units, wherein entangling the quantum states of a pair of selected qubits comprises: controlling one or more switches to define a communications path between the selected qubits and an entanglement generator, receiving signals from the selected qubits at the entanglement generator, and processing the signals at the entanglement generator to create quantum entanglement between the signals and the method further comprises: applying the quantum error correcting code during a quantum operation.

A messaging system for a distributed quantum system (e.g. a quantum control system and / or a quantum error correction unit). The system has a plurality of real-time units (e.g. decoders, sequencers or

A computer-implemented quantum error correction method uses a decoder apparatus for decoding errors in a register of quantum devices. The decoder apparatus comprises processing elements (PEs) in a pro

Error-corrected quantum computation using transversal gates and correlated decoding is provided. A first and second logical qubit is encoded into physical qubits according to a quantum error correcting code. Based on the quantum error correcting code, a bipartite decoding graph is constructed corresponding to the first and the second logical qubits, the bipartite decoding graph comprising a plurality of detector nodes and a plurality of error nodes, each error node corresponding to an error mechanism. A transversal gate is applied to the first and the second logical qubits. Syndrome measurement of the first and the second logical qubits is performed. For each of the plurality of detector nodes affected by the corresponding error mechanism of one of the plurality of error nodes, an edge is generated on the bipartite decoding graph therebetween. A physical error configuration is determined from the bipartite decoding graph.

One or more systems, devices, computer program products and / or computer- implemented methods of use provided herein relate to regional decoders for quantum error correction. Accordingly, a system can comprise a memory that can store computer executable components. The system can further comprise a processor that can execute at least one of the computer executable components that can map one or more regional decoders to one or more modules, wherein each of the one or more modules comprise one or more logical qubits, and wherein each of the one or more regional decoders operate on a region comprising one module and at least a subsection of another module. The at least one of the computer executable component can further coordinate activation of the one or more regional decoders by facilitating logical operations between a first logical qubit and a second logical qubit.

A system and method are provided for compiling a bare quantum-logic circuit. The method includes receiving the bare quantum-logic circuit including multiple encoded operations and multiple syndrome measurements, where each encoded operation and each syndrome measurement may be associated with an input and / or output quantum error correction code; interleaving multiple random stabilizers and / or multiple random stabilizers associated with multiple random operations between adjacent encoded operations, between adjacent syndrome measurements, and / or between adjacent encoded operations and syndrome measurements, respectively, to provide one or more modified quantum-logic circuits logically equivalent to the bare quantum-logic circuit; and outputting the one or more modified quantum-logic circuits to a quantum information processor or a simulator of quantum information processor for execution, where when executed, the one or more modified quantum-logic circuits enable a noise-tailored outcome, having reduced coherent and non-unital logical noise.

The application discloses a liquid cooling-based quantum computing server optimization method and system, relates to the technical field of quantum computing, and discloses the liquid cooling-based quantum computing server optimization method and system, which acquires quantum state and liquid cooling state data in real time, dynamically generates optimization parameters by using an AI model, and cooperatively adjusts quantum error correction operation and a liquid cooling circulation system, solves the technical problems of low heat dissipation efficiency and large error correction resource consumption in the traditional scheme, and improves system stability and computing efficiency.

It is described a method of performing quantum error correction on a measurement-based quantum computer using fault complexes. A first chain complex is derived based on a first parity check matrix (PCM) and a second PCM that describe a quantum surface code. A second chain complex is derived based on a third PCM of a binary linear code. A fault complex having one or more boundary operators is generated based on a tensor product between the first and the second chain complexes. Qubits on the measurement-based quantum computer are prepared to implement a fault-tolerant graph state based on the one or more boundary operators of the fault complex. Quantum error correction can be performed based on the measurement of the prepared qubits.

Methods, systems, and apparatus for predicting an occurrence of errors in a quantum computation. In one aspect, a method includes updating edge weights of a second quantum error correction detector graph by performing a local search of a first quantum error correction detector graph, wherein performing the local search comprises, for each detection event in the first quantum error correction detector graph, reweighting complementary edges in the second quantum error correction detector graph using single-edge errors on an edge that connects the detection event to a nearest other detection event; and executing a decoding process on the second quantum error correction detector graph to compute a decoding output of the decoding process, wherein the decoding output predicts the occurrence of errors in the quantum computation.

The present disclosure relates to the technical field of computers, and discloses a quantum error correction code generation method and device, computer equipment and a storage medium. The method comprises: in the 0th round, the 1st round, the 2nd round and the 3rd round, measuring a plurality of first type detection operators, measuring a plurality of second type detection operators, measuring a plurality of first type detection operators and measuring a plurality of third type detection operators; in the tth round, determining a tth round measurement result of a tth round stabilizer operator; in the t+1th round, determining a t+1th round measurement result of a t+1th round stabilizer operator; in the t+2th round, determining a t+2th round measurement result of a t+2th round stabilizer operator; and in the t+3th round, determining a t+3th round measurement result of a t+3th round stabilizer operator.

A quantum computing system comprises a classical computing entity, a controller, and a quantum processor. The controller is configured to control the operation of the quantum processor and communicate with the computing entity. The controller triggers the implementation of a syndrome circuit segment to generate a syndrome of logic qubits. The syndrome circuit segment is implemented, at least in part, by triggering the implementation of an interaction of a set of at least two physical qubits. The logic qubits comprise multiple data qubits logically organized in real projective plane topology, and the interaction of the set of at least two physical qubits is determined based on a stabilizer determined based on the real projective plane topology of the logic qubits. The classical computing entity determines at least one quantum error correction based on the syndrome. The classical memory of the controller or the classical computing entity is updated based on the syndrome and / or at least one quantum error correction.