16results about "Checking code calculations" patented technology

In some examples, a system groups a multitude of blocks of coded data into first segments, where each first segment comprises several blocks from the multitude of blocks, and the coded data is based on the application of a deletion correction coding to input data. The system stores the first segments in corresponding error domains of a first set of error domains in a first deletion correction configuration, where the first deletion correction configuration allows error recovery in response to lost coded data in a specified number of error domains. The system transitions from the first deletion correction configuration to a second deletion correction configuration by reorganizing the first segments into second segments, where each second segment comprises a different number of blocks of coded data than a first segment.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3 / 4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

This invention provides an encoding and decoding method and apparatus for Structured Low-Density Parity-Check (LDPC) codes. The encoding method includes: determining a base matrix for encoding, the base matrix comprising one or more submatrices, the submatrices including a top-left submatrix Hb1 and a top-left submatrix Hb2, wherein the number of rows and columns of the top-left submatrix Hb1 and Hb2 are both less than the number of rows and columns of the base matrix Hb, and the top-left submatrix Hb1 is the top-left submatrix of the top-left submatrix Hb2; performing LDPC encoding operations on the source information bit sequence based on the base matrix and the corresponding extension factor Z to obtain a codeword sequence, where Z is a positive integer greater than or equal to 1. The above technical solution provided by this invention solves the problems of insufficient flexibility and inability to support incremental redundancy HARQ in related technologies for LDPC encoders and decoders.

A turbo code designing method for designing a turbo encoding using a high-performance interleaver is provided. A turbo encoder is provided with a first convolutional encoder, an interleaver, and a second convolutional encoder. The first convolutional encoder generates a first parity stream of input data by use of a predetermined RSC encoding. The interleaver swaps an order of series inside the input data based on a first rule to generate a swapped data. The second convolutional encoder es a second parity stream of the swapped data by use of the RSC encoder. The turbo code designing method includes selecting a polynomial that indicate the RSC encoding from a Galois field of polynomials and designing the first rule of the inter leaver based on the RSC encoding.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 1 / 2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 288 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

Methods, systems, and apparatus for producing CCZ states and T states. In one aspect, a method for transforming a CCZ state into three T states includes obtaining a first target qubit, a second target qubit and a third target qubit in a CCZ state; performing a X−1 / 2 gate on the third target qubit; performing an X gate on the first target qubit and the second target qubit using the third target qubit as a control; performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control; performing a Z−1 / 4 gate on the third target qubit; and performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control to obtain the three T states.

According to some embodiments, a method for use in a wireless transmitter of a wireless communication network comprises encoding information bits using a parity check matrix (PCM) and transmitting the encoded information bits to a wireless receiver. The parity check matrix (PCM) is optimized according to two or more approximate cycle extrinsic message degree (ACE) constraints. In some embodiments, a first portion of the PCM is optimized according to a first ACE constraint and a second portion of the PCM is optimized according to a second ACE constraint.

This application discloses an encoding method, an apparatus, a communications device, and a communications system. The method includes: encoding an input bit sequence by using a low-density parity-check LDPC matrix, where a base graph of the LDPC matrix is represented by a matrix of m rows and n columns, m is an integer greater than or equal to 5, and n is an integer greater than or equal to 27; the base graph includes at least a submatrix A and a submatrix B; the submatrix A is a matrix of five rows and 22 columns; and the submatrix B is a matrix of five rows and five columns, and the submatrix B includes a column whose weight is 3 and a submatrix B' with a bidiagonal structure. According to the encoding method, the apparatus, the communications device, and the communications system in this application, encoding requirements of information bit sequences of a plurality of lengths can be supported.

Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word.

This invention relates to the generation of a set of raised quasi-cyclic LDPC codes. Methods for generating codes, methods for encoding and decoding data, and encoders and decoders for performing encoding and decoding are disclosed. In an embodiment, the method for raising subcodes from a base code for encoding and decoding data includes determining a single combination of a cycle size, a raising function, and a label base matrix (PCM) based on information length and coding rate using data stored in a raising table. The raising table is defined during the code generation phase. The method also includes calculating multiple shifts for the subcodes. Each shift is calculated by applying the raising function to the label base matrix (PCM) using an index defined with the cycle size, and the resulting subPCM is used to encode or decode data.

The present invention relates to a transmission method using LDPC codes with row-orthogonal structure and a device therefor. A method for encoding a quasi-cyclic low density parity check (LDPC) code according to an embodiment of the present invention can include the steps of generating a multi-edge LDPC code matrix including a high-rate code matrix and a single parity check code matrix; and encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix is formed by concatenating a first matrix having a non-row-orthogonal structure matrix and a second matrix having a pure row-orthogonal structure.

Methods, systems, and devices for wireless communications are described. A wireless communication device may implement a low- density parity-check (LDPC) code to encode and / or decode bits of a signal. The LDPC code may be defined by a base graph and a lifting scheme. The base graph may include check nodes and variable nodes. The lifting scheme may define a quantity of copies of the base graph used to generate the LDPC code and respective cyclic shifts associated with connected variable nodes and check nodes. The respective cycle shifts may be defined such that one or more cycles associated with a minimum length of the LDPC code are associated with a restriction on second degree variable nodes, nodes associated with least significant bits, or a combination thereof. Additionally, or alternatively, the respective cycle shifts may be defined such that a weighted girth of the LDPC code satisfies a threshold.

A non-transitory computer-readable medium and related method, including processing circuitry, which performs in-order error correction code construction. The processing circuitry receives a first plurality of matrices. The processing circuitry is to generate a second plurality of matrices based on at least one additive candidate matrix and each respective matrix of the first plurality of matrices. The processing circuitry then generates a third plurality of matrices based on at least one additive test matrix and each respective matrix of the second plurality of matrices. Each respective weight indicative of respective extensibility for each matrix of the second plurality of matrices is determined based on the third plurality of matrices. At least one matrix from the second plurality of matrices is then selected by processing circuitry based on the determined weights. The processing circuitry then generates an error correction code based on one of the at least one selected matrix.