72results about "Checking code calculations" patented technology

This application provides example concatenated code encoding and decoding methods. In one example method, polar code encoding is performed on a to-be-encoded message bit sequence based on a frozen bit set and a message bit set that are of a first polar code, to obtain a first encoded code word whose length is N_o. The first encoded code word is interleaved to obtain a second encoded code word, and optimized low-density parity-check (LDPC) code encoding is performed on the second encoded code word to obtain a concatenated code word. Interleaving includes both outer interleaving and inner interleaving. The concatenated code word is then outputted.

Certain aspects of this disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structures. A method for wireless communication by a transmitting device is provided. This method generally includes: encoding a set of information bits based on an LDPC code to generate a codeword, the LDPC code being defined by a basic matrix having a first number of variable nodes and a second number of parity nodes; puncturing the codeword according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to generate a punctured codeword; adding at least one additional parity bit to the punctured at least two variable nodes; and transmitting the punctured codeword.

A method for constructing a permutation matrix or a check matrix, a processing device, a storage medium and a coding method. The method for constructing the permutation matrix comprises: obtaining a base matrix for the permutation matrix; and performing lifting on the base matrix to obtain the permutation matrix. The lifting on the base matrix to obtain the permutation matrix comprises: obtaining a modulus graph of the base matrix, obtaining each macro ring in the modulus graph, and for each macro ring in the modulus graph, determining the size of a short ring corresponding to the macro ring in a Tanner graph of a check matrix corresponding to the permutation matrix from an equivalent cycle value ECS of the macro ring, and determining whether at least one cycle value in the macro ring needs to be set according to the size of the short ring. The method can more efficiently obtain a required permutation matrix.

An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3 / 4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

The present disclosure provides methods, components, devices, and systems for low density parity check (LDPC) coding. Some aspects are more particularly directed to expanding an LDPC codeword to produce a longer codeword. In some examples, a first wireless device may generate a baseline LDPC code by performing a first boost on a basis matrix, which may produce an LDPC code for a current Wi-Fi implementation. The first wireless device may then perform a second boost or re-boost (such as a cyclic boost, a product boost, an exchange boost, or a combination thereof) to generate an extended boosted code. The extended lifted code may be an extension of the first LDPC code such that the first LDPC code may be held as part of the extended code. The first wireless device may then transmit the expanded LDPC code as an expanded or boosted codeword.

Techniques pertaining to low-density parity-check (LDPC) encoding enhancement for next-generation wireless local area network (WLAN) systems in wireless communications are described. An apparatus (e.g., a station (STA) ) encodes a plurality of bits with an enlarged codeword length. The apparatus then communicates with the encoded plurality of bits in a wireless communication system.

In some examples, a system groups a multitude of blocks of coded data into first segments, where each first segment comprises several blocks from the multitude of blocks, and the coded data is based on the application of a deletion correction coding to input data. The system stores the first segments in corresponding error domains of a first set of error domains in a first deletion correction configuration, where the first deletion correction configuration allows error recovery in response to lost coded data in a specified number of error domains. The system transitions from the first deletion correction configuration to a second deletion correction configuration by reorganizing the first segments into second segments, where each second segment comprises a different number of blocks of coded data than a first segment.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3 / 4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

This invention provides an encoding and decoding method and apparatus for Structured Low-Density Parity-Check (LDPC) codes. The encoding method includes: determining a base matrix for encoding, the base matrix comprising one or more submatrices, the submatrices including a top-left submatrix Hb1 and a top-left submatrix Hb2, wherein the number of rows and columns of the top-left submatrix Hb1 and Hb2 are both less than the number of rows and columns of the base matrix Hb, and the top-left submatrix Hb1 is the top-left submatrix of the top-left submatrix Hb2; performing LDPC encoding operations on the source information bit sequence based on the base matrix and the corresponding extension factor Z to obtain a codeword sequence, where Z is a positive integer greater than or equal to 1. The above technical solution provided by this invention solves the problems of insufficient flexibility and inability to support incremental redundancy HARQ in related technologies for LDPC encoders and decoders.

This application discloses an encoding method, an apparatus, a communications device, and a communications system. The method includes: encoding an input bit sequence by using a low-density parity-check LDPC matrix, where a base graph of the LDPC matrix is represented by a matrix of m rows and n columns, m is an integer greater than or equal to 5, and n is an integer greater than or equal to 27; the base graph includes at least a submatrix A and a submatrix B; the submatrix A is a matrix of five rows and 22 columns; and the submatrix B is a matrix of five rows and five columns, and the submatrix B includes a column whose weight is 3 and a submatrix B' with a bidiagonal structure. According to the encoding method, the apparatus, the communications device, and the communications system in this application, encoding requirements of information bit sequences of a plurality of lengths can be supported.

This disclosure describes systems, methods, and devices related to for low-density parity-check (LDPC) Wi-Fi coding and decoding. A device may identify a first base matrix to generate LDPC codewords of 1944 bits; identify a mask matrix to generate a second base matrix based on the first base matrix used to generate LDPC codewords of 3888 bits, the entries of the mask matrix having values of 0, 1, and −1; generate the second base matrix by multiplying each the first base matrix by the mask matrix, the entries of the second base matrix indicative of respective cyclic shifts to apply to an identity matrix; generate a parity check matrix by multiplying the second base matrix by the identity matrix; generate a LDPC codeword of 3888 bits based on the parity check matrix; and transmit a frame including the LDPC codeword.

A method for data transfer via a communication channel (11) is provided, comprising: determining, in a first data processing unit (10), a codeword from a message using a channel code and sending the codeword via the communication channel (11), wherein the channel code comprises an outer code concatenated with an inner code; the outer code is one of a Reed-Solomon code, a folded Reed-Solomon code, a twisted Reed-Solomon code, and a generalized Reed-Solomon code; the inner code is a neural network code comprising a neural encoder-decoder pair, which includes an encoding neural network (21) and a decoding neural network (23); a nonlinear channel and / or a noisy channel (22) is arranged between the encoding neural network (21) and the decoding neural network (23); and the neural encoder-decoder pair has been adapted such that the decoding neural network (23) provides an estimated outer codeword symbol for an input outer codeword symbol by training the neural encoder-decoder pair using a training data set which comprises a plurality of outer codewords determined from a plurality of input messages by an outer code encoder (31), wherein one or more outer codeword symbols of the plurality of outer codewords are used as an input to the encoding neural network (21). Moreover, a further method and systems for data transfer via a communication channel (11) are provided.

Low density parity check (LDPC) codes for wireless communications are constructed to adapt to channel conditions. A method of encoding input bits by an LDPC code to obtain encoded bits is provided. A method of decoding the encoded bits is also provided. The LDPC code has a parity check matrix obtained by lifting a protograph matrix according to a lifting matrix, in which the lifting matrix is based on a polar kernel.

Methods, systems, and devices for wireless communications are described. A first device may transmit, to a second device, a bit sequence encoded with a convolutional encoder associated with a constraint length of five, six, or seven, and associated with a subset of polynomials of a polynomial set, wherein the polynomial set is selected from a group of polynomial sets, expressed with octal values, consisting of polynomial sets described herein.

A coding method and apparatus are provided. The method includes: coding an information bit by using a preset generator matrix of a systematic (U|U+V)-code to obtain a codeword of a systematic code. The preset generator matrix of the systematic (U|U+V)-code includes a first identity sub-matrix of a U code and a second identity sub-matrix of a V code. A plurality of elements in a same column as the first identity sub-matrix are all 0. A plurality of elements in a same column as the second identity sub-matrix are all 0.

An encoding method and apparatus, a decoding method and apparatus, and a device are provided. The encoding method includes: obtaining K to-be-encoded bits (S301), where K is a positive integer; determining a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed based on a preset position relationship, and the sub-block includes a plurality of first generator matrix cores (S302); generating a second generator matrix based on the first generator matrix, where the second generator matrix includes T sub-blocks, and a position relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset position relationship (S303), where T is a positive integer; and polar encoding the K to-be-encoded bits based on the second generator matrix (S304), to obtain encoded bits. This can reduce encoding / decoding complexity.

An encoding method and apparatus, a decoding method and apparatus, and a device are provided. The encoding method includes: obtaining K to-be-encoded bits (S301), where K is a positive integer; determining a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed based on a preset position relationship, and the sub-block includes a plurality of first generator matrix cores (S302); generating a second generator matrix based on the first generator matrix, where the second generator matrix includes T sub-blocks, and a position relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset position relationship (S303), where T is a positive integer; and polar encoding the K to-be-encoded bits based on the second generator matrix (S304), to obtain encoded bits. This can reduce encoding / decoding complexity.

A turbo code designing method for designing a turbo encoding using a high-performance interleaver is provided. A turbo encoder is provided with a first convolutional encoder, an interleaver, and a second convolutional encoder. The first convolutional encoder generates a first parity stream of input data by use of a predetermined RSC encoding. The interleaver swaps an order of series inside the input data based on a first rule to generate a swapped data. The second convolutional encoder es a second parity stream of the swapped data by use of the RSC encoder. The turbo code designing method includes selecting a polynomial that indicate the RSC encoding from a Galois field of polynomials and designing the first rule of the inter leaver based on the RSC encoding.

An LDPC code-based communication method and a communication apparatus are provided. Through row grouping and column grouping, an LDPC base matrix may be divided into a plurality of units of a same scale. The plurality of units include three types: a first unit, a second unit, and a third unit. A column weight of each column of the first unit is 1. A column weight of at least one column of the second unit is 1, and a column weight of a remaining column is 0. A column weight of each column of the third unit is 0. None of the column weights of the columns of the first unit, the second unit, and the third unit is greater than 1. Therefore, a receiver device may perform parallel decoding of a plurality of QC blocks on a codeword sequence corresponding to each unit, and a case in which decoding cannot be performed does not occur. This helps improve decoding performance.

The invention relates to a method for encoding at least one block of K. Z source data that emits at least one codeword of size N. Z, where Z is an integer expansion factor, Z ≥ 1, the method implementing a step of encoding (53) the K. Z source data using a parity-check matrix H of size (M. Z x N. Z). According to the invention, the parity-check matrix H is obtained (52) from a basis matrix BG' of size M x N by replacing each element of the basis matrix BG' with an expansion matrix of size Z x Z, the basis matrix BG' being expressed in the form of (I). The expansion matrix C comprises at least two consecutive blocks of rows each having a different number of rows equal to a prime number or to the square of a prime number, each block of rows comprising at least one instance of a diagonal matrix.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 1 / 2, a second parity check matrix corresponding to a first exponent matrix comprising 1152 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 2 / 3, a second parity check matrix corresponding to a first exponent matrix comprising 768 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 1 / 2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 288 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

An apparatus for processing a low density parity check code and a method thereof are disclosed. The method comprises the following steps: identifying a parity check matrix; encoding the code block based on the parity check matrix; and transmitting at least a portion of the encoded code block. The parity check matrix includes an information portion and a parity check portion. The parity portion comprises: a first portion (B) comprising a plurality of first permutation matrices, a second portion (D) comprising a second permutation matrix, a third portion (E) comprising a third permutation matrix, a fourth portion (T) comprising a plurality of unit matrices arranged diagonally in the fourth portion, and a plurality of fourth permutation matrices arranged diagonally in the fourth portion, the plurality of fourth permutation matrices are arranged below the plurality of unit matrices. And the fourth part (T) is in a square matrix form. A matrix according to (E) (T-1) (B) + D corresponds to a cyclic permutation matrix that is not a unit matrix.

Methods, systems, and apparatus for producing CCZ states and T states. In one aspect, a method for transforming a CCZ state into three T states includes obtaining a first target qubit, a second target qubit and a third target qubit in a CCZ state; performing a X−1 / 2 gate on the third target qubit; performing an X gate on the first target qubit and the second target qubit using the third target qubit as a control; performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control; performing a Z−1 / 4 gate on the third target qubit; and performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control to obtain the three T states.

The invention relates to a method for encoding at least one block of source data, generating at least one codeword of size, where an integer expansion factor, said method implementing a step of encoding (53) said source data using a parity matrix of size. According to the invention, the parity matrix is obtained (52) from a modified basis matrix of size by replacing each element of the modified basis matrix of size with an expansion matrix of size, the modified basis matrix being represented in Form (I). The extension matrix includes at least two row blocks, each row block including the same number of rows, each row block including a diagonal matrix.

The present invention provide a system and method for generating a catalogue of graphs that acts as a source for error correcting codes. A D3 chord index notation is used to describe the graphs. A list of (3, g) Hamiltonian graphs for even girth g is created to satisfy the condition 6 g 16. Each of the lists is infinite and is used for creating LDPC codes of high quality. Furthermore, the embodiments herein generalizes the application scenario for usage of LDPC codes. The embodiments herein utilizes dynamically changing error-correction codes in wireless communication systems.

A forward error correction ( EEC ) system and method are provided, intended for DVB-S2 data streams in an on-board processing transponder of a LEO communication satellite. The system comprises an LDPC encoder circuit implemented in an FPGA, and a terrestrial cellular network compatible soft -decis ion- EEC ( SD-FEC ) LDPC decoder module, implemented in an AS IC module which is embedded in the FPGA.

An apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, based at least on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate R of 3 / 4, a second parity check matrix for a second QC-LDPC code, wherein the second QC-LDPC code has a code block size that is four times a code block size of the first QC-LDPC code. The one or more processors may be configured to encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data. In some implementations, the code block size of the second QC-LDPC code may be 7776 bits.