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Systems and methods for block-kronecker based low density parity check (LDPC) code with 3 / 4 code rate
An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 3 / 4, a second parity check matrix corresponding to a first exponent matrix comprising 576 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.
Owner:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
Systems and methods for block-kronecker based low density parity check (LDPC) code with 5 / 6 code rate
An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5 / 6, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.
Owner:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
Transmission device, transmission method, reception device, and reception method
InactiveUS20240421831A1Error correction/detection using LDPC codesChecking code calculationsCommunication qualityAlgorithm
The present technology relates to a transmission device, a transmission method, a reception device, and a reception method capable of ensuring good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 1224 or 1152 bits and the coding rate r of 144 / 1224 or 144 / 1152. The parity check matrix includes an A matrix of M1 rows and K columns represented by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure of M1 rows and M1 columns, a Z matrix which is a zero matrix of M1 rows and N−K−M1 columns, a C matrix of N−K−M1 rows and K+M1 columns, and a D matrix which is an identity matrix of N−K−M1 rows and N−K−M1 columns. The A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing the positions of the elements of 1 of the A matrix and the C matrix for every 36 columns, and is a predetermined table. The present technology can be applied to, for example, data transmission using an LDPC code.
Owner:SONY GROUP CORP
Systems and methods for block-kronecker based low density parity check (LDPC) code with 2 / 3 code rate
An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 2 / 3, a second parity check matrix corresponding to a first exponent matrix comprising 768 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.
Owner:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
Systems and methods for block-kronecker based low density parity check (LDPC) code with 1 / 2 code rate
An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 1 / 2, a second parity check matrix corresponding to a first exponent matrix comprising 1152 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.
Owner:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
Extending low-density parity check (LDPC) codes for Wi-Fi
This disclosure provides methods, components, devices and systems for low-density parity check (LDPC) coding. Some aspects more specifically relate to extending LDPC codewords to produce longer codewords. In some examples, a first wireless device may generate a baseline LDPC code by performing a first lifting on a base matrix, which may produce an LDPC code used for a current Wi-Fi implementation. The first wireless device may then perform a second lifting or a re-lifting (such as a cyclic lifting, a product lifting, a swapping lifting, or a combination thereof) to generate an extended lifted code. This extended lifted code may be an extension of the first LDPC code such that the first LDPC code may be preserved as part of the extended code. Then first wireless device may then transmit the extended LDPC code as an extended or lifted codeword.
Owner:QUALCOMM INC
System and method for low density parity check (LDPC) code with 1 / 2 code rate
ActiveUS20250047308A1Error correction/detection using LDPC codesChecking code calculationsCoding blockAlgorithm
In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 1 / 2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 288 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.
Owner:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
Quasi-cyclic LDPC codes based on generalised quadrangles
InactiveUS20250286565A1Code conversionChecking code calculationsTheoretical computer scienceParity-check matrix
In an aspect, digital communication coding methods (or simply coding methods) are provided, said methods comprising providing families of quasi-cyclic low-density parity check, LDPC, codes each represented by a single equation. Said single equation is derived from a geometry whose nature implies good error correcting properties for each of the LDPC codes and allows quasi-cyclic parity check matrices to be constructed for geometric LDPC codes of exceedingly long length, up to and exceeding four hundred thousand bits. The construction of such check matrices is not possible by any other known method. The LDPC codes have different lengths and different rates and the families of LDPC codes are provided with a guarantee of minimum distance. The geometric and quasi-cyclic properties of the LDPC codes allow low complexity decoding with very low frame error rates. Systems, computing systems and computer programs suitable to perform such coding methods are also provided.
Owner:UNIV POLITECNICA DE CATALUNYA
Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes
PendingUS20250112644A1Checking code calculationsError correction/detection using multiple parity bits
Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
Owner:QUALCOMM INC
Systems and methods for generating optimized combination sets for error correction in data transmission
A non-transitory computer-readable medium, method and system, the system including processing circuitry. The processing circuitry is to generate a first matrix, perform an incident cycle optimization process using the first matrix to generate a modified first matrix, and perform an encoder gate optimization process using the modified first matrix to generate a further modified first matrix. Processing circuitry is then to generate a second matrix including the further modified first matrix as a submatrix of the second matrix, perform the incident cycle optimization process using the second matrix to generate a modified second matrix, and perform the encoder gate optimization process using the further modified first matrix and the modified second matrix to generate a further modified second matrix. Processing circuitry then configures a transmitting device that receives and encodes transmission data the using the further modified first matrix and further modified second matrix, and transmits the encoded transmission data.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Systems and methods for irregular error correction code construction in order of weights
A non-transitory computer-readable medium and related method, including processing circuitry, which performs in-order error correction code construction. The processing circuitry receives a first plurality of matrices. The processing circuitry is to generate a second plurality of matrices based on at least one additive candidate matrix and each respective matrix of the first plurality of matrices. The processing circuitry then generates a third plurality of matrices based on at least one additive test matrix and each respective matrix of the second plurality of matrices. Each respective weight indicative of respective extensibility for each matrix of the second plurality of matrices is determined based on the third plurality of matrices. At least one matrix from the second plurality of matrices is then selected by processing circuitry based on the determined weights. The processing circuitry then generates an error correction code based on one of the at least one selected matrix.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Lifting schemes for low-density parity-check codes
PendingUS20250055481A1Error correction/detection using LDPC codesCode conversionTelecommunicationsLeast significant bit
Methods, systems, and devices for wireless communications are described. A wireless communication device may implement a low-density parity-check (LDPC) code to encode and / or decode bits of a signal. The LDPC code may be defined by a base graph and a lifting scheme. The base graph may include check nodes and variable nodes. The lifting scheme may define a quantity of copies of the base graph used to generate the LDPC code and respective cyclic shifts associated with connected variable nodes and check nodes. The respective cycle shifts may be defined such that one or more cycles associated with a minimum length of the LDPC code are associated with a restriction on second degree variable nodes, nodes associated with least significant bits, or a combination thereof. Additionally, or alternatively, the respective cycle shifts may be defined such that a weighted girth of the LDPC code satisfies a threshold.
Owner:QUALCOMM INC
Quasi-cyclic LDPC coding and decoding method and apparatus, and LDPC coder and decoder
ActiveUS12218686B2Checking code calculationsError correction/detection using multiple parity bitsDecoding methodsData sequences
A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S202), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and / or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S204).
Owner:ZTE CORP
Coding method, decoding method and device
The invention discloses a coding method, a decoding method and a device, which are used for supporting an IEEE (Institute of Electrical and Electronic Engineers) 802.11 ax next generation Wi-Fi (Wireless Fidelity) protocol (such as 802.11 be, Wi-Fi7 or EHT), or an IEEE 802.11 be next generation Wi-Fi protocol (such as 802.11 bn, Wi-Fi 8 or UHR), or Wi-Fi AI (Wireless Fidelity), or MMW (Millimeter Wave), or UWB (Ultra Wideband) or perception and the like. The method comprises the following steps: a first communication device obtains an information bit sequence, performs LDPC coding on the information bit sequence based on a check matrix, obtains a coded sequence, and outputs the sequence. The length of the sequence is N1, N1 is n times of 1944, and n is an integer greater than or equal to 2. And after obtaining the to-be-decoded information, the second communication device performs LDPC decoding in combination with the check matrix to obtain an information bit sequence. The method can improve the decoding performance.
Owner:HUAWEI TECH CO LTD
Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes
ActiveUS12191883B2Checking code calculationsError correction/detection using multiple parity bitsAlgorithmParity-check matrix
Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
Owner:QUALCOMM INC
Encoder and encoding method
An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.
Owner:SAMSUNG ELECTRONICS CO LTD
Data mapping method and related device
The embodiment of the invention discloses a data mapping method and a related device, which can obtain higher coding gain while keeping good compatibility, and can ensure the resistance to channel burst errors at the same time. Specifically, a first data stream encoded by an outer code is obtained. Afterwards, the first data stream is subjected to inner code coding to obtain a second data stream, the second data stream comprises L code words subjected to second FEC coding, L is an integral multiple of 8, each code word comprises n bits, and n is an odd number larger than 1. Furthermore, the L code words are interleaved and mapped to obtain n * L / 8 DP-16QAM symbols, any one of an X polarization direction I-path component, an X polarization direction Q-path component, a Y polarization direction I-path component and a Y polarization direction Q-path component of each DP-16QAM symbol is obtained by mapping two bits in the L code words, and each DP-16QAM symbol is obtained by mapping eight bits from eight code words.
Owner:HUAWEI TECH CO LTD
Concatenated code encoding method, concatenated code decoding method, and communication apparatus
ActiveUS12476736B2Error preventionChecking code calculationsParallel computingTheoretical computer science
This application provides example concatenated code encoding and decoding methods. In one example method, polar code encoding is performed on a to-be-encoded message bit sequence based on a frozen bit set and a message bit set that are of a first polar code, to obtain a first encoded code word whose length is N_o. The first encoded code word is interleaved to obtain a second encoded code word, and optimized low-density parity-check (LDPC) code encoding is performed on the second encoded code word to obtain a concatenated code word. Interleaving includes both outer interleaving and inner interleaving. The concatenated code word is then outputted.
Owner:HUAWEI TECH CO LTD
Encoding method, decoding method, and apparatus
The method includes: A transmitter obtains a first bit sequence, and then performs LDPC encoding on the first bit sequence based on a check matrix, to obtain a second bit sequence. Correspondingly, a receiver receives the second bit sequence, and then performs LDPC decoding on the second bit sequence based on the check matrix, to obtain K information bits. The first bit sequence includes the K information bits, the second bit sequence includes M check bits, and both K and M are positive integers. The check matrix is obtained based on a first base matrix, the first base matrix corresponds to a second base matrix, the second base matrix includes the following elements: 0, 1, and 2.
Owner:HUAWEI TECH CO LTD
System and method for low density parity check (LDPC) code with 5 / 6 code rate
In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 5 / 6 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 96 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.
Owner:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
Single error correct double error detect (SECDED) error coding with burst error detection capability
An integrated circuit (IC) device is disclosed. The IC device includes an error encoder to receive a word of k bits and to encode the word using a G-matrix to generate an encoded word of n bits. The n bits include the k bits and n-k check bits. The G matrix is based on a parity check matrix defining a single error correct, double error detect, and burst error detect (SECDEDBED) code. An error decoder receives the encoded word and applies the parity check matrix to the encoded word. The parity check matrix is configured to generate a syndrome from the encoded word. The syndrome being used to detect a random double bit error, a random single bit error, and a burst error of between two and m bits within m adjacent bits of an m-bit subset of the data word starting from an m-bit boundary of the word of k bits, and where m<n-k.
Owner:RAMBUS INC
Communication method based on LDPC code, and communication apparatus
PCT designated stage expiredWO2025035365A1Error preventionChecking code calculationsComputer networkComputer engineering
Owner:HUAWEI TECH CO LTD
Information processing method and apparatus, and communication device
PendingCN119232327AError preventionError correction/detection using LDPC codesComputer hardwareInformation processing
The invention discloses a coding method, a coding device, communication equipment and a communication system. An input bit sequence is encoded using a low density parity check (LDPC) matrix to obtain an encoded bit sequence for transmission. Wherein the LDPC matrix is obtained based on an expansion factor Z and a basis matrix. The invention also discloses the design of various different structures of the basis matrix. According to the coding method, the coding device, the communication equipment and the communication system, the coding requirements of information bit sequences with various lengths can be met.
Owner:HUAWEI TECH CO LTD
Enhanced punched and low-density parity-check (LDPC) code structure
ActiveCN114520660BChecking code calculationsError correction/detection using multiple parity bitsParallel computingLow-density parity-check code
Certain aspects of this disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structures. A method for wireless communication by a transmitting device is provided. This method generally includes: encoding a set of information bits based on an LDPC code to generate a codeword, the LDPC code being defined by a basic matrix having a first number of variable nodes and a second number of parity nodes; puncturing the codeword according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to generate a punctured codeword; adding at least one additional parity bit to the punctured at least two variable nodes; and transmitting the punctured codeword.
Owner:QUALCOMM INC
Coding method and apparatus
A coding method and apparatus are provided to provide a uniform coding method for ultra short codes. The method is as follows: obtaining, by a transmit end, to-be-coded information bits; performing, by the transmit end, PC-polar coding on the to-be-coded information bits based on first constructor parameters, to obtain a coded bit sequence; and sending the coded bit sequence, where a check equation of the first constructor parameters include a first element representing a check-required information bit position and a second element representing a check bit position, the first element corresponds to a first vector in a generator matrix for PC-polar codes, the second element corresponds to a second vector in the generator matrix, and if a first Hamming weight of the first vector is the same as a second Hamming weight of the second vector, a third Hamming weight of an addition modulo 2 vector is greater than the first Hamming weight and greater than the second Hamming weight, or if the first Hamming weight is different from the second Hamming weight, the third Hamming weight is greater than a smaller one of the first Hamming weight and the second Hamming weight.
Owner:HUAWEI TECH CO LTD
Transmission / reception system and transmission / reception method
To secure favorable communication quality in data transmission using an LDPC code.SOLUTION: In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, to a case of performing LDPC code-based data transmission and the like.SELECTED DRAWING: Figure 185
Owner:SONY GROUP CORP
Construction method and processing device, storage medium, and coding and decoding method
A method for constructing a permutation matrix or a check matrix, a processing device, a storage medium and a coding method. The method for constructing the permutation matrix comprises: obtaining a base matrix for the permutation matrix; and performing lifting on the base matrix to obtain the permutation matrix. The lifting on the base matrix to obtain the permutation matrix comprises: obtaining a modulus graph of the base matrix, obtaining each macro ring in the modulus graph, and for each macro ring in the modulus graph, determining the size of a short ring corresponding to the macro ring in a Tanner graph of a check matrix corresponding to the permutation matrix from an equivalent cycle value ECS of the macro ring, and determining whether at least one cycle value in the macro ring needs to be set according to the size of the short ring. The method can more efficiently obtain a required permutation matrix.
Owner:BEIJING ESWIN COMPUTING TECH CO LTD +1
Magic state factory constructions for producing CCZ and T states
ActiveUS12242927B2Quantum computersReliability increasing modificationsParticle physicsQuantum electrodynamics
Methods, systems, and apparatus for producing CCZ states and T states. In one aspect, a method for transforming a CCZ state into three T states includes obtaining a first target qubit, a second target qubit and a third target qubit in a CCZ state; performing a X−1 / 2 gate on the third target qubit; performing an X gate on the first target qubit and the second target qubit using the third target qubit as a control; performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control; performing a Z−1 / 4 gate on the third target qubit; and performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control to obtain the three T states.
Owner:GOOGLE LLC
Transmission device, transmission method, reception device, and reception method
The present technology relates to a transmission device, a transmission method, a reception device, and a reception method capable of ensuring good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 1224 or 1152 bits and the coding rate r of 144 / 1224 or 144 / 1152. The parity check matrix includes an A matrix of M1 rows and K columns represented by a predetermined value M1 and an information length K = N × r of the LDPC code, a B matrix of a staircase structure of M1 rows and M1 columns, a Z matrix which is a zero matrix of M1 rows and N - K - M1 columns, a C matrix of N - K - M1 rows and K + M1 columns, and a D matrix which is an identity matrix of N - K - M1 rows and N - K - M1 columns. The A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing the positions of the elements of 1 of the A matrix and the C matrix for every 36 columns, and is a predetermined table. The present technology can be applied to, for example, data transmission using an LDPC code.
Owner:SONY GROUP CORP
Transmission / reception system and transmission / reception method
To secure favorable communication quality in data transmission using an LDPC code.SOLUTION: In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, to a case of performing LDPC code-based data transmission and the like.SELECTED DRAWING: Figure 172
Owner:SONY GROUP CORP