LDPC design for high rate, high parallelism, and low error floor

Abstract

A method of data encoding is disclosed. An encoder receives a set of information bits and performs a lifted LDPC encoding operation on the information bits to produce a codeword. The encoder then punctures all lifted bits of the codeword that correspond to one or more punctured base bits of a base LDPC code used for the LDPC encoding operation. The base LDPC code has no multiple edges, and the one or more punctured base bits are those that correspond with one or more punctured base nodes, respectively, of the base LDPC code. For some embodiments, the one or more punctured base nodes correspond to one or more degree 2 variable nodes.

Description

RELATED APPLICATIONS[0001]This application claims priority under 35 U.S.C. §119(e) of the co-pending and commonly-owned U.S. Provisional Patent Application No. 61 / 764,476, titled “LDPC Design for High Rate, High Parallelism, Low Error Floor, and Simple Encoding,” filed Feb. 13, 2013, which is hereby incorporated by reference in its entirety.TECHNICAL FIELD[0002]The present embodiments relate generally to communications and data storage systems, and specifically to communications and data storage systems that use LDPC codes.BACKGROUND OF RELATED ART[0003]Many communications systems use error-correcting codes. Specifically, error correcting codes compensate for the intrinsic unreliability of information transfer in these systems by introducing redundancy into the data stream. Low density parity check (LDPC) codes are a particular type of error correcting codes which use an iterative coding system. LDPC codes can be represented by bipartite graphs (often referred to as “Tanner graphs”)...

AI Technical Summary

Benefits of technology

The patent describes a device and method for encoding and decoding low density parity check (LDPC) codewords. The invention adds a punctured variable node to the base graph design, which increases the number of checks in the code without changing the rate parameters. Punctered bits correspond with punctured base variable nodes which eliminates multiple edges between node pairs in the base graph. This simplifies the hardware and memory operations and improves error correction performance of LDPC coding system. The punctured nodes can be a highest-degree variable node or a degree two variable node used to split a check node. The elimination process also reduces the complexity of the read and write operations in memory.

Problems solved by technology

Having a based variable node and a base check node connected by two or more edges is generally undesirable for parallel hardware implementation purposes.

For example, such double edges may result in multiple concurrent read and write operations to the same memory locations, which in turn may create data coherency problems.

Pipelining of parallel message updates can be adversely affected by the presence of double edges.

Such an elimination process is likely to introduce double or multiple edges into the representation which is undesirable for parallel implementation of decoding.

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