LDPC design for high rate, high parallelism, and low error floor

Abstract

A method of data encoding is disclosed. An encoder receives a set of information bits and performs a lifted LDPC encoding operation on the information bits to produce a codeword. The encoder then punctures all lifted bits of the codeword that correspond to one or more punctured base bits of a base LDPC code used for the LDPC encoding operation. The base LDPC code has no multiple edges, and the one or more punctured base bits are those that correspond with one or more punctured base nodes, respectively, of the base LDPC code. For some embodiments, the one or more punctured base nodes correspond to one or more degree 2 variable nodes.

Description

RELATED APPLICATIONS[0001]This application claims priority under 35 U.S.C. §119(e) of the co-pending and commonly-owned U.S. Provisional Patent Application No. 61 / 764,476, titled “LDPC Design for High Rate, High Parallelism, Low Error Floor, and Simple Encoding,” filed Feb. 13, 2013, which is hereby incorporated by reference in its entirety.TECHNICAL FIELD[0002]The present embodiments relate generally to communications and data storage systems, and specifically to communications and data storage systems that use LDPC codes.BACKGROUND OF RELATED ART[0003]Many communications systems use error-correcting codes. Specifically, error correcting codes compensate for the intrinsic unreliability of information transfer in these systems by introducing redundancy into the data stream. Low density parity check (LDPC) codes are a particular type of error correcting codes which use an iterative coding system. LDPC codes can be represented by bipartite graphs (often referred to as “Tanner graphs”)...

AI Technical Summary

Benefits of technology

[0008]A device and method of operation are disclosed that may aid in the encoding and / or decoding of low density parity check (LDPC) codewords. It is noted that the addition of a punctured variable node (also known as a state variable node) into the base graph design can effectively increase the number of checks in the graph by one without changing the rate parameters (k and n) of the code. For some embodiments, an encoder may receive a set of information bits and perform an LDPC encoding operation on the information bits to produce a codeword. The device may then puncture a set of lifted codeword bits corresponding to one or more base variable nodes based on a lifted LDPC code used for the LDPC encoding operation, wherein the punctured bits correspond with one or more punctured base variable nodes, respectively, of the base LDPC graph. It is understood that punctured variable nodes in the graphical description of the code can be eliminated from the description by a check node combining process operating on the lifted parity check matrix. Therefore, at least one of the one or more punctured base nodes is understood to eliminate multiple edges between node pairs of the base graph for the lifted LDPC code when the elimination of the punctured variable node results in multiple edges.

[0009]For some embodiments, the one or more punctured nodes may include a variable node having a degree equal to, or one less than, a number of check nodes of the LDPC code. For example, at least one of the punctured nodes may be a highest-degree variable node of the LDPC code. In such an embodiment, the high degree of the node is often desirable for enhancing the performance of the code. For example, the puncturing allows higher variable node degree while avoiding double edges in the base graph. The presence of the punctured variable node in the graph effectively increases the number of check nodes that would otherwise be present in a base graph of a code of the same size and rate. For other embodiments, at least one of the punctured nodes may be a degree two variable node used to split a check node that would otherwise be connected to a variable node of the LDPC code by two or more edges. A punctured degree two node can be eliminated from the description by adding the two parity checks to which it is connected. The at least one punctured base degree two variable node may thus be used to eliminate double edges in the base LDPC graph. Similarly, a high degree punctured node may be eliminated from a parity check matrix representation by an elimination process summing constraint nodes to effectively reduce the degree of the variable node to one. A degree one punctured node can be eliminated from the graph along with its neighboring check node without altering the code. Such an elimination process is likely to introduce double or multiple edges into the representation which is undesirable for parallel implementation of decoding.

[0010]By eliminating or reducing double (or multiple) edges from the base LDPC graph, the present embodiments may reduce the complexity of the hardware that performs LDPC decoding operations in parallel, thereby increasing the processing efficiency of LDPC decoders that implement lifted LDPC codes. This further simplifies read and / or write operations performed in memory, and ensures that the read and write operations are not performed out of order. By allowing larger variable node degrees, while avoiding double edges, the present embodiments may also improve the error correcting performance of the LDPC coding system.

Problems solved by technology

Having a based variable node and a base check node connected by two or more edges is generally undesirable for parallel hardware implementation purposes.

For example, such double edges may result in multiple concurrent read and write operations to the same memory locations, which in turn may create data coherency problems.

Pipelining of parallel message updates can be adversely affected by the presence of double edges.

Such an elimination process is likely to introduce double or multiple edges into the representation which is undesirable for parallel implementation of decoding.

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