1035results about "Error correction/detection using multiple parity bits" patented technology

The invention discloses an LDPC (Low Density Parity Check) coding and decoding system and method for high-density tape storage, and the system comprises a main controller which is used for scheduling coding and decoding mode switching and module cooperative control; the storage and calculation integrated array is used for executing zero-carrying storage calculation; the ping-pong buffer framework is composed of an input buffer module Buffer A and an output buffer module Buffer B; the dynamic code length extension module is used for reconstructing a cascade link; the preprocessing module is used for converting the noisy code word into a log likelihood ratio (LLR) value; the hard decision module is used for converting the VN message into user data; the main controller is connected with all the modules through a control bus, and the dynamic code length extension module controls the power state and interconnection topology of the sub-arrays. According to the LDPC coding and decoding system and method based on the storage and calculation integrated array, zero-carrying calculation is achieved, iterative decoding is accelerated through a ping-pong buffer architecture, and the code length is flexibly configured through the dynamic code length extension module, the coding and decoding efficiency of high-density tape storage is improved, delay and energy consumption are reduced, meanwhile, multi-code-length self-adaption is supported, and high performance and flexibility are considered.

In an aspect, digital communication coding methods (or simply coding methods) are provided, said methods comprising providing families of quasi-cyclic low-density parity check, LDPC, codes each represented by a single equation. Said single equation is derived from a geometry whose nature implies good error correcting properties for each of the LDPC codes and allows quasi-cyclic parity check matrices to be constructed for geometric LDPC codes of exceedingly long length, up to and exceeding four hundred thousand bits. The construction of such check matrices is not possible by any other known method. The LDPC codes have different lengths and different rates and the families of LDPC codes are provided with a guarantee of minimum distance. The geometric and quasi-cyclic properties of the LDPC codes allow low complexity decoding with very low frame error rates. Systems, computing systems and computer programs suitable to perform such coding methods are also provided.

The invention discloses a data error correction method and device based on low-density parity check, equipment and a medium, and relates to the technical field of data error correction, and the method comprises the steps: reading data to be corrected from a data memory, and carrying out the pre-verification of the data to be corrected and a verification matrix of a preset low-density parity check code, and obtaining a pre-verification result; based on the pre-verification result, determining a first error position set in a code word position set; performing bit flipping operation on code words indicated by the first error position set to complete pre-error correction; and inputting the code word after pre-error correction processing into a low density parity check decoder for decoding, outputting data after error correction, pre-detecting the error position of the code word, and performing bit flipping on the code word at the error position, thereby reducing the number of error bits entering LDPC decoding, and improving the decoding efficiency. Therefore, the number of error bits does not exceed the decoding capability limit of hard decoding, the probability that the system enters soft decoding is reduced, and the decoding throughput rate of the system is ensured.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G systems and 6G systems. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality (XR) service or a low-delay service.

The invention discloses an LDPC code coding method. The method comprises the following steps: acquiring an information bit sequence; performing low density parity check (LDPC) coding on the information bit sequence according to a check matrix to obtain a coded bit sequence; wherein the check matrix is determined by a basis matrix, and the basis matrix comprises a basic sub-matrix; the basic sub-matrix is formed by splicing at least two basic unit blocks with circulation or translation. According to the invention, compared with the condition that the shift value Shifting Value of the existing 5G new air interface NR matrix is a random search result and lacks fixed algebraic structure guidance, the basis matrix with the cyclic block or translation block structure designed by the invention can have fixed algebraic structure guidance, the problem that the LDPC lacks practical code design is solved, and the LDPC performance is improved. And the index matrix of the free is difficult to find through random search.

The application provides a polar code soft input soft output decoding method, a decoding device and a communication device; the decoding method comprises the following steps: (S1) performing fast serial cancellation list decoding under dynamic frozen bit constraint for all special nodes constituting a polar code; the types of the special nodes comprise rate zero, rate one, repetition and single parity check; (S2) calculating the approximation of the sum of the posterior probabilities of the legal code words not accessed under each special node after decoding; (S3) using the approximation of the code book probability obtained in the step (S2) to calculate the bit level soft information of the output polar code. The low-latency polar code soft input soft output decoding method provided by the application improves the parallelism by realizing fast soft output decoding based on the Rate0, Rate1, REP and SPC nodes, and significantly reduces the decoding latency without losing the soft output precision compared with the SO-SCL decoding algorithm.

The invention discloses a channel coding and decoding read-write parallel scheduling method, which comprises the following steps of: inputting a base graph matrix, and sequentially arranging to obtain a read variable node sequence and a write variable node sequence of each row according to a column sequence number of a non-zero element in each row of the base graph matrix; constructing a conflict graph according to the base graph matrix; selecting the vertex with the highest saturation from the uncolored vertexes, selecting the minimum available color, and coloring the vertex; coloring each vertex, grouping the vertexes, dividing the vertexes with the same coloring color sequence number into the same group to obtain a vertex group set, and distributing a processing unit for each vertex group; constructing an operation sequence of each processing unit; conflict variable nodes of operation are eliminated; storing a reading variable node sequence and a writing variable node sequence of each operation of each processing unit; the invention further discloses a channel coding and decoding read-write parallel scheduling device. According to the technical scheme, the conflict rate can be effectively reduced, and the method can be suitable for various base graphs.

The invention discloses a coding method and system based on matrix optimization and a storage and calculation integrated accelerator and a medium, and relates to the technical field of communication, and the method comprises the steps: constructing the storage and calculation integrated accelerator which comprises an input buffer area, a dynamic reconstruction storage and calculation array and a result processing module; m * n sub-matrixes obtained by splitting the check matrix H are respectively stored in corresponding storage and calculation integrated cores of the dynamic reconstruction storage and calculation array; the total code c is divided into n segments through an input buffer area and then multiply-accumulate with the corresponding column of sub-matrixes, a calculation result of the dynamic reconstruction storage array is input into a result processing module for result processing, and a final coding result is obtained; according to the coding method, the coding system and the medium, the dynamic adaptability and the calculation efficiency are broken through, and a high-reliability and low-delay LDPC coding solution is provided for tape storage.

This invention discloses a low-complexity decoding method for LDPC-Hadamard codes based on a prototype diagram, belonging to the field of digital signal processing. The implementation method is as follows: information bits are LDPC encoded, and then the constraint relationship of the check nodes of the LDPC code is encoded into Hadamard code to obtain the prototype diagram of the LDPC-Hadamard code; the encoded codewords are transmitted and received through a channel, and the PVN and HCN nodes are initialized with the received information; Hadamard decoding is performed using a symbol-by-symbol maximum a posteriori probability decoding algorithm, and DFHT approximation is used to reduce decoding complexity; the decoded information is transmitted to the PVN nodes; the updated HCN node information is summed with the information from the previous iteration, and the summation result is used to determine the decoding; a decoding decision is made on the PVN information, and decoding is performed. This invention combines LDPC encoding, Hadamard encoding, and Max-Log approximation calculation methods to reduce decoding complexity and enhance the stability and reliability of the communication system.

The invention discloses a soft decoding method and device, a medium and a product, and relates to the technical field of error correction coding, and the method is applied to a low-density parity check code, and comprises the steps: obtaining a target low-density parity check code with an information node and a check node containing an erasure bit; and allocating a preset non-zero log-likelihood ratio to the erasure bit on the check node, and executing first soft decoding. And if the first soft decoding fails, judging whether to carry out second soft decoding or not based on the weight of the syndrome generated by the first soft decoding and the number of the erasure bits on the information node. If it is judged that the second soft decoding needs to be carried out, a preset non-zero log likelihood ratio is distributed to the erasure bit located on the information node, and the second soft decoding is carried out. According to the method and the device, the erasing bits on different nodes are conditionally processed in stages, so that the success rate and the efficiency of decoding are effectively improved.

The invention discloses a layered LDPC (Low Density Parity Check Code) decoding method based on syndrome feedback self-adaption, and aims to solve the problem of poor decoding performance caused by fixed correction factors and poor adaptability to different check matrixes and channel conditions in the existing LDPC decoding algorithm. The method comprises the following steps of: firstly, dividing rows of a check matrix into a plurality of independent layers by adopting a hierarchical scheduling architecture so as to accelerate propagation and convergence of decoding information; secondly, in each iteration process of hierarchical decoding, a self-adaptive mechanism based on syndrome feedback is used, and a core offset factor beta in an offset minimum sum algorithm is adjusted in real time; the mechanism intelligently increases or decreases the offset factor by diagnosing the current decoding state (i.e., the number of unsatisfied check equations) to help the decoding process jump out of local optimum and stably converge. A simulation result shows that compared with a traditional offset minimum sum algorithm, the decoding performance is effectively improved and the bit error rate is reduced on the premise that the complexity is not obviously increased, and particularly, the performance gain is obvious in a medium-high signal-to-noise ratio region, and the robustness is higher.

The invention provides an LDPC (Low Density Parity Check) optimization method based on dynamic parameter adaptive coding and a Tanner graph neural network. The method comprises the following steps: acquiring a data set through a channel sensing module; the data set comprises channel state information, bit error rate statistics and QoS (Quality of Service) demand information; the collected data set is preprocessed; dividing the preprocessed data set according to a preset proportion; constructing an LSTM (Long Short Term Memory) prediction model; training and optimizing the LSTM prediction model by using the training set based on the loss function, and storing an optimal model; inputting the test set into the optimal model to predict the coding parameters of the channel transmission to obtain a prediction result of the adaptive coding parameters of the channel transmission; the method comprises the following steps: establishing an LDPC encoder and a Tanner-GNN decoder; building a joint optimization controller; the joint optimization controller is used for dynamically adjusting coding parameters through the LSTM prediction model and receiving the bit error rate BER counted by the Tanner-GNN decoder, the technical limitation of traditional coding and decoding separation optimization is broken through, and the performance of the LDPC code in a complex channel environment is remarkably improved.

A method for verifying a low-density parity-check (LDPC) unit capable of being applied in a memory system can include receiving original data corresponding to a memory device, encoding the original data by the LDPC unit to be verified, injecting errors into the encoded original data by a data pattern for generating verifying data, and verifying a soft decode capability of the LDPC unit by utilizing the verifying data. The data pattern can include the errors generated by threshold voltage (Vth) distributions interlaced between two neighboring logic states of 2n logic states of the memory device. The method and system can provide an error injection to accurately and efficiently verify a LDPC soft decode capability of the LDPC unit, decrease errors, increase error correction accuracy and efficiency, more accurately model actual threshold voltage (Vth) distributions, increase flexibility, increase speed, increase performance, and reduce firmware overhead.

Provided are an encoding method and apparatus, a decoding method and apparatus, and a storage medium. The encoding method comprises: determining a parity check matrix, wherein the dimension of the parity check matrix is determined on the basis of the dimension of a binary extended matrix, the binary extended matrix is obtained by hashing an exponential matrix on the basis of a lifting factor, and the lifting factor is determined on the basis of a binary fundamental matrix, an information bit sequence, and the order of a non-binary low density parity check code (NB-LDPC); and performing NB-LDPC encoding on the information bit sequence on the basis of the parity check matrix or a generator matrix corresponding to the parity check matrix, to obtain an encoding sequence.

The invention relates to an adaptive Layered Threshold Min-Sum (ALTMS) decoding method for an LDPC (Low Density Parity Check Code) code, which is characterized in that the adaptive Layered Threshold Min-Sum (Amplitude Layered Threshold Min-Sum) decoding method is provided; according to the method, the advantages of a threshold normalized minimum sum decoding algorithm and a threshold offset minimum sum decoding algorithm are combined, correction factors under different iterations are dynamically adjusted, and check node information updating in each iteration is adapted, so that the algorithm convergence speed and the decoding performance are effectively improved. Simulation results show that compared with three threshold minimum sum decoding algorithms under hierarchical scheduling, the ALTMS decoding algorithm provided by the invention realizes certain performance gain, and compared with a fixed parameter minimum sum decoding algorithm, the ALTMS decoding algorithm provided by the invention has better error correction performance.

This disclosure provides methods, components, devices, and systems for ultra-high reliability (UHR) signaling design. Some aspects more specifically relate to an access point (AP) transmitting a frame including a user info field to a wireless station (STA), where the user info field supports UHR parameters. The user info field may include a subfield indicating a coding scheme for communications, where the subfield includes at least two bits to support at least three coding scheme options. Additionally, or alternatively, the AP may transmit a trigger frame indicating for one or more STAs to communicate via distributed resource units (RUs). The AP may arrange the user info fields in the trigger frame to implicitly indicate respective global cyclic shift delay (CSD) indexes to the STAs. A STA receiving the trigger frame may determine a global CSD index corresponding to the STA according to the order of the user info fields.

The present application discloses an encoding method for low-density parity-check (LDPC) codes. The method comprises: acquiring an information bit sequence; and on the basis of a check matrix, performing LDPC encoding on the information bit sequence to obtain an encoded bit sequence, wherein the check matrix is determined by a base matrix, the base matrix comprises a fundamental sub-matrix, and the fundamental sub-matrix is formed by concatenating at least two basic unit blocks with cyclic or translational properties. Compared with existing 5G new radio (NR) matrices of which shifting values are all obtained by random search without guidance from a fixed algebraic structure, the base matrix having cyclic block structures or translational block structures designed in the present application can be guided by a fixed algebraic structure, thereby solving the technical problems of the lack of practical code design for LDPC and the difficulty in finding a cycle-free exponent matrix by means of random search.

The invention provides a communication method and a related device, and the method comprises the steps: determining a redundancy version (RV) corresponding to an encoded bit sequence, the encoded bit sequence comprising a plurality of bit segments, each of the plurality of bit segments comprising a system bit, and an initial position corresponding to the RV being located in one of the plurality of bit segments; and performing data transmission based on the RV. According to the embodiment of the invention, the initial position corresponding to the RV is located in one of the plurality of bit segments, and each bit segment corresponds to a group of system bits. Data transmission based on each RV is associated with a group of system bits, so that the data transmission efficiency and the data retransmission performance can be ensured.

Dynamic frozen polar codes for probabilistic shaping are described. An apparatus is configured to map transmission bits to an EC-polar code. The transmission bits include first data bits, second data bits, EC bits, and shaping bits. The first data bits correspond to frozen bit locations of the EC-polar code, the shaping bits correspond to information bit locations of the EC-polar code, and the EC bits and the second bits both correspond to remaining locations of the EC-polar code. The apparatus is configured to shape the transmission bits to shaped transmission bits based on the mapping, the EC-polar code, and an addition operation on the transmission bits including the EC bits and the second data bits. The apparatus is configured to transmit, to a receiver network device, the shaped transmission bits.

In some implementations, an apparatus may receive a first copy of payload data and a corresponding first cyclic redundancy check (CRC) code, and a second copy of the payload data and a corresponding second CRC code. Each of the first copy and the second copy may be encrypted with an identical keystream. The apparatus may decrypt, using the keystream, the first copy to obtain first decrypted data and the second copy to obtain second decrypted data, append the first CRC code to the first decrypted data to form first data, append the second CRC code to the second decrypted data to form second data, determine one or more bit positions, at each of which the first data and the second data have bit values different from each other, and correct, based on the one or more bit positions, an error contained in the first data.

The invention relates to an LDPC (Low Density Parity Check) decoding method and system based on a dynamic scale factor, belongs to the technical field of circuit design, and solves the problem of low decoding performance caused by adopting a fixed value to correct deviation in the prior art. Comprising the following steps: S1, receiving to-be-decoded information, initializing posterior probability information and check node information, and iteratively executing S2-S4 until a termination condition is met; s2, acquiring a decoding decision value according to the check matrix and the hard decision value of the posterior probability information, identifying whether a termination condition is met or not according to the decoding decision value and the number of iterations, if yes, outputting a decoding result, and otherwise, entering S3; s3, updating variable node information according to posterior probability information and check node information of the last iteration; calculating a dynamic scale factor, and updating check node information according to the dynamic scale factor and the updated variable node information; and S4, updating the posterior probability information according to the updated check node information to obtain the posterior probability information of the current iteration, and returning to S2. And the decoding performance is improved.

Disclosed is a method comprising, by a transmitter apparatus, partitioning (901) an input data stream to obtain a bit stream X1 and a bit stream X2; subjecting (902) the bit stream X2 to encoding by LDPC encoders, to obtain X2 parity bits, and X2 information bits; applying (903) SPC encoding to the X2 parity bits, together with the bit stream X1, to obtain sign bits, wherein the bit stream X1 is used as padding bits; subjecting (904) the sign bits, the padding bits, and the X2 information bits, to an interleaver operation to obtain an interleaver output; subjecting (905) the interleaver output to Gray mapping to form multiple consecutive quadratic amplitude modulation, QAM, symbols; modulating (905) the QAM symbols by quadratic amplitude modulation to obtain a modulated data stream; and transmitting (906) the modulated data stream via a radio access network or optical fibre communication network.

The invention relates to an LDPC (Low Density Parity Check) quantitative hierarchical decoding working method combining an improved dragonfly algorithm with residual degradation, and belongs to the technical field of wireless communication. The method specifically comprises the steps that firstly, a pilot signal is sent by a signal source, average least square estimation of channel state information is obtained through analysis based on representation of a received signal in a time domain and a frequency domain, noise power is determined, then the pilot signal is introduced into an improved dragonfly algorithm, quantization parameter set training is carried out, and the improved dragonfly algorithm reads a sample signal to obtain the channel state information. And finally, applying the self-adaptive quantization parameter set obtained by training to a residual degradation decoding algorithm, and if a decoding result does not meet a verification equation, carrying out next iteration. The performance of the residual degradation decoding algorithm is superior to that of the DLNMS, hardware resources are saved, the decoding performance of layered quantization is improved, the decoding time is shortened, and therefore the decoding speed is increased.

The invention relates to an LDPC (Low Density Parity Check) decoder oriented to a CCSDS (Consultative Committee for Space Data System) standard and a decoding method thereof, relates to the technical field of satellite communication and channel coding, and aims to solve the technical problems of insufficient parallelism and low resource utilization rate of a satellite communication LDPC decoder in the prior art. The LDPC decoder for the CCSDS standard comprises a frame input module, a control module, an initial probability storage module, a check node calculation module, a variable node calculation module and a frame output module. The LDPC decoder facing the CCSDS standard and the decoding method thereof are suitable for efficient decoding of long-frame data in satellite communication, dynamic block storage architecture, hybrid iterative decoding algorithm and configurable control module collaborative design, balance of decoding algorithm performance and complexity is achieved through storage design optimization, the algorithm flexibility is improved through a configurable strategy, and the decoding efficiency is improved. And the contradiction between the efficiency and resources of long-frame LDPC decoding in satellite communication is systematically solved.

The invention discloses a QC-LDPC check matrix construction method and device for NAND, equipment and a medium, and relates to the technical field of channel coding, and the method comprises the steps: firstly generating an initial check matrix without a four-ring structure; based on the row weight distribution characteristics of the initial matrix, adjusting non-zero item arrangement to generate a middle check matrix with uniform row weight; and finally, traversing non-zero items of the intermediate matrix column by column and row by row, and minimizing the number of six rings by adjusting a shift value to obtain a target check matrix. According to the method, by optimizing the ring structure and row redistribution of the check matrix in stages, the influence of four rings and six rings on the decoding performance is remarkably reduced, so that the data error correction capability of the NAND flash memory is improved, and the decoding time delay is reduced.

A method for error correction includes reading, by a memory controller, a first-level codeword from a memory device, the first-level codeword having user data and first-level parity data. The method includes decoding, by the memory controller responsive to determining the first-level codeword contains errors, the first-level codeword using a first-level low-density parity-check (LDPC) decoder employing a first-level H matrix having a portion with reduced column weights to reduce an average row weight for the first-level H matrix. Responsive to the first-level LDPC decoder failing to correct the errors in the first-level codeword, the memory controller decodes a second-level codeword using a second-level LDPC decoder employing a second-level H matrix that includes a portion with increased column weights to increase an average row weight of a second-level of the second-level H matrix. The second-level codeword having the user data, the first-level parity data and second-level parity data.

According to the communication method and the communication device based on the LDPC code, coding or decoding can be carried out based on an LDPC check matrix, and the LDPC check matrix is determined based on an LDPC basis matrix, a lifting value Zc, a translation value corresponding to each element 1 in the basis matrix and the number k of the translation values corresponding to each element 1. K is an integer greater than or equal to 1, k corresponding to at least one element 1 in the basis matrix is an integer greater than 1, Zc is an integer greater than 1, Zc and k translation values of each element 1 are used for indicating that the corresponding element 1 is replaced by k cyclic shift matrixes of Zc * Zc, the cyclic shift matrixes are obtained by performing cyclic shift on a unit matrix of Zc * Zc, and k is an integer greater than 1. The k translation values are cyclic shift times corresponding to the k cyclic shift matrixes respectively. According to the method, the decoding performance of the LDPC code can be improved.

The present application provides a coding method, a decoding method, and a communication apparatus. In the method, a check matrix used for coding first information comprises a plurality of submatrices, and each submatrix is a zero matrix or a non-zero matrix having both row and column weights of 1. Therefore, each submatrix is an orthogonal matrix, such that parallel decoding and low decoding complexity can be achieved, and the communication delay is reduced, thereby improving the communication efficiency.