599results about "Error correction/detection using multiple parity bits" patented technology

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G systems and 6G systems. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality (XR) service or a low-delay service.

The invention discloses a channel coding and decoding read-write parallel scheduling method, which comprises the following steps of: inputting a base graph matrix, and sequentially arranging to obtain a read variable node sequence and a write variable node sequence of each row according to a column sequence number of a non-zero element in each row of the base graph matrix; constructing a conflict graph according to the base graph matrix; selecting the vertex with the highest saturation from the uncolored vertexes, selecting the minimum available color, and coloring the vertex; coloring each vertex, grouping the vertexes, dividing the vertexes with the same coloring color sequence number into the same group to obtain a vertex group set, and distributing a processing unit for each vertex group; constructing an operation sequence of each processing unit; conflict variable nodes of operation are eliminated; storing a reading variable node sequence and a writing variable node sequence of each operation of each processing unit; the invention further discloses a channel coding and decoding read-write parallel scheduling device. According to the technical scheme, the conflict rate can be effectively reduced, and the method can be suitable for various base graphs.

The invention provides an LDPC (Low Density Parity Check) optimization method based on dynamic parameter adaptive coding and a Tanner graph neural network. The method comprises the following steps: acquiring a data set through a channel sensing module; the data set comprises channel state information, bit error rate statistics and QoS (Quality of Service) demand information; the collected data set is preprocessed; dividing the preprocessed data set according to a preset proportion; constructing an LSTM (Long Short Term Memory) prediction model; training and optimizing the LSTM prediction model by using the training set based on the loss function, and storing an optimal model; inputting the test set into the optimal model to predict the coding parameters of the channel transmission to obtain a prediction result of the adaptive coding parameters of the channel transmission; the method comprises the following steps: establishing an LDPC encoder and a Tanner-GNN decoder; building a joint optimization controller; the joint optimization controller is used for dynamically adjusting coding parameters through the LSTM prediction model and receiving the bit error rate BER counted by the Tanner-GNN decoder, the technical limitation of traditional coding and decoding separation optimization is broken through, and the performance of the LDPC code in a complex channel environment is remarkably improved.

A method for verifying a low-density parity-check (LDPC) unit capable of being applied in a memory system can include receiving original data corresponding to a memory device, encoding the original data by the LDPC unit to be verified, injecting errors into the encoded original data by a data pattern for generating verifying data, and verifying a soft decode capability of the LDPC unit by utilizing the verifying data. The data pattern can include the errors generated by threshold voltage (Vth) distributions interlaced between two neighboring logic states of 2n logic states of the memory device. The method and system can provide an error injection to accurately and efficiently verify a LDPC soft decode capability of the LDPC unit, decrease errors, increase error correction accuracy and efficiency, more accurately model actual threshold voltage (Vth) distributions, increase flexibility, increase speed, increase performance, and reduce firmware overhead.

The invention relates to an adaptive Layered Threshold Min-Sum (ALTMS) decoding method for an LDPC (Low Density Parity Check Code) code, which is characterized in that the adaptive Layered Threshold Min-Sum (Amplitude Layered Threshold Min-Sum) decoding method is provided; according to the method, the advantages of a threshold normalized minimum sum decoding algorithm and a threshold offset minimum sum decoding algorithm are combined, correction factors under different iterations are dynamically adjusted, and check node information updating in each iteration is adapted, so that the algorithm convergence speed and the decoding performance are effectively improved. Simulation results show that compared with three threshold minimum sum decoding algorithms under hierarchical scheduling, the ALTMS decoding algorithm provided by the invention realizes certain performance gain, and compared with a fixed parameter minimum sum decoding algorithm, the ALTMS decoding algorithm provided by the invention has better error correction performance.

This disclosure provides methods, components, devices, and systems for ultra-high reliability (UHR) signaling design. Some aspects more specifically relate to an access point (AP) transmitting a frame including a user info field to a wireless station (STA), where the user info field supports UHR parameters. The user info field may include a subfield indicating a coding scheme for communications, where the subfield includes at least two bits to support at least three coding scheme options. Additionally, or alternatively, the AP may transmit a trigger frame indicating for one or more STAs to communicate via distributed resource units (RUs). The AP may arrange the user info fields in the trigger frame to implicitly indicate respective global cyclic shift delay (CSD) indexes to the STAs. A STA receiving the trigger frame may determine a global CSD index corresponding to the STA according to the order of the user info fields.

In some implementations, an apparatus may receive a first copy of payload data and a corresponding first cyclic redundancy check (CRC) code, and a second copy of the payload data and a corresponding second CRC code. Each of the first copy and the second copy may be encrypted with an identical keystream. The apparatus may decrypt, using the keystream, the first copy to obtain first decrypted data and the second copy to obtain second decrypted data, append the first CRC code to the first decrypted data to form first data, append the second CRC code to the second decrypted data to form second data, determine one or more bit positions, at each of which the first data and the second data have bit values different from each other, and correct, based on the one or more bit positions, an error contained in the first data.

A method for error correction includes reading, by a memory controller, a first-level codeword from a memory device, the first-level codeword having user data and first-level parity data. The method includes decoding, by the memory controller responsive to determining the first-level codeword contains errors, the first-level codeword using a first-level low-density parity-check (LDPC) decoder employing a first-level H matrix having a portion with reduced column weights to reduce an average row weight for the first-level H matrix. Responsive to the first-level LDPC decoder failing to correct the errors in the first-level codeword, the memory controller decodes a second-level codeword using a second-level LDPC decoder employing a second-level H matrix that includes a portion with increased column weights to increase an average row weight of a second-level of the second-level H matrix. The second-level codeword having the user data, the first-level parity data and second-level parity data.

The invention discloses a data processing method, device and equipment for a QC-LDPC decoder. The method comprises the following steps: storing posterior probability information into a first memory; in the reading stage of the QC-LDPC decoder, soft information corresponding to a layer where a check matrix is located is read from a first memory or a second memory, a check node value corresponding to the layer where the check matrix is located is read from a third memory, and a variable node update value is stored in the second memory; and in a write-in stage of the QC-LDPC decoder, reading the variable node update value from the second memory, storing the check node update value to a third memory, storing the soft information update value to the first memory and the second memory, and storing the soft information update value to the second memory. And the decoding result is read from the second memory after iteration is completed. By optimizing caching and calling of information such as check nodes, variable nodes and soft information, use of memory resources is reduced.

The invention discloses a multi-user joint decoding method for a cellular-free large-scale MIMO system based on model-driven deep learning, and the method comprises the steps: building an optimization problem of a simulation combination matrix with maximization of the reachable rate of the cellular-free large-scale MIMO system as a target in a simulation part of data decoding; on the basis of a heuristic algorithm, an optimization target is simplified, an optimization problem is divided into a plurality of sub-problems, the single AP simulation precoding matrix optimization problem is solved one by one, and an optimal simulation combination matrix is obtained; a multi-user joint LDPC decoding algorithm is expanded to a cellular-free large-scale MIMO scene, multi-user joint LDPC decoding is realized based on an MIMO-LDPC-Net decoding network, an input layer of the MIMO-LDPC-Net decoding network generates an initial value as an input of a hidden layer, the hidden layer is formed by stacking modules composed of a first sub-layer, a second sub-layer and an MIMO detection layer, and the first sub-layer, the second sub-layer and the MIMO detection layer are stacked. The output layer generates a log-likelihood ratio of the variable node. Experiments show that compared with a traditional algorithm, the heuristic algorithm and the AI auxiliary joint decoding algorithm have a signal-to-noise ratio gain of 1dB.

The present invention relates to a virtualized radio access point, vRAP, as well as to a method of operating the same. With regard to enabling high-performing DU virtualization in order to maximize performance in cloud-based virtualized RANs, the vRAP comprises an encoder / decoder configured to encode / decode transport blocks, TBs, by using iterative codes such as turbo codes or LDPC codes that exchange extrinsic information in each decoding iteration; and a digital signal processor, DSP, pipeline configured to infer information about the decodability of the data of the TBs by exploiting the exchanged extrinsic information.

The invention relates to the technical field of wireless communication, and discloses an adaptive LDPC code coding method, system and device based on evaporation waveguide field intensity distribution, and a medium, and the method comprises the steps: obtaining the evaporation waveguide field intensity distribution in real time, and generating a field intensity distribution diagram; calculating a channel state parameter, and dynamically selecting a low-density parity check code rate according to the channel state parameter information; dynamic low-density parity check coding is adopted, and a sparse structure is adjusted through a check matrix, so that real-time switching of multi-code-rate low-density parity check codes is carried out; and a receiving end carries out decoding by adopting an NW-RBP decoding algorithm, defines a node updating rule, and dynamically schedules a node updating sequence through a residual error. According to the method, the bit error rate under a complex channel is reduced, and meanwhile, the reliable transmission efficiency of system data is improved.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G and 6G. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality XR service or another low-delay service.

The application relates to the technical field of decoding, and provides a source channel joint decoding method and device, electronic equipment and a storage medium, the method comprising the following steps: acquiring initialization information of a channel encoder and prior probability information of a variable node of a source decoder; determining check node information of the source decoder based on the initialization information and the prior probability information; and performing the following iterative steps, which comprise the following steps: updating soft information of the variable node of the source decoder based on the check node information and the initialization information; and performing decoding decision based on the updated soft information to determine a decoding result. The method determines the check node information of the source decoder based on the initialization information and the prior probability information, iteratively updates the soft information of the variable node of the source decoder based on the check node information and the initialization information, that is, uses the information of the source as the soft information available in the decoding process, improves the coding gain, and thus improves the accuracy of the source channel joint decoding.

The invention discloses an LDPC (Low Density Parity Check) code check matrix construction method, which is used for processing a low earth orbit satellite ground foundation zone, and comprises the following steps of: A1, determining degree distribution of a basis matrix under a high code rate by adopting an extrinsic information transfer graph EXIT, and realizing construction of the basis matrix under the constraint of optimal degree distribution through extrinsic information transfer P-EXIT based on a basic model graph; a2, based on the code length and the code rate of FEC coding of the DVB-S2 protocol, determining the size and the expansion factor of a basis matrix corresponding to each code rate; a3, determining a finite field and a generator based on an expansion factor, and constructing a linearly independent shift value row vector and cycle coefficient table; a4, selecting row vectors from the cyclic coefficient table to construct a cyclic shift matrix, and performing short ring identification and elimination on the cyclic shift matrix; and A5, performing matrix hashing on the basis of the basis matrix and the cyclic shift matrix to obtain an LDPC check matrix.

According to one embodiment, a magnetic disk device includes a disk, a write head, a volatile buffer memory, a parity generation unit, a write processing unit, an error correction unit, a storage processing unit, and a conventional correction limit prediction unit. The parity generation unit generates first conventional parity, first potential parity, second conventional parity and second potential parity. The storage processing unit overwrites the second potential parity to a first recoding area if the first prediction information is normal information, and leaves the first potential parity in the first recording area and stores the second potential parity in a second recording area if the first prediction information is replaced with abnormal information.

The application provides a low-density parity-check code decoding method and device based on a graph neural network, which comprises the following steps: step 1, constructing a factor graph comprising variable nodes, check nodes and edge relationships, and mapping log-likelihood ratio information of a received signal to initial embedding of the variable nodes; step 2, generating message features according to node embedding, node degree and iteration step length, and constructing attention weights for each edge to measure the importance of the message; step 3, inputting the message features and the attention weights into a gated recurrent unit to update the residual of the edge weight, and feeding back the updated edge weight to the graph structure; step 4, weighting and aggregating the messages from the adjacent nodes according to the edge weight, calculating the updated embedding of the variable nodes and the check nodes, and performing gated modulation combined with the check result; step 5, repeating steps 2 to 4 until a preset iteration number or a decoding convergence condition is reached, and mapping the final variable node embedding to a decoding result to realize LDPC code word recovery. By introducing the attention mechanism and the gated residual update into the message passing process, the application realizes adaptive modeling of the contribution degree of different edge messages, dynamically remembers the historical state, thereby improving the decoding performance and the convergence speed; meanwhile, the application can effectively reduce the bit error rate and is suitable for high-speed reliable data transmission scenarios in a 5G / 6G wireless communication system.

A method for constructing a permutation matrix or a check matrix, a processing device, a storage medium and a coding method. The method for constructing the permutation matrix comprises: obtaining a base matrix for the permutation matrix; and performing lifting on the base matrix to obtain the permutation matrix. The lifting on the base matrix to obtain the permutation matrix comprises: obtaining a modulus graph of the base matrix, obtaining each macro ring in the modulus graph, and for each macro ring in the modulus graph, determining the size of a short ring corresponding to the macro ring in a Tanner graph of a check matrix corresponding to the permutation matrix from an equivalent cycle value ECS of the macro ring, and determining whether at least one cycle value in the macro ring needs to be set according to the size of the short ring. The method can more efficiently obtain a required permutation matrix.

A method for error correction includes reading, by a memory controller, a first-level codeword from a memory device, the first-level codeword having user data and first-level parity data. The method includes decoding, by the memory controller responsive to determining the first-level codeword contains errors, the first-level codeword using a first-level low-density parity-check (LDPC) decoder employing a first-level H matrix having a portion with reduced column weights to reduce an average row weight for the first-level H matrix. Responsive to the first-level LDPC decoder failing to correct the errors in the first-level codeword, the memory controller decodes a second-level codeword using a second-level LDPC decoder employing a second-level H matrix that includes a portion with increased column weights to increase an average row weight of a second-level of the second-level H matrix. The second-level codeword having the user data, the first-level parity data and second-level parity data.

Apparatuses, systems, and techniques to select fifth-generation (5G) new radio data. In at least one embodiment, a processor includes one or more circuits to select 5G new radio signal information in parallel.

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.

A communication method and a communication apparatus in which a device may perform encoding or decoding based on an LDPC matrix, the LDPC matrix being determined based on an LDPC basis matrix, Zc, a, and b, a first region of the basis matrix including L types of elements, 2 < = L < = 2a * b, a and b not being 1 at the same time, Zc, a, and b being used to lift the elements in the first region to a (a * Zc) * (b * Zc) matrix, the matrix including (a * b) (Zc * Zc) matrices, each Zc * Zc matrix is an all-zero matrix or a cyclic shift matrix, the first sub-matrixes of the L elements are different, and the first sub-matrixes are matrixes formed by replacing the cyclic shift matrixes in (a * b) (Zc * Zc) matrixes of the matrix with the lifted corresponding elements with Zc * Zc unit matrixes. According to the method, the decoding performance of the LDPC code can be improved.

This application provides a coding and decoding method and apparatus. In this method, the transmitting device determines a first low-density parity-check matrix (LDPC) based on the number of bits n1 of the first transmitted bits, encodes the information bits according to the first LDPC matrix, obtains the first transmitted bits, and then transmits the first transmitted bits. Since the first LDPC matrix is ​​determined based on the number of bits of the first transmitted bits, the coding rate of the first LDPC matrix varies depending on the number of bits in the first transmitted bits. The transmitting device can flexibly adapt different coding rates for different numbers of transmitted bits, improving the reliability of data transmission and saving data transmission resources.

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

A method of operating a modem chip may include measuring quality of a plurality of resource elements allocated to receive a codeword, allocating a maximum number of decoding iterations per code block based on a measurement result of the quality and a resource element-to-code block (RE-CB) mapping pattern corresponding to a target slot, and decoding a plurality of first code blocks of the target slot based on the allocated maximum number of decoding iterations per code block.

A data processing method using a plurality of devices for Artificial Intelligence (AI) task, the method comprising: transmitting transmission data including detection data, determining whether an error has occurred in the transmission data based on the detection data, and when the error has not occurred in the transmission data, performing an operation task based on the transmission data, wherein receiving side detection data is derived based on the transmission data, and whether the error has occurred in the transmission data is determined based on the receiving side detection data and the detection data included in the transmission data.

An example includes a method for decoding a shaped codeword that includes shaped data and the shaped parity bits. The shaped codeword has been encoded via an identity matrix comprising an array of layers and block columns of parity data. The method also includes recovering parity data from the shaped parity data of the shaped codeword via the controller. Recovering the parity data includes comparing a syndrome weight of each of a plurality of block columns of the shaped parity data with a threshold and flipping bits of each of the block columns of the shaped parity data in response to the syndrome weight of the respective one of the block columns being greater than the threshold to recover parity data from the shaped parity data of the shaped codeword. The method further includes decoding the shaped data based on the recovered parity data via the controller.

According to the information processing method and device, a first LDPC base matrix can be divided into two types of G * G sub-matrixes, the row weight of each G * G sub-matrix is not larger than 1, and the column weight of each G * G sub-matrix is not larger than 1, so that the hardware implementation complexity is low, and a longer code length can be supported under the same hardware. Moreover, the first region of the first LDPC basis matrix comprises the second type of sub-matrixes with at least two element arrangement modes, so that interleaving can be realized, and long codes are supported. Moreover, the first region of the first LDPC basis matrix comprises a second type of sub-matrix in an element arrangement mode, so that the gain in the aspect of decoding parallelism can be provided.

Systems, methods, and devices related to adaptive base map (BG) selection for low density parity check (LDPC) encoding are described herein. A device (e.g., a wireless transmit / receive unit (WTRU)) may include a processor configured to perform one or more actions. The device may send a request message for a base graph (BG) selection. The device may receive a response message associated with the request message. The response message may indicate a subset of the plurality of BGs associated with the WTRU. The device may select, from a subset of the plurality of BGs, a BG for which a performance associated with the WTRU is determined to meet a threshold. The device may send an indication of the selected BG.

An LDPC-code-based communication method and communication apparatus. In the method, a device can perform encoding or decoding on the basis of an LDPC matrix, wherein the LDPC matrix is determined on the basis of an LDPC base matrix, the base matrix comprises an extended check matrix, the extended check matrix is a lower triangular matrix with diagonal elements all being 1, the extended check matrix comprises a plurality of lower triangular matrices, diagonal elements of each of the plurality of lower triangular matrices are located on the diagonal of the extended check matrix, the positions of the diagonal elements of the plurality of lower triangular matrices do not overlap, and the elements in the extended check matrix other than the diagonal elements of the extended check matrix and the diagonal elements of the plurality of lower triangular square matrices are all zero elements. The method can increase the column weight of a check region, reduce the occurrence probability of an error plane, and also support retransmissions at some specific columns, and thus the method is compatible with an IR-HARQ scheme of 5G LDPC codes.