1480results about "Error correction/detection using multiple parity bits" patented technology

Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 3 / 4, a second parity check matrix corresponding to a first exponent matrix comprising 576 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5 / 6, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 2 / 3, a second parity check matrix corresponding to a first exponent matrix comprising 768 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 1 / 2, a second parity check matrix corresponding to a first exponent matrix comprising 1152 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

The invention relates to an underwater optical communication LDPC (Low Density Parity Check) coding processing method. The method comprises the following steps: determining a current channel quality grade based on a real-time communication distance and channel state information; dynamically selecting LDPC (Low Density Parity Check) coding parameters and modulation orders in combination with equipment mobile data and channel quality levels, and generating an adaptive parameter combination; performing error correction coding on the data according to the selected parameters and generating an optical communication signal; transmitting to a receiving end through an optical channel; and dynamically updating the coding parameter and the modulation order based on the feedback information of the receiving end. According to the method, the problem that a traditional fixed coding scheme is insufficient in error correction capability or wastes resources in a dynamic distance scene is solved by predicting the equipment moving trend and the channel state in real time and adaptively adjusting the coding parameters and the modulation mode, the error rate is remarkably reduced, the communication efficiency is improved, and the method is suitable for a complex and changeable underwater optical communication environment.

The invention discloses an LDPC (Low Density Parity Check) coding and decoding system and method for high-density tape storage, and the system comprises a main controller which is used for scheduling coding and decoding mode switching and module cooperative control; the storage and calculation integrated array is used for executing zero-carrying storage calculation; the ping-pong buffer framework is composed of an input buffer module Buffer A and an output buffer module Buffer B; the dynamic code length extension module is used for reconstructing a cascade link; the preprocessing module is used for converting the noisy code word into a log likelihood ratio (LLR) value; the hard decision module is used for converting the VN message into user data; the main controller is connected with all the modules through a control bus, and the dynamic code length extension module controls the power state and interconnection topology of the sub-arrays. According to the LDPC coding and decoding system and method based on the storage and calculation integrated array, zero-carrying calculation is achieved, iterative decoding is accelerated through a ping-pong buffer architecture, and the code length is flexibly configured through the dynamic code length extension module, the coding and decoding efficiency of high-density tape storage is improved, delay and energy consumption are reduced, meanwhile, multi-code-length self-adaption is supported, and high performance and flexibility are considered.

This application relates to a method for determining a length of an low-density parity-check (LDPC) code word in a ultra-wideband (UWB) system and a related apparatus. The method includes a communication apparatus that determines a length of an LDPC code based on a length of a to-be-encoded information bit. When the length of the information bit ranges from 0 to 324, a 648-bit LDPC code is selected. When the length of the information bit ranges from 325 to 648 or from 973 to 1296, a 1296-bit LDPC code is selected. When the length of the information bit ranges from 649 to 972, a 1944-bit LDPC code is selected. According to embodiments of this application, higher performance gain can be achieved.

In an aspect, digital communication coding methods (or simply coding methods) are provided, said methods comprising providing families of quasi-cyclic low-density parity check, LDPC, codes each represented by a single equation. Said single equation is derived from a geometry whose nature implies good error correcting properties for each of the LDPC codes and allows quasi-cyclic parity check matrices to be constructed for geometric LDPC codes of exceedingly long length, up to and exceeding four hundred thousand bits. The construction of such check matrices is not possible by any other known method. The LDPC codes have different lengths and different rates and the families of LDPC codes are provided with a guarantee of minimum distance. The geometric and quasi-cyclic properties of the LDPC codes allow low complexity decoding with very low frame error rates. Systems, computing systems and computer programs suitable to perform such coding methods are also provided.

Scalable, parallelizable quantum error correction on surface codes can be performed using a decoder graph. Overlapping decoder graph windows can be generated using the decoder graph. First corrections can be independently determined for each of the overlapping decoder graph windows. First core corrections can be retained for core regions of each of the overlapping decoder graph windows. Non-overlapping decoder graph windows can be generated using the decoder graph. The temporal boundaries of the non-overlapping decoder graph windows can be the temporal boundaries of the corrected core regions of the overlapping decoder graph windows. Second corrections can be independently determined for each of the non-overlapping decoder graph windows based on the temporal boundaries of the corrected core regions. The first core corrections and the second corrections can be combined to form a complete set of corrections for the decoder graph.

The invention discloses a data error correction method and device based on low-density parity check, equipment and a medium, and relates to the technical field of data error correction, and the method comprises the steps: reading data to be corrected from a data memory, and carrying out the pre-verification of the data to be corrected and a verification matrix of a preset low-density parity check code, and obtaining a pre-verification result; based on the pre-verification result, determining a first error position set in a code word position set; performing bit flipping operation on code words indicated by the first error position set to complete pre-error correction; and inputting the code word after pre-error correction processing into a low density parity check decoder for decoding, outputting data after error correction, pre-detecting the error position of the code word, and performing bit flipping on the code word at the error position, thereby reducing the number of error bits entering LDPC decoding, and improving the decoding efficiency. Therefore, the number of error bits does not exceed the decoding capability limit of hard decoding, the probability that the system enters soft decoding is reduced, and the decoding throughput rate of the system is ensured.

Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.

The invention discloses a data processing method and device based on a two-dimensional parity check code, a product and a medium, belongs to the field of data protection, is used for carrying out data coding and recovery on a multi-node storage system, and solves the problems that the number of fault disks supporting data recovery simultaneously has a fixed upper limit and the data recovery efficiency is low. In order to solve the problems that a multi-node storage system is not provided with a first check chain and a second check chain for a stripe group of the multi-node storage system through a two-dimensional parity check code, at least one preset straight line is further determined, and for any preset straight line, a data block selection mode along the preset straight line is based on a data block selection mode along the preset straight line. According to the method, the data block is selected from the stripe group of the multi-node storage system, and the new check chain is determined for the stripe group according to the selected data block, so that the at least three check chains are generated for the stripe group, the upper limit number of the faulty disks supporting data recovery at the same time can be flexibly changed, and data recovery of at least three faulty disks at the same time is supported.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G systems and 6G systems. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality (XR) service or a low-delay service.

A receiver configured to receive a signal may include a symbol, the receiver may include: at least one memory storing instructions; and at least one processor configured to execute the instructions to: generate a first posteriori log likelihood ratio corresponding to a bit in the symbol based on a channel log likelihood ratio corresponding to the bit; apply a first scaled value to a first extrinsic log likelihood ratio in the first posteriori log likelihood ratio; generate a first priori log likelihood ratio by selectively using a first reference value based on a comparison result; generate a second posteriori log likelihood ratio corresponding to the bit based on the first priori log likelihood ratio and the channel log likelihood ratio; and decode the signal based on the second posteriori log likelihood ratio.

The embodiment of the invention provides a coding and decoding method and device and a storage medium, relates to the technical field of communication, and can reduce the storage space requirement of coding. The method comprises the steps that a parity check matrix is determined, the dimension of the parity check matrix is determined based on the dimension of a binary extension matrix, the binary extension matrix is obtained by hashing an index matrix based on a lifting factor, and the lifting factor is determined based on the order of a binary basic matrix, an information bit sequence and a non-binary low-density parity check code NB-LDPC code; and according to the parity check matrix or a generation matrix corresponding to the parity check matrix, performing NB-LDPC coding on the information bit sequence to obtain a coding sequence.

The invention discloses a communication method and device, relates to the technical field of communication, and can improve the utilization rate of hardware resources, especially decoding performance. The method comprises the following steps: according to an information bit sequence, a sending end device determines an information column number set associated with M base graphs corresponding to the information bit sequence and a lifting factor set associated with the M base graphs; according to the first information, determining an information column number associated with a code length interval corresponding to the length of the information bit sequence as a target information column number; determining a base graph corresponding to the target information column number from the M base graphs according to the target information column number; wherein M is a positive integer greater than or equal to 2; the first information is used for indicating the number of information columns associated with each code length interval in a plurality of code length intervals; the information column number associated with the code length interval is determined according to an information column number set and / or a lifting factor set; the base graph is used for encoding the information bit sequence to obtain an encoded bit sequence.

The invention discloses a bit flipping decoding method and device for a low-density parity check code and a related medium. The method comprises the following steps of: 1, setting a target parameter; step 2, performing calculation based on the original code word and the check matrix to obtain a syndrome, and if the syndrome is judged to meet a first preset condition, entering step 3; 3, calculating to obtain an energy value of a corresponding bit by using an exclusive-or result between the original code word and the overlapped code word and a syndrome; 4, when the number of iterations is larger than the number of predicted effective times, it is judged that the energy value meets a second preset condition, and the energy value is updated to be the overturning threshold value; 5, performing flipping on the bits of which the energy values are greater than or equal to the flipping threshold value; and step 6, repeating the step 2 to the step 5 until the syndrome is equal to a preset value or the number of iterations reaches the maximum number of iterations, and outputting a decoding result. According to the method, the step 2 to the step 5 are repeated, so that the decoding speed can be improved and the calculation complexity can be reduced while the strong error correction capability is ensured.

The invention discloses an LDPC code coding method. The method comprises the following steps: acquiring an information bit sequence; performing low density parity check (LDPC) coding on the information bit sequence according to a check matrix to obtain a coded bit sequence; wherein the check matrix is determined by a basis matrix, and the basis matrix comprises a basic sub-matrix; the basic sub-matrix is formed by splicing at least two basic unit blocks with circulation or translation. According to the invention, compared with the condition that the shift value Shifting Value of the existing 5G new air interface NR matrix is a random search result and lacks fixed algebraic structure guidance, the basis matrix with the cyclic block or translation block structure designed by the invention can have fixed algebraic structure guidance, the problem that the LDPC lacks practical code design is solved, and the LDPC performance is improved. And the index matrix of the free is difficult to find through random search.

The application provides a polar code soft input soft output decoding method, a decoding device and a communication device; the decoding method comprises the following steps: (S1) performing fast serial cancellation list decoding under dynamic frozen bit constraint for all special nodes constituting a polar code; the types of the special nodes comprise rate zero, rate one, repetition and single parity check; (S2) calculating the approximation of the sum of the posterior probabilities of the legal code words not accessed under each special node after decoding; (S3) using the approximation of the code book probability obtained in the step (S2) to calculate the bit level soft information of the output polar code. The low-latency polar code soft input soft output decoding method provided by the application improves the parallelism by realizing fast soft output decoding based on the Rate0, Rate1, REP and SPC nodes, and significantly reduces the decoding latency without losing the soft output precision compared with the SO-SCL decoding algorithm.

The invention provides a belief propagation LDPC decoding method and device based on deep learning, a medium and a program product. The method comprises the following steps: acquiring an LDPC code training sample set corresponding to a check matrix H; according to the check matrix H, determining a weight matrix and an activation function of each layer of a deep learning decoding model; based on the weight matrix and the activation function, using a belief propagation algorithm to establish a deep learning decoding model; training the deep learning decoding model by using the training sample set, and storing the trained deep learning decoding model as a decoder; and sending the LDPC code soft information which is corresponding to the check matrix H and needs to be decoded into the decoder to complete LDPC decoding. According to the method, iterative operation is completed by using deep learning in the error correction decoding process, the number of decoding iterations is reduced, and the sequence sent by the sending end is restored from the sequence containing noise and interference, so that the problem of decoding error codes caused by noise and other interference factors is solved.

The invention discloses a channel coding and decoding read-write parallel scheduling method, which comprises the following steps of: inputting a base graph matrix, and sequentially arranging to obtain a read variable node sequence and a write variable node sequence of each row according to a column sequence number of a non-zero element in each row of the base graph matrix; constructing a conflict graph according to the base graph matrix; selecting the vertex with the highest saturation from the uncolored vertexes, selecting the minimum available color, and coloring the vertex; coloring each vertex, grouping the vertexes, dividing the vertexes with the same coloring color sequence number into the same group to obtain a vertex group set, and distributing a processing unit for each vertex group; constructing an operation sequence of each processing unit; conflict variable nodes of operation are eliminated; storing a reading variable node sequence and a writing variable node sequence of each operation of each processing unit; the invention further discloses a channel coding and decoding read-write parallel scheduling device. According to the technical scheme, the conflict rate can be effectively reduced, and the method can be suitable for various base graphs.

The invention discloses a coding method and system based on matrix optimization and a storage and calculation integrated accelerator and a medium, and relates to the technical field of communication, and the method comprises the steps: constructing the storage and calculation integrated accelerator which comprises an input buffer area, a dynamic reconstruction storage and calculation array and a result processing module; m * n sub-matrixes obtained by splitting the check matrix H are respectively stored in corresponding storage and calculation integrated cores of the dynamic reconstruction storage and calculation array; the total code c is divided into n segments through an input buffer area and then multiply-accumulate with the corresponding column of sub-matrixes, a calculation result of the dynamic reconstruction storage array is input into a result processing module for result processing, and a final coding result is obtained; according to the coding method, the coding system and the medium, the dynamic adaptability and the calculation efficiency are broken through, and a high-reliability and low-delay LDPC coding solution is provided for tape storage.

Techniques for decoding a low-density parity check (LDPC) can include determining an asymmetric ratio of bit errors read as logic zero to bit errors read as logic one. The energy of each variable node of the LDPC codeword can be computed. For each variable node having an energy greater than a threshold energy, the variable node can be added to a collection of candidate bits for bit flipping. The asymmetric ratio can then be applied to flip bits in the collection of candidate bits to decode the LDPC codeword.

This invention discloses a low-complexity decoding method for LDPC-Hadamard codes based on a prototype diagram, belonging to the field of digital signal processing. The implementation method is as follows: information bits are LDPC encoded, and then the constraint relationship of the check nodes of the LDPC code is encoded into Hadamard code to obtain the prototype diagram of the LDPC-Hadamard code; the encoded codewords are transmitted and received through a channel, and the PVN and HCN nodes are initialized with the received information; Hadamard decoding is performed using a symbol-by-symbol maximum a posteriori probability decoding algorithm, and DFHT approximation is used to reduce decoding complexity; the decoded information is transmitted to the PVN nodes; the updated HCN node information is summed with the information from the previous iteration, and the summation result is used to determine the decoding; a decoding decision is made on the PVN information, and decoding is performed. This invention combines LDPC encoding, Hadamard encoding, and Max-Log approximation calculation methods to reduce decoding complexity and enhance the stability and reliability of the communication system.

The invention discloses a soft decoding method and device, a medium and a product, and relates to the technical field of error correction coding, and the method is applied to a low-density parity check code, and comprises the steps: obtaining a target low-density parity check code with an information node and a check node containing an erasure bit; and allocating a preset non-zero log-likelihood ratio to the erasure bit on the check node, and executing first soft decoding. And if the first soft decoding fails, judging whether to carry out second soft decoding or not based on the weight of the syndrome generated by the first soft decoding and the number of the erasure bits on the information node. If it is judged that the second soft decoding needs to be carried out, a preset non-zero log likelihood ratio is distributed to the erasure bit located on the information node, and the second soft decoding is carried out. According to the method and the device, the erasing bits on different nodes are conditionally processed in stages, so that the success rate and the efficiency of decoding are effectively improved.

A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.