328results about "Error correction/detection by combining multiple code structures" patented technology

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

A method of operating a user equipment (UE) and a base station in a wireless communication system and an apparatus supporting this are disclosed. The method of operating the UE may comprise encoding input data based on a neural network and transmitting the encoded input data to a base station. In this case, the neural network may be determined to be at least one of a real neural network or a complex neural network.

The invention provides a dual-binary Turbo decoding method based on deep learning, and belongs to the technical field of wireless communication. Comprising the following steps: generating a binary random bit stream as original information, and generating a Turbo code sequence through two recursive system convolutional code component encoders; pre-processing the Turbo code sequence, and inputting the pre-processed Turbo code sequence into a bidirectional PNN model for processing to obtain an output feature vector; based on the output feature vector, standardization is carried out through a batch normalization layer, and a decoding result probability value is output by using a full connection layer and a Sigmoid activation function; and on the basis of the decoding result probability value, a Max-Log-MAP algorithm is cascaded with a component decoder of the bidirectional RNN to obtain a decoding result.

The invention relates to the technical field of communication and computer instruction execution and processing, in particular to a polar code encoding and decoding algorithm-oriented special instruction set processor and an implementation method, and a vector processor has efficient parallel computing capability. A coding and decoding algorithm of a polar code relates to parallel computing of a large number of log-likelihood ratios, a vector processor of a special instruction set can process a plurality of LLR values at the same time through a parallel processing unit, and the throughput rate is remarkably improved; special instructions such as polarization shuffling and vector G operation instructions are designed for polarization code encoding and decoding and are used for accelerating algorithm operation. The method can achieve the balance among the performance, the energy efficiency and the flexibility, can adapt to the continuous iteration upgrading of the algorithm due to the programmable and reusable characteristics, and has a good application prospect.

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.

Aspects of the present disclosure provide improved techniques for detecting the presence of RF anomalies and providing for enhanced user control of RF anomaly detection and related actions. Some aspects relate to detecting an RF anomaly by determining, based on a multidimensional encoding of characteristics of an RF signal, that the RF signal is anomalous compared to a baseline of multidimensional encodings of characteristics of RF radiation received in the operating environment. Some aspects relate to controlling RF anomaly detection by initiating an action in response to selection of an option displayed to a user in a graphical user interface in along with an indication of an RF signal determined to be anomalous compared to a baseline. Some aspects relate to identifying a subset of RF data and determining a presence of an RF anomaly corresponding to the subset by comparing a representation of RF radiation to a baseline.

Methods, systems, and devices for coordinated error correction are described. A memory device indicates, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on the comparison, an indication of or based on whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both.

A device in a communication or broadcast system may comprise a memory, at least one transceiver, and at least one processor, comprising processing circuitry, connected to the memory and the at least one transceiver. The device may be configured to: acquire a signal; identify information about at least one dummy parity check (PC) bit among one or more PC bits of the signal on the basis of at least one information bit of the signal and a rate matching size for a polar code; identify a decoder setting for error detection and error correction on the basis of information about the at least one dummy PC bit; and decode the signal based on the decoder setting. The at least one dummy PC bit may include a bit having a fixed value regardless of one or more preceding bits of the decoding among the one or more PC bits.

The invention discloses a multi-user joint decoding method for a cellular-free large-scale MIMO system based on model-driven deep learning, and the method comprises the steps: building an optimization problem of a simulation combination matrix with maximization of the reachable rate of the cellular-free large-scale MIMO system as a target in a simulation part of data decoding; on the basis of a heuristic algorithm, an optimization target is simplified, an optimization problem is divided into a plurality of sub-problems, the single AP simulation precoding matrix optimization problem is solved one by one, and an optimal simulation combination matrix is obtained; a multi-user joint LDPC decoding algorithm is expanded to a cellular-free large-scale MIMO scene, multi-user joint LDPC decoding is realized based on an MIMO-LDPC-Net decoding network, an input layer of the MIMO-LDPC-Net decoding network generates an initial value as an input of a hidden layer, the hidden layer is formed by stacking modules composed of a first sub-layer, a second sub-layer and an MIMO detection layer, and the first sub-layer, the second sub-layer and the MIMO detection layer are stacked. The output layer generates a log-likelihood ratio of the variable node. Experiments show that compared with a traditional algorithm, the heuristic algorithm and the AI auxiliary joint decoding algorithm have a signal-to-noise ratio gain of 1dB.

Communication devices, systems and methods for performing multi-layer packet coding (MLPC) in a wireless system are provided. The MLPC includes segmenting a data stream into a plurality of data segments, encoding each of the plurality of data segments into a plurality of forward error correction (FEC) codewords, performing a first exclusive OR (XOR) operation on the plurality of FEC codewords to generate a plurality of first layer parity codewords, performing a second XOR operation on the plurality of first layer parity codewords to generate at least one second layer parity codeword, and transmitting at least one of: the plurality of FEC codewords, the plurality of first layer parity codewords, or the at least one second layer parity codeword.

The present invention relates to a virtualized radio access point, vRAP, as well as to a method of operating the same. With regard to enabling high-performing DU virtualization in order to maximize performance in cloud-based virtualized RANs, the vRAP comprises an encoder / decoder configured to encode / decode transport blocks, TBs, by using iterative codes such as turbo codes or LDPC codes that exchange extrinsic information in each decoding iteration; and a digital signal processor, DSP, pipeline configured to infer information about the decodability of the data of the TBs by exploiting the exchanged extrinsic information.

An interleaving and deinterleaving method suitable for Turbo decoding of 4G 802.16m protocol, aiming at 39 groups of Turbo interleaving parameters supported by 4G 802.16m protocol, the method uses grouped interleaving initial address table Itab_init and fixed interleaving step Istep at each level to realize simplified calculation of interleaving address; uses grouped deinterleaving initial address table Dtab_init and fixed deinterleaving step Dstep at each level to realize simplified calculation of deinterleaving address; uses the mapping relationship between interleaving and deinterleaving to process the interleaver and deinterleaver of Turbo iterative decoding and replace the deinterleaving table and interleaving table between iteration of component decoders. The present application reduces the calculation complexity based on the simplified Turbo decoding interleaving and deinterleaving calculation method, and replaces the interleaving and deinterleaving tables between two component encoders to realize parallel processing of interleaving and deinterleaving processing and Turbo component decoder external information calculation, which reduces the interleaving and deinterleaving delay to equivalent only one processing time slot, is irrelevant to interleaving depth, and improves the decoding rate of Turbo decoding.

Implementations for simplified and efficient error correction code schemes with multiple codewords are provided. One aspect includes a computing system comprising: processing circuitry and memory storing instructions that, during execution, causes the processing circuitry to: encode data comprising user data and metadata in a memory module comprising a plurality of dies by: logically partitioning the memory module into a plurality of partitions; on a first partition: storing a first portion of the user data on one or more memory segments of the first partition; and storing a first cyclic redundancy check (CRC) codeword and the metadata on a memory segment of the first partition different from the one or more memory segments of the first partition, wherein the first CRC codeword is generated based on the first portion of the user data and the metadata; and storing parity data on one of the plurality of dies.

Methods, devices, and systems for controlling a storage system, including: a storage device configured to store a plurality of code words; and at least one processor configured to: obtain information bits; encode the information bits using a first code to obtain a first plurality of code words; encode the first plurality of code words using a second code to generate a second plurality of code words; update the first plurality of code words based on the second plurality of code words to generate an adaptive generalized concatenated code (A-GCC) code word; and store the A-GCC code word in the storage device, wherein each code word of the first plurality of code words is encoded using a different error protection level.

In 5G / New Radio (NR), sidelink communication refers to a channel for communications directly between devices, e.g., user equipment (UEs), without use of traditional uplink or downlink communication channels. Sidelink Control Information (SCI) is separated into two stages (i.e., SCI stage 1 and SCI stage 2) before being transmitted to configure a user device. A method for configuring sidelink communications for a wireless device includes: obtaining SCI Stage 2 payload information; attaching and distributing cyclic redundancy check (CRC) information to the payload information; performing encoding and rate matching (RM) on the payload information; scrambling the encoded and rate matched payload information; performing modulation on the scrambled payload information; determining a resource mapping for the modulated payload information, wherein the modulated payload information is aggregated across two or more slots (e.g., using different processing operations for at least two slots); and transmitting the modulated payload information according to the determined resource mapping.

According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

The present invention discloses a two-stage decoding method for algebraic codes, comprising: S1, performing hard decision based on a received sequence to obtain a hard decision sequence; S2, generating one or more test error pattern sequences based on the received sequence; S3, performing bitwise exclusive-OR on each error pattern sequence and the hard decision sequence to obtain a second-stage decoding input sequence; S4, determining whether second-stage algebraic code decoding is required for each second-stage decoding input sequence, and performing S5 for all input sequences requiring algebraic code decoding; S5, performing algebraic code decoding, returning a decoding status and a decoding result; and S6, selecting the optimal decoding result from the decoding output as the decoding output. The present invention can achieve performance close to the finite code length bound based on hard decision decoding when the list is small, achieving low-complexity and high-performance decoding. Furthermore, a specially introduced judgment skipping mechanism can significantly reduce the number of times the algebraic code decoder is called in the second stage, thereby significantly reducing decoding power consumption.

This invention provides a Viterbi decoding method, apparatus, electronic device, and storage medium. The method includes: calculating the distance between a received codeword and a desired codeword at the same time to obtain a branch metric value at the current time; determining a surviving path metric value at the current time based on the branch metric value, thereby determining surviving path information; setting a deletion threshold; filtering the surviving path metric value at the current time based on the deletion threshold to obtain the minimum surviving path metric value; and, when the decoding time reaches the backtracking depth, starting from the state corresponding to the minimum surviving path metric value at the current decoding time, starting backtracking based on the surviving path information to output the corresponding decoding result. Thus, the setting of the deletion threshold achieves effective filtering of surviving paths, effectively reducing the computational load in the decoding process, and simultaneously achieving high-speed, low-power efficient decoding under any signal-to-noise ratio conditions.

Embodiments of this application disclose a data processing method and a data processing device, which can achieve good performance of a connected FEC-based solution in low-latency scenarios. In a connected FEC-based transmission solution, before convolutional interleaving is performed on a first data stream, interleaved alignment must first be performed to determine the boundaries of each bit set in the first data stream and the boundaries of each bit subset within each bit set. Furthermore, in the convolutional interleaving process, bit subsets are transmitted to each storage unit as granularity. In other words, each bit subset contains d bits, and each storage unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

To perform error correction with higher accuracy.SOLUTION: A memory system includes a nonvolatile memory storing a concatenated code consisting of a first error correction code and a second error correction code, and a memory controller. When first decoding processing using the first error correction code on read-out information read from the nonvolatile memory or verification processing for verifying that the read-out information does not contain any error is successful, the memory controller generates a first parity, which is a parity of the second error correction code, and calculates a first evaluation value for determining whether the read-out information contains any error using the generated first parity and a second parity, which is a parity of the second error correction code after the second decoding processing. The memory controller uses the first evaluation value to determine whether the read-out information contains an error.SELECTED DRAWING: Figure 1

A method and an apparatus for processing an Ethernet data stream, a computer system, a network system, and a computer-readable storage medium are disclosed. The method is applied to a receiver apparatus including a first forward error correction FEC decoder and a second FEC decoder. The method includes: obtaining transmission information of a first data stream; and if the transmission information meets a trigger condition, adjusting an error correction capability of the receiver apparatus. The data stream can be flexibly and effectively processed by using the method, the apparatus, the computer system, the network system, and the computer-readable storage medium.

Various aspects of the present disclosure generally relate to wireless communication, and to supporting physical broadcast channel (PBCH) scrambling and soft combining that supports larger synchronization signal block (SSB) periodicity. For example, a network node may transmit multiple SSBs in accordance with an SSB periodicity. The SSBs respectively include multiple PBCHs, and the PBCHs respectively include multiple master information blocks (MIBs) in accordance with an MIB periodicity. Each of the PBCHs includes a respective scrambled portion and a respective unscrambled portion. The unscrambled portions each include timing information in accordance with the SSB periodicity and the MIB periodicity. The UE decodes the PBCHs by soft combining the PBCHs in accordance with the timing information and descrambles resulting scrambled PBCH payloads in accordance with scrambling sequences associated with the unscrambled portions.