172results about "Error correction/detection by combining multiple code structures" patented technology

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

Aspects of the present disclosure provide improved techniques for detecting the presence of RF anomalies and providing for enhanced user control of RF anomaly detection and related actions. Some aspects relate to detecting an RF anomaly by determining, based on a multidimensional encoding of characteristics of an RF signal, that the RF signal is anomalous compared to a baseline of multidimensional encodings of characteristics of RF radiation received in the operating environment. Some aspects relate to controlling RF anomaly detection by initiating an action in response to selection of an option displayed to a user in a graphical user interface in along with an indication of an RF signal determined to be anomalous compared to a baseline. Some aspects relate to identifying a subset of RF data and determining a presence of an RF anomaly corresponding to the subset by comparing a representation of RF radiation to a baseline.

Communication devices, systems and methods for performing multi-layer packet coding (MLPC) in a wireless system are provided. The MLPC includes segmenting a data stream into a plurality of data segments, encoding each of the plurality of data segments into a plurality of forward error correction (FEC) codewords, performing a first exclusive OR (XOR) operation on the plurality of FEC codewords to generate a plurality of first layer parity codewords, performing a second XOR operation on the plurality of first layer parity codewords to generate at least one second layer parity codeword, and transmitting at least one of: the plurality of FEC codewords, the plurality of first layer parity codewords, or the at least one second layer parity codeword.

The present invention relates to a virtualized radio access point, vRAP, as well as to a method of operating the same. With regard to enabling high-performing DU virtualization in order to maximize performance in cloud-based virtualized RANs, the vRAP comprises an encoder / decoder configured to encode / decode transport blocks, TBs, by using iterative codes such as turbo codes or LDPC codes that exchange extrinsic information in each decoding iteration; and a digital signal processor, DSP, pipeline configured to infer information about the decodability of the data of the TBs by exploiting the exchanged extrinsic information.

Implementations for simplified and efficient error correction code schemes with multiple codewords are provided. One aspect includes a computing system comprising: processing circuitry and memory storing instructions that, during execution, causes the processing circuitry to: encode data comprising user data and metadata in a memory module comprising a plurality of dies by: logically partitioning the memory module into a plurality of partitions; on a first partition: storing a first portion of the user data on one or more memory segments of the first partition; and storing a first cyclic redundancy check (CRC) codeword and the metadata on a memory segment of the first partition different from the one or more memory segments of the first partition, wherein the first CRC codeword is generated based on the first portion of the user data and the metadata; and storing parity data on one of the plurality of dies.

This invention provides a Viterbi decoding method, apparatus, electronic device, and storage medium. The method includes: calculating the distance between a received codeword and a desired codeword at the same time to obtain a branch metric value at the current time; determining a surviving path metric value at the current time based on the branch metric value, thereby determining surviving path information; setting a deletion threshold; filtering the surviving path metric value at the current time based on the deletion threshold to obtain the minimum surviving path metric value; and, when the decoding time reaches the backtracking depth, starting from the state corresponding to the minimum surviving path metric value at the current decoding time, starting backtracking based on the surviving path information to output the corresponding decoding result. Thus, the setting of the deletion threshold achieves effective filtering of surviving paths, effectively reducing the computational load in the decoding process, and simultaneously achieving high-speed, low-power efficient decoding under any signal-to-noise ratio conditions.

Embodiments of this application disclose a data processing method and a data processing device, which can achieve good performance of a connected FEC-based solution in low-latency scenarios. In a connected FEC-based transmission solution, before convolutional interleaving is performed on a first data stream, interleaved alignment must first be performed to determine the boundaries of each bit set in the first data stream and the boundaries of each bit subset within each bit set. Furthermore, in the convolutional interleaving process, bit subsets are transmitted to each storage unit as granularity. In other words, each bit subset contains d bits, and each storage unit is configured to store d bits. The bits in each bit subset come from v symbols, and each of the v symbols comes from v first codewords. In other words, one symbol is selected from each of the v first codewords to form a bit subset.

A method and an apparatus for processing an Ethernet data stream, a computer system, a network system, and a computer-readable storage medium are disclosed. The method is applied to a receiver apparatus including a first forward error correction FEC decoder and a second FEC decoder. The method includes: obtaining transmission information of a first data stream; and if the transmission information meets a trigger condition, adjusting an error correction capability of the receiver apparatus. The data stream can be flexibly and effectively processed by using the method, the apparatus, the computer system, the network system, and the computer-readable storage medium.

Various aspects of the present disclosure generally relate to wireless communication, and to supporting physical broadcast channel (PBCH) scrambling and soft combining that supports larger synchronization signal block (SSB) periodicity. For example, a network node may transmit multiple SSBs in accordance with an SSB periodicity. The SSBs respectively include multiple PBCHs, and the PBCHs respectively include multiple master information blocks (MIBs) in accordance with an MIB periodicity. Each of the PBCHs includes a respective scrambled portion and a respective unscrambled portion. The unscrambled portions each include timing information in accordance with the SSB periodicity and the MIB periodicity. The UE decodes the PBCHs by soft combining the PBCHs in accordance with the timing information and descrambles resulting scrambled PBCH payloads in accordance with scrambling sequences associated with the unscrambled portions.

Acceleration of S-polarized ECC throughput by a scheduler is disclosed. A method of simplified successive cancellation list (SSCL) error decoding of an S-polar code includes representing an S-polar code as a perfect binary tree; providing a node v with a soft information vector from a parent node of v to compute a soft information vector for a left child node of v; providing v with a hard decision vector from the left child node and using it with to create a soft information vector and pass it to a right child node of v; providing v with a hard decision vector from its right child node and using it with to create a hard decision vector β v and pass it to its parent node; when v is an i-th leaf node of the perfect tree, updating two path metrics and selecting a path obtained by extending a current path by the lowest path metric.

The invention discloses an efficient method for realizing Turbo coding by an FPGA (Field Programmable Gate Array), which comprises the following steps of: before data enters a Turbo coding module, firstly introducing a dual-port RAM (Random Access Memory) and a rate grouping processing module, preprocessing and reasonably segmenting the data, saving time delay, reducing hardware resource consumption, better adapting to the Turbo coding module, and greatly compressing the processing and queuing time of the data in a Turbo coder; after Turbo coding is completed, serial-to-parallel processing is carried out on coded data, and it is ensured that the coded data can be continuously and stably output in a serial mode. According to the method, the problems that a traditional Turbo encoder is large in encoding delay and large in resource consumption are solved, the operation complexity is low, and the Turbo code can be applied to a new wireless communication system.

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a soft-aided decoder (112) to produce decoded bits (118) using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal (soft-aided bit marking) that are computed by calculation (114) and marking blocks (116) based on an absolute value of log-likelihood ratios (LLRs) of the HD-FEC coded signal. The hard-decision (HD) forward error correcting (FEC) coded signal may be, for example, a staircase code (SCC) coded signal or a product code (PC) coded signal.

Embodiments of the present disclosure relate to inner FEC encoding systems and methods. The present invention relates to communication systems and methods. According to certain embodiments, FEC data streams from a plurality of FEC data channels are received. First stage interleaving and inner encoding are performed on the FEC data streams to generate inner encoded data streams. Second stage interleaving processing is performed to interleave the inner encoded data streams. There are other embodiments.

A communication device may include: a processor configured to perform a procedure comprising: receiving a first consensus check code from a first communication device; receiving a second consensus check code from a second communication device; generating a combination code by network encoding the first consensus check code and the second consensus check code; and instructing the transmission of the combination code to the first communication device and to the second communication device.

This invention discloses a multidimensional coupled chain code encoding method based on generalized integrated interleaving codes. It selects d-dimensional chain codes from s-dimensional chain codes for generalized integrated interleaving encoding, resulting in the l-th... i The code length of the wiry chain code is [value], and the information bit length is [value]. The remaining (s-d) wiry chain code is encoded, and the l′ [value] is [value]. i' Wirachain codes use linear block codes with a code length of and an information bit length of as the basic code, and the sequence c... (t) Initialize to an all-zero sequence; set the information sequence u Divide into sL groups. For the l-th dimensional zip code, divide into groups of length k. t,l -m t,l sequence u (t,l) With a length of m t,l sequence w (t,l) The data is fed into a multiplexer to obtain a length of k. t,l sequence a (t,l) The sequence is fed into a basic code encoder for encoding to obtain a codeword sequence. Simultaneously, the sequence is fed into a generalized integrated interleaved code encoder for encoding to obtain another codeword sequence. c (t,0) , c (t,1) ,…, c (t,s‑1) The encoded output sequence c at time t is obtained by feeding it into the multiplexer. (t) This invention has the advantages of simple coding, ease of implementation, and good performance.

The present disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate than a 4G communication system such as LTE. An encoding method performed by a transmission device of a communication system according to an embodiment of the present disclosure may comprise the steps of: identifying at least one parameter related to a convolutional code associated with a polarization-adjusted convolutional (PAC) code; on the basis of the at least one parameter, identifying a parity check matrix for an input binary vector of a polar code associated with the PAC code; on the basis of the parity check matrix, encoding a polar code concatenated with an outer code; and transmitting a codeword vector generated on the basis of the encoding.

A device capable of operating in a wireless communication environment. The device may be configured to determine a plurality of control signaling bits. The device may determine a plurality of cyclic redundancy check (CRC) bits based on the plurality of control signaling bits. The device may apply a channel coding scheme to the plurality of control signaling bits and the plurality of CRC bits. The plurality of CRC bits may be distributed among the plurality of control signaling bits prior to applying the channel coding scheme. The device may transmit the channel coded plurality of control signaling bits and CRC bits.

The invention relates to a system and a method for optimizing Turbo coding and decoding by a neural network, and belongs to the technical field of crossing of communication technology and artificial intelligence. The system comprises a PL end which adopts a Turbo decoding IP core, supports dynamic configuration of iteration times and LLR scaling factors, and realizes data throughput through an AXI-Stream interface; at the PS end, a Transform model is deployed, and channel feature extraction is realized; the collaboration layer is used for realizing zero-copy data transmission between the PS and the PL; according to the method, a closed-loop optimization mechanism is formed through an end-to-end process of data input, feature extraction, parameter configuration, decoding execution, result verification and performance circulation; the objective of the invention is to realize jumping of decoding performance by dynamically adjusting decoding parameters for channel parameters, realize efficient interaction of decoding at a PS end and a PL end, improve Turbo decoding throughput and significantly improve system BER performance according to adaptive parameter adjustment.

The invention provides a dual-binary turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; determining a processing module according to the length of the processing data; wherein the processing module uniquely corresponds to one storage unit; and performing multi-round parallel processing on the processing data based on the DVB-RCS2 standard through the determined processing module. According to the method, a processing module is determined according to the length of processing data; wherein the processing module uniquely corresponds to one storage unit; through the determined processing module, multi-round parallel processing is performed on the processing data based on the DVB-RCS2 standard, parallel processing of the processing data is realized, the processing time is reduced, and the processing efficiency is improved.

A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.

Provided is a device in a communication system or a broadcast system. The device may comprise a memory, at least one transceiver, and at least one processor connected to the memory and the at least one transceiver. The device may be configured to: acquire a signal; identify information about at least one dummy parity check (PC) bit among one or more PC bits of the signal on the basis of at least one information bit of the signal and a rate matching size for a polar code; identify a decoder setting for error detection and error correction on the basis of information about the at least one dummy PC bit; and decode the signal on the basis of the decoder setting. The at least one dummy PC bit may include a bit having a fixed value regardless of one or more preceding bits of the decoding among the one or more PC bits.

A turbo encoder intended for use in earth stations communicating through data networks where Successive Interference Cancellation ( S IC ) multiple access to Low Earth Orbit ( LEO ) satellites is employed. The disclosed turbo encoder constitutes an enhancement to code rate 1 / 8 of a known in the art code rate 1 / 6 turbo encoder that comprises two recursive convolutional encoders, an encoder a and an encoder b. The enhancement is achieved by adding two recursive convolutional encoder forward connection vectors to the code rate 1 / 6 turbo encoder as follows : adding forward connection vector G4 10111 to either encoder a or encoder b; and adding forward connection vector G2 10101 to encoder b.

A system includes a memory device and one or more processing devices operatively coupled to the memory device via a memory channel. The processing device(s) cause data to be received over the memory channel from the memory device, where the data includes known multi-bit patterns. The processing device(s) sweep the data over voltage and time to generate eye diagram data. The processing device(s) detect errors at identified cursors of the eye diagram data, where each identified cursor corresponds to a known multi-bit pattern within a set of previously transmitted bits. The processing device(s) store counts of each detected error associated with a respective known multi-bit pattern. The processing device(s) determine, using the counts, a plurality of decision feedback equalizer (DFE) coefficients to be employed in receiving unknown data over the memory channel.

Disclosed in the present application are a method and apparatus for wireless communication. The method comprises: a first node receiving first signaling, and receiving or sending a first signal. The first signaling indicates scheduling information of the first signal; a first bit block and a second bit block are used together to generate the first signal, the first bit block depends on an output of a first encoder, wherein an input of the first encoder comprises a first information bit block, and the second bit block depends on an output of a second encoder, wherein an input of the second encoder comprises a first check bit block, the first information bit block being used for generating the first check bit block; and the ratio between the size of the input of the first encoder and the size of the first bit block is not equal to the ratio between the size of the input of the second encoder and the size of the second bit block. The method improves encoding efficiency and / or encoding performance, thereby improving system transmission efficiency and performance.

The invention provides a turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; partitioning the processed data into blocks; wherein the blocks correspond to different storage units; performing multi-path processing on each block based on each storage unit; wherein the processing is interleaving or de-interleaving. According to the method provided by the invention, the parallel processing of the processing data is realized by partitioning the processing data and then performing multi-path processing on each block, so that the processing time is shortened, and the processing efficiency is improved.

An encoding method and apparatus, a decoding method and apparatus, and a device are provided. The encoding method includes: obtaining K to-be-encoded bits (S301), where K is a positive integer; determining a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed based on a preset position relationship, and the sub-block includes a plurality of first generator matrix cores (S302); generating a second generator matrix based on the first generator matrix, where the second generator matrix includes T sub-blocks, and a position relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset position relationship (S303), where T is a positive integer; and polar encoding the K to-be-encoded bits based on the second generator matrix (S304), to obtain encoded bits. This can reduce encoding / decoding complexity.