624results about "Error correction/detection by combining multiple code structures" patented technology

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

The present invention relates to a method by which a device transmits a signal in a communication system and the device for same, and to a method and a device for same, the method comprising the steps of: applying a pre-code to an information bit sequence so as to generate a first encoded bit sequence including an information set, a frozen set, and a parity set; additionally changing some of the information sets of the first encoded bit sequence into the frozen set and the parity set so as to generate a second encoded bit sequence corresponding to the first encoded bit sequence; applying a polar code to the second encoded bit sequence so as to generate a third encoded bit sequence; and transmitting the third encoded bit sequence.

A cyclic redundancy check bit determination method and system, the method including obtaining an information bit, determining, based on a first correspondence, that a check bit length is L, where L is a natural number, and where the first correspondence includes a correspondence among code length information of to-be-transmitted data including the information bit, length information of the information bit, and the check bit length, and determining a first check bit based on a first cyclic redundancy check (CRC) polynomial, where a length of the first check bit is the check bit length L, where a highest power of terms in the first CRC polynomial is Lmax, where Lmax is a positive integer, and where Lmax is greater than or equal to L.

The invention provides a Turbo product code-oriented decoding method and system, and relates to the technical field of communication, and the method comprises the steps: initializing a Turbo product code decoder; obtaining channel information to be decoded; quantizing the channel information into signed character type data; transmitting the quantized channel information to a GPU (Graphics Processing Unit) in an asynchronous transmission mode; respectively updating the channel information according to rows and columns through a Chase algorithm by utilizing an intra-frame parallelism degree consistent with the size of a GPU thread block until the maximum number of iterations is reached, and finishing the updating of the soft output information; performing hard decision according to the channel information and the updated soft output information; transmitting the hard decision result to a host memory of the CPU in an asynchronous transmission mode; and after decoding of all code words is completed, resource release is carried out. According to the invention, the decoding process with low delay, high throughput rate and high reliability can be realized, and the resource utilization rate and the decoding efficiency are improved.

A device is configured for encoding an input sequence comprising message bits into a codeword using a polar code. The device is configured to sequentially encode each of a plurality of blocks of the input sequence by applying a sliding window to the input sequence, wherein each block of the input sequence is encoded based on an XOR operation of the block and a previous block of the input sequence to obtain a codeword block of the codeword, and sequentially output each obtained codeword block of the codeword.

A method of operating a user equipment (UE) and a base station in a wireless communication system and an apparatus supporting this are disclosed. The method of operating the UE may comprise encoding input data based on a neural network and transmitting the encoded input data to a base station. In this case, the neural network may be determined to be at least one of a real neural network or a complex neural network.

The invention provides a dual-binary Turbo decoding method based on deep learning, and belongs to the technical field of wireless communication. Comprising the following steps: generating a binary random bit stream as original information, and generating a Turbo code sequence through two recursive system convolutional code component encoders; pre-processing the Turbo code sequence, and inputting the pre-processed Turbo code sequence into a bidirectional PNN model for processing to obtain an output feature vector; based on the output feature vector, standardization is carried out through a batch normalization layer, and a decoding result probability value is output by using a full connection layer and a Sigmoid activation function; and on the basis of the decoding result probability value, a Max-Log-MAP algorithm is cascaded with a component decoder of the bidirectional RNN to obtain a decoding result.

According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

The embodiment of the invention provides a data coding method and a related device. The coding complexity is reduced while the code word length and the redundancy cost of an inner code are not changed. Specifically, for a first data stream subjected to outer code coding, every continuous k bits in the first data stream need to be subjected to inner code coding, and k is an odd number greater than 1. The other bits except one target bit in the k bits are subjected to XOR pairwise to obtain (k-1) / 2 bits in total. Further, a bit sequence including (k-1) / 2 bits and a target bit is subjected to second FEC coding to obtain p check bits. Wherein the n bits in the code word of the inner code after the inner code is coded comprise continuous k bits and p check bits. It can be seen that the embodiment of the invention adopts a mode of first exclusive OR and then encoding, for example, code word processing of (128, 119) can be realized through an encoder of (69, 60), and the encoding complexity is reduced while the code word length of an inner code and the redundancy cost are not changed.

Disclosed are a data processing method, an electronic device, and a computer-readable storage medium. The data processing method may include: determining, in response to acquiring at least one source data packet, a first network coding mode for the at least one source data packet according to a pre-configured first network coding parameter; encoding the at least one source data packet according to the first network coding mode to obtain a first encoded data packet; and sending the first encoded data packet to a first receiving end, such that the first receiving end processes the first encoded data packet.

A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.

The embodiment of the invention discloses a data processing method and a related device. Specifically, for a first data stream subjected to outer code coding, the first data stream is subjected to inner code coding to obtain a second data stream comprising at least one inner code word. Wherein the inner code coding adopts GF (28) error correction 2-bit extended BCH coding, the inner code codeword comprises 119 information bits and 17 check bits, the total number of the bits is 136, and the 17 check bits comprise 1-bit CRC extended check bit. That is to say, the embodiment of the invention adopts single-bit extended BCH (136, 119) coding with 2 bits of error correction capability. In an existing 400G ZR scene, data filling and convolutional interleaving between outer code coding and inner code coding are realized by taking 119 bits as granularity, so that the inner code coding scheme provided by the embodiment of the invention is compatible with the 400G ZR scene, and meanwhile, the cascade coding performance is also improved.

A communication unit for performing soft-decision demodulation includes a receiver that receives a transmitted signal conveying a first set of bits including k bits selected from a set of 2k possible signals. A demodulator includes a bank of 2k correlators that detects a transmission of each possible transmitted signal, and outputs 2k magnitudes of correlator outputs, based on the detected possible transmitted signals, as a first set of inputs. A de-mapper circuit receives the first set of inputs and determines derived from a plurality of aggregated correlator output magnitude distributions of the first set of inputs, wherein the plurality of aggregated correlator output magnitude distributions is fewer than 22k; and calculates therefrom a first set of aposteriori soft bits including k soft bits. In this manner, high quality soft-decisions can be obtained in a robust and practical manner.

Systems, devices, and methods for encoding information bits for storage, including obtaining information bits; encoding the information bits using an inner code to obtain a plurality of inner code words; encoding the plurality of inner code words using an outer code to generate an outer code word; and storing the outer code word in a storage device, wherein at least one of the inner code and the outer code includes a generalized concatenated code (GCC), and wherein the outer code word includes a hierarchical-GCC (H-GCC) code word.

A method includes monitoring processing of a writing process associated with a plurality of sets of encoded data slices to storage units of the storage network in accordance with error encoding parameters to produce write processing performance information, where for a set of encoded data slices of the plurality of sets of encoded data slices, the error encoding parameters include an error coding number and a decode threshold number. When the write processing performance information compares unfavorably to a desired write performance range, the method further includes adjusting at least one of the error coding number and the decode threshold number to produce adjusted error encoding parameters for writing subsequent sets of encoded data slices of the plurality of sets of encoded data slices.

The invention discloses a low-complexity Fano decoding method for a PAC code, and relates to the field of wireless communication channel coding. According to the method, on the premise that the index, the log-likelihood ratio and the channel state of the received PAC code are known, the frozen bit and the information bit in the received PAC code are respectively subjected to decoding judgment, the total path metric is updated in real time, whether backtracking is carried out or not and a specific backtracking process is selected according to the total path metric, and finally a decoding result corresponding to the received PAC code is obtained. According to the method, the backtracking operation is newly optimized, the backtracking threshold is newly defined, and the complexity of the Fano decoding algorithm is effectively reduced on the premise that the error correction performance of the algorithm is not greatly reduced.

The invention relates to the technical field of communication and computer instruction execution and processing, in particular to a polar code encoding and decoding algorithm-oriented special instruction set processor and an implementation method, and a vector processor has efficient parallel computing capability. A coding and decoding algorithm of a polar code relates to parallel computing of a large number of log-likelihood ratios, a vector processor of a special instruction set can process a plurality of LLR values at the same time through a parallel processing unit, and the throughput rate is remarkably improved; special instructions such as polarization shuffling and vector G operation instructions are designed for polarization code encoding and decoding and are used for accelerating algorithm operation. The method can achieve the balance among the performance, the energy efficiency and the flexibility, can adapt to the continuous iteration upgrading of the algorithm due to the programmable and reusable characteristics, and has a good application prospect.

A codeword is generated based on a segmentation transform and a Polarization-Assisted Convolutional (PAC) code that includes an outer convolutional code and a polar code, and based on separate encoding of respective different segments of convolutionally encoded input bits according to the polar code. Each segment of the respective segments includes multiple bits of the convolutionally encoded input bits for which the separate encoding of the segment is independent of the separate encoding of other segments. Separate decoding may be applied to segments of such a codeword to decode convolutionally encoded input bits corresponding to the separately encoded segments of the convolutionally encoded input bits.

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit / receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.

A modem chip may include a turbo decoding circuit configured to receive a plurality of channel log likelihood ratios respectively corresponding to a plurality of bits included in a symbol, generate a plurality of first posteriori log likelihood ratios respectively corresponding to the plurality of bits in an Nth iterative loop based on the plurality of channel log likelihood ratios, wherein N is greater than or equals to 1, and generate a first input / output counting value by counting a number of first posteriori log likelihood ratios, among the plurality of first posteriori log likelihood ratios, that differ in sign from the corresponding channel log-likelihood ratios, and a decoding control circuit configured to stop decoding for the plurality of bits in the turbo decoding circuit based on the first input / output counting value being greater than or equal to a first threshold.

Methods and devices are provided in which a channel encoded with a polarization-adjusted convolutional (PAC) code is received. A decoded codeword is generated based at least in part on simplified successive cancellation list (SSCL) decoding performed on the channel via a decoding tree. The decoding tree includes a node that generates candidate codeword output based on predefined processing using convolutional code (CC) state input and channel vector input. A sub-tree of the node remains unprocessed.

A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.

A coding method and apparatus for data communication are provided, and may be applied to a plurality of scenarios such as a metro network, a backbone network, and a data center interconnection. As an example method, a first codeword is formed, where the first codeword includes n image bits and n to-be-transmitted bits. The n image bits are selected from to-be-transmitted bits in m source codewords. The m source codewords are formed before the first codeword. Both n and m are positive integers, and n>m; The n to-be-transmitted bits in the first codeword are sent. The bit in the first codeword can be protected by a plurality of codewords generated at different moments. In addition, the bit in the codeword can be protected by different quantities of codewords.

The present invention discloses an error correction method and system for FPGA, which relates to the technical field of data encoding and decoding, and includes: generating Galois field elements based on the received symbol vector and the primitive polynomial, and calculating the syndrome polynomial through 8-symbol parallel processing; calculating the coefficients of the error location polynomial through the BM iterative algorithm based on the syndrome polynomial; calculating the error location by parallel substituting 10 Galois field elements through the Chien search method based on the error location polynomial; establishing the evaluation polynomial and the error pattern calculation formula, and performing polynomial division calculation through the derivative of the error location polynomial to obtain the error pattern; performing error code judgment based on the error location and the error pattern, and correcting the error symbol through the XOR operation in the Galois field to obtain the updated symbol vector. The present application adopts a parallel pipeline design structure, which enables the FPGA to automatically and real-time correct the received error module data without retransmission, effectively improving the real-time performance and reliability of error correction.

Aspects of the present disclosure provide improved techniques for detecting the presence of RF anomalies and providing for enhanced user control of RF anomaly detection and related actions. Some aspects relate to detecting an RF anomaly by determining, based on a multidimensional encoding of characteristics of an RF signal, that the RF signal is anomalous compared to a baseline of multidimensional encodings of characteristics of RF radiation received in the operating environment. Some aspects relate to controlling RF anomaly detection by initiating an action in response to selection of an option displayed to a user in a graphical user interface in along with an indication of an RF signal determined to be anomalous compared to a baseline. Some aspects relate to identifying a subset of RF data and determining a presence of an RF anomaly corresponding to the subset by comparing a representation of RF radiation to a baseline.

Methods, systems, and devices for coordinated error correction are described. A memory device indicates, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on the comparison, an indication of or based on whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both.

According to certain embodiments, a method by a transmitter is provided for adaptively generating precoder bits for a Polar code. The method includes acquiring at least one configuration parameter upon which a total number of precoder bits depends. The at least one configuration parameter comprising at least one of an information block length K, a code block length N, and / or a code rate R=K / N. The total number of precoder bits is determined, and the precoder bits for a code block are generated according to the determined total number of precoder bits. The precoder bits are placed within the code block.

The present application provides an encoding method, a decoding method, and a communication apparatus. An encoding end device divides an information vector m1 k into a first information vector m1 kc and a second information vector mkc+1 k , and carries out code rate configuration one on the first information vectorm1 kc to obtain a vector m´ 1 Nc ; and carries out convolution transformation on a vector m´ 1 Nc to obtain a code word vector v1 Nc of the convolution code; carries out the code rate configuration one on the code word vector v1 Nc and the second information vector mkc+1 k to obtain a message vector u1 N , and carries out polarization transformation on the message u1 N to obtain a codeword vector c1 N . A coding end device receives a symbol vector y1 N and determines a message vector uˆ 1 N ; to be estimated; according to a node position i of a decoding node uˆi, calls a continuous elimination decoding algorithm or a Fano decoding algorithm to decode a decoding node uˆ 1 N . It is apparent that in the present application, the number of nodes allowed to fall back in the decoding process is reduced, and the complexity of overall decoding can be reduced.