456results about "Error correction/detection by combining multiple code structures" patented technology

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

A cyclic redundancy check bit determination method and system, the method including obtaining an information bit, determining, based on a first correspondence, that a check bit length is L, where L is a natural number, and where the first correspondence includes a correspondence among code length information of to-be-transmitted data including the information bit, length information of the information bit, and the check bit length, and determining a first check bit based on a first cyclic redundancy check (CRC) polynomial, where a length of the first check bit is the check bit length L, where a highest power of terms in the first CRC polynomial is Lmax, where Lmax is a positive integer, and where Lmax is greater than or equal to L.

A device is configured for encoding an input sequence comprising message bits into a codeword using a polar code. The device is configured to sequentially encode each of a plurality of blocks of the input sequence by applying a sliding window to the input sequence, wherein each block of the input sequence is encoded based on an XOR operation of the block and a previous block of the input sequence to obtain a codeword block of the codeword, and sequentially output each obtained codeword block of the codeword.

A method of operating a user equipment (UE) and a base station in a wireless communication system and an apparatus supporting this are disclosed. The method of operating the UE may comprise encoding input data based on a neural network and transmitting the encoded input data to a base station. In this case, the neural network may be determined to be at least one of a real neural network or a complex neural network.

The invention provides a dual-binary Turbo decoding method based on deep learning, and belongs to the technical field of wireless communication. Comprising the following steps: generating a binary random bit stream as original information, and generating a Turbo code sequence through two recursive system convolutional code component encoders; pre-processing the Turbo code sequence, and inputting the pre-processed Turbo code sequence into a bidirectional PNN model for processing to obtain an output feature vector; based on the output feature vector, standardization is carried out through a batch normalization layer, and a decoding result probability value is output by using a full connection layer and a Sigmoid activation function; and on the basis of the decoding result probability value, a Max-Log-MAP algorithm is cascaded with a component decoder of the bidirectional RNN to obtain a decoding result.

Disclosed are a data processing method, an electronic device, and a computer-readable storage medium. The data processing method may include: determining, in response to acquiring at least one source data packet, a first network coding mode for the at least one source data packet according to a pre-configured first network coding parameter; encoding the at least one source data packet according to the first network coding mode to obtain a first encoded data packet; and sending the first encoded data packet to a first receiving end, such that the first receiving end processes the first encoded data packet.

Systems, devices, and methods for encoding information bits for storage, including obtaining information bits; encoding the information bits using an inner code to obtain a plurality of inner code words; encoding the plurality of inner code words using an outer code to generate an outer code word; and storing the outer code word in a storage device, wherein at least one of the inner code and the outer code includes a generalized concatenated code (GCC), and wherein the outer code word includes a hierarchical-GCC (H-GCC) code word.

The invention relates to the technical field of communication and computer instruction execution and processing, in particular to a polar code encoding and decoding algorithm-oriented special instruction set processor and an implementation method, and a vector processor has efficient parallel computing capability. A coding and decoding algorithm of a polar code relates to parallel computing of a large number of log-likelihood ratios, a vector processor of a special instruction set can process a plurality of LLR values at the same time through a parallel processing unit, and the throughput rate is remarkably improved; special instructions such as polarization shuffling and vector G operation instructions are designed for polarization code encoding and decoding and are used for accelerating algorithm operation. The method can achieve the balance among the performance, the energy efficiency and the flexibility, can adapt to the continuous iteration upgrading of the algorithm due to the programmable and reusable characteristics, and has a good application prospect.

A codeword is generated based on a segmentation transform and a Polarization-Assisted Convolutional (PAC) code that includes an outer convolutional code and a polar code, and based on separate encoding of respective different segments of convolutionally encoded input bits according to the polar code. Each segment of the respective segments includes multiple bits of the convolutionally encoded input bits for which the separate encoding of the segment is independent of the separate encoding of other segments. Separate decoding may be applied to segments of such a codeword to decode convolutionally encoded input bits corresponding to the separately encoded segments of the convolutionally encoded input bits.

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit / receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.

A modem chip may include a turbo decoding circuit configured to receive a plurality of channel log likelihood ratios respectively corresponding to a plurality of bits included in a symbol, generate a plurality of first posteriori log likelihood ratios respectively corresponding to the plurality of bits in an Nth iterative loop based on the plurality of channel log likelihood ratios, wherein N is greater than or equals to 1, and generate a first input / output counting value by counting a number of first posteriori log likelihood ratios, among the plurality of first posteriori log likelihood ratios, that differ in sign from the corresponding channel log-likelihood ratios, and a decoding control circuit configured to stop decoding for the plurality of bits in the turbo decoding circuit based on the first input / output counting value being greater than or equal to a first threshold.

Methods and devices are provided in which a channel encoded with a polarization-adjusted convolutional (PAC) code is received. A decoded codeword is generated based at least in part on simplified successive cancellation list (SSCL) decoding performed on the channel via a decoding tree. The decoding tree includes a node that generates candidate codeword output based on predefined processing using convolutional code (CC) state input and channel vector input. A sub-tree of the node remains unprocessed.

A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.

The present invention discloses an error correction method and system for FPGA, which relates to the technical field of data encoding and decoding, and includes: generating Galois field elements based on the received symbol vector and the primitive polynomial, and calculating the syndrome polynomial through 8-symbol parallel processing; calculating the coefficients of the error location polynomial through the BM iterative algorithm based on the syndrome polynomial; calculating the error location by parallel substituting 10 Galois field elements through the Chien search method based on the error location polynomial; establishing the evaluation polynomial and the error pattern calculation formula, and performing polynomial division calculation through the derivative of the error location polynomial to obtain the error pattern; performing error code judgment based on the error location and the error pattern, and correcting the error symbol through the XOR operation in the Galois field to obtain the updated symbol vector. The present application adopts a parallel pipeline design structure, which enables the FPGA to automatically and real-time correct the received error module data without retransmission, effectively improving the real-time performance and reliability of error correction.

Aspects of the present disclosure provide improved techniques for detecting the presence of RF anomalies and providing for enhanced user control of RF anomaly detection and related actions. Some aspects relate to detecting an RF anomaly by determining, based on a multidimensional encoding of characteristics of an RF signal, that the RF signal is anomalous compared to a baseline of multidimensional encodings of characteristics of RF radiation received in the operating environment. Some aspects relate to controlling RF anomaly detection by initiating an action in response to selection of an option displayed to a user in a graphical user interface in along with an indication of an RF signal determined to be anomalous compared to a baseline. Some aspects relate to identifying a subset of RF data and determining a presence of an RF anomaly corresponding to the subset by comparing a representation of RF radiation to a baseline.

Methods, systems, and devices for coordinated error correction are described. A memory device indicates, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on the comparison, an indication of or based on whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both.

The invention discloses a PAC code fast decoding method and system based on a neural network, and relates to the technical field of communication channel coding and decoding, and the method comprises the steps: obtaining a plurality of code words to be decoded and LLR values thereof; classifying according to the LLR value of each code word to be decoded, and determining an optimal decoding algorithm corresponding to each code word to be decoded; based on the LLR value of each code word to be decoded and the optimal decoding algorithm, training a neural network model to obtain a trained neural network model; obtaining a target to-be-decoded codeword and an LLR value thereof, inputting the LLR value of the target to-be-decoded codeword into the trained neural network model, and determining an optimal decoding algorithm corresponding to the target to-be-decoded codeword; and decoding the target to-be-decoded codeword by using the optimal decoding algorithm corresponding to the target to-be-decoded codeword to obtain a decoding result. According to the invention, the decoding complexity of the PAC code can be greatly reduced while the high error correction performance of the PAC code is ensured.

A device in a communication or broadcast system may comprise a memory, at least one transceiver, and at least one processor, comprising processing circuitry, connected to the memory and the at least one transceiver. The device may be configured to: acquire a signal; identify information about at least one dummy parity check (PC) bit among one or more PC bits of the signal on the basis of at least one information bit of the signal and a rate matching size for a polar code; identify a decoder setting for error detection and error correction on the basis of information about the at least one dummy PC bit; and decode the signal based on the decoder setting. The at least one dummy PC bit may include a bit having a fixed value regardless of one or more preceding bits of the decoding among the one or more PC bits.

The invention relates to the technical field of power line communication, and relates to a Turbo decoding method, a decoder, equipment and a storage medium. The Turbo decoding method comprises the following steps: obtaining observation information and iteration parameter information; during the first iteration, determining the state transition probability, the forward probability and the backward probability of the component encoder at each moment according to the observation information; from the second iteration to the last iteration, calculating the state transition probability, the forward probability and the backward probability of the component encoder at each moment according to the observation information and the output result of the last iteration; determining a decision log-likelihood ratio of the component encoder at each moment according to the state transition probability, the forward probability and the backward probability of the component encoder at each moment; and performing hard decision on the decision log-likelihood ratio output by the last iteration to obtain a decoding result. According to the invention, transmission of redundant information can be reduced, and the data processing amount of the decoder is reduced.

The invention discloses a multi-user joint decoding method for a cellular-free large-scale MIMO system based on model-driven deep learning, and the method comprises the steps: building an optimization problem of a simulation combination matrix with maximization of the reachable rate of the cellular-free large-scale MIMO system as a target in a simulation part of data decoding; on the basis of a heuristic algorithm, an optimization target is simplified, an optimization problem is divided into a plurality of sub-problems, the single AP simulation precoding matrix optimization problem is solved one by one, and an optimal simulation combination matrix is obtained; a multi-user joint LDPC decoding algorithm is expanded to a cellular-free large-scale MIMO scene, multi-user joint LDPC decoding is realized based on an MIMO-LDPC-Net decoding network, an input layer of the MIMO-LDPC-Net decoding network generates an initial value as an input of a hidden layer, the hidden layer is formed by stacking modules composed of a first sub-layer, a second sub-layer and an MIMO detection layer, and the first sub-layer, the second sub-layer and the MIMO detection layer are stacked. The output layer generates a log-likelihood ratio of the variable node. Experiments show that compared with a traditional algorithm, the heuristic algorithm and the AI auxiliary joint decoding algorithm have a signal-to-noise ratio gain of 1dB.

The invention discloses a method, a system and a terminal for calculating the word number of a low Hamming weight code of a polarization code, and the method comprises the steps: obtaining a serial offset path metric and a serial offset decoding of a Fano decoder, carrying out the modification processing of the serial offset path metric, and obtaining a target serial offset path metric, modifying the serial offset decoding to obtain a target serial offset decoding; performing node selection according to the target serial cancellation decoding to obtain a target node, and selecting a corresponding target path according to the target serial cancellation path metric; if the target path is a low-weight path, counting the code weight value of the target path to obtain a counting result; and performing path backtracking according to the counting result to obtain a backtracking result, obtaining a corresponding target counting result according to the backtracking result, and obtaining a low Hamming weight code word number according to the target counting result. According to the method, the low Hamming weight code word number is calculated from the perspective of a decoder, and the calculation complexity and the space complexity are lower.

Communication devices, systems and methods for performing multi-layer packet coding (MLPC) in a wireless system are provided. The MLPC includes segmenting a data stream into a plurality of data segments, encoding each of the plurality of data segments into a plurality of forward error correction (FEC) codewords, performing a first exclusive OR (XOR) operation on the plurality of FEC codewords to generate a plurality of first layer parity codewords, performing a second XOR operation on the plurality of first layer parity codewords to generate at least one second layer parity codeword, and transmitting at least one of: the plurality of FEC codewords, the plurality of first layer parity codewords, or the at least one second layer parity codeword.

The present invention relates to a virtualized radio access point, vRAP, as well as to a method of operating the same. With regard to enabling high-performing DU virtualization in order to maximize performance in cloud-based virtualized RANs, the vRAP comprises an encoder / decoder configured to encode / decode transport blocks, TBs, by using iterative codes such as turbo codes or LDPC codes that exchange extrinsic information in each decoding iteration; and a digital signal processor, DSP, pipeline configured to infer information about the decodability of the data of the TBs by exploiting the exchanged extrinsic information.

An interleaving and deinterleaving method suitable for Turbo decoding of 4G 802.16m protocol, aiming at 39 groups of Turbo interleaving parameters supported by 4G 802.16m protocol, the method uses grouped interleaving initial address table Itab_init and fixed interleaving step Istep at each level to realize simplified calculation of interleaving address; uses grouped deinterleaving initial address table Dtab_init and fixed deinterleaving step Dstep at each level to realize simplified calculation of deinterleaving address; uses the mapping relationship between interleaving and deinterleaving to process the interleaver and deinterleaver of Turbo iterative decoding and replace the deinterleaving table and interleaving table between iteration of component decoders. The present application reduces the calculation complexity based on the simplified Turbo decoding interleaving and deinterleaving calculation method, and replaces the interleaving and deinterleaving tables between two component encoders to realize parallel processing of interleaving and deinterleaving processing and Turbo component decoder external information calculation, which reduces the interleaving and deinterleaving delay to equivalent only one processing time slot, is irrelevant to interleaving depth, and improves the decoding rate of Turbo decoding.

Implementations for simplified and efficient error correction code schemes with multiple codewords are provided. One aspect includes a computing system comprising: processing circuitry and memory storing instructions that, during execution, causes the processing circuitry to: encode data comprising user data and metadata in a memory module comprising a plurality of dies by: logically partitioning the memory module into a plurality of partitions; on a first partition: storing a first portion of the user data on one or more memory segments of the first partition; and storing a first cyclic redundancy check (CRC) codeword and the metadata on a memory segment of the first partition different from the one or more memory segments of the first partition, wherein the first CRC codeword is generated based on the first portion of the user data and the metadata; and storing parity data on one of the plurality of dies.

Methods, devices, and systems for controlling a storage system, including: a storage device configured to store a plurality of code words; and at least one processor configured to: obtain information bits; encode the information bits using a first code to obtain a first plurality of code words; encode the first plurality of code words using a second code to generate a second plurality of code words; update the first plurality of code words based on the second plurality of code words to generate an adaptive generalized concatenated code (A-GCC) code word; and store the A-GCC code word in the storage device, wherein each code word of the first plurality of code words is encoded using a different error protection level.

In 5G / New Radio (NR), sidelink communication refers to a channel for communications directly between devices, e.g., user equipment (UEs), without use of traditional uplink or downlink communication channels. Sidelink Control Information (SCI) is separated into two stages (i.e., SCI stage 1 and SCI stage 2) before being transmitted to configure a user device. A method for configuring sidelink communications for a wireless device includes: obtaining SCI Stage 2 payload information; attaching and distributing cyclic redundancy check (CRC) information to the payload information; performing encoding and rate matching (RM) on the payload information; scrambling the encoded and rate matched payload information; performing modulation on the scrambled payload information; determining a resource mapping for the modulated payload information, wherein the modulated payload information is aggregated across two or more slots (e.g., using different processing operations for at least two slots); and transmitting the modulated payload information according to the determined resource mapping.

The present application relates to improved data reliability for extreme temperature usage conditions in data storage. Systems, methods, and apparatus are related to memory devices, such as solid-state drives. In one method, data (e.g., data to be written to an SSD) is received from a host system. The received data is encoded using a first error correction code to generate first parity data. A temperature at which a memory cell of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in a memory storage device that is prone to errors at a predicted higher temperature determined based on output from an artificial neural network using sensor inputs). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cell of the storage device.