852 results about "Correction code" patented technology

The invention discloses an ST code generation method based on graph alignment coding large model and multi-agent collaboration, and the method comprises the steps: receiving an ST code programming demand inputted by a user through a demand analysis module, refining and analyzing the demand based on multiple rounds of interactive conversations of the user and insight agents, and generating a standardized ST code programming demand; the retrieval module receives a standardized ST code programming requirement, and retrieves and obtains related knowledge through a retrieval agent in combination with an ST code knowledge base; and the double-agent collaborative self-correction code generation module receives standardized ST code programming requirements and retrieved related knowledge, a graph alignment coding large model constructed based on a graph neural network and a cross-modal alignment technology serves as a coding agent to cooperatively work with a review agent, ST code structure information is injected into the large model, and a final ST code is generated. According to the method, high-accuracy and high-reliability ST code automatic generation can be realized, and the development efficiency of a PLC program in the industrial control field is improved.

The invention relates to the technical field of hard disk testing and verification, in particular to a multi-thread-based solid state disk reliability automatic testing method and system.The method comprises the steps that firstly, SMART information is deeply analyzed through microsecond-level high-granularity continuous performance monitoring, and multi-thread parallel processing is assisted; according to the method, fine performance fluctuation of the solid state disk under the concurrent load can be quickly captured, a fault mode can be identified, then early warning is realized by utilizing the extracted multi-dimensional features and a machine learning model, and a detailed fault diagnosis report is generated; and through dynamic error correction code strength verification and data integrity verification under pressure, an internal error correction mechanism of the solid state disk is actively detected and optimized. And finally, in combination with prediction reliability modeling, the system can estimate the remaining service life and predict faults, and provides product optimization suggestions for design, manufacturing and firmware optimization of the solid state disk, so that automation, intelligence and full life cycle management of the fault detection reliability of the solid state disk are realized.

The invention provides an intelligent scheduling and control method and device for an integrated energy system. According to the method, power, gas and heat resource operation data are acquired, multi-scale layered modeling is performed according to a time scale and a space scale, and a power resource state space model, a gas resource flow continuity model, a heat resource heat balance model and a multi-energy coupling characteristic constraint model are established; carrying out feature extraction and dimension reduction representation by adopting a deep auto-encoder network; cooperative training of multiple groups of cognitive models is carried out through a split hierarchical federal learning framework, and a global intelligent model is obtained; constructing a neural architecture search network with a hybrid bionic learning rule, setting a hierarchical scheduling target, and generating a hierarchical intelligent scheduling strategy; and a fault-tolerant control mechanism is constructed, and error detection and correction of operation deviation are realized. According to the invention, multi-time scale collaboration, collaborative learning under multi-device group privacy protection and high-reliability fault-tolerant control are realized, and the operation efficiency and reliability of the integrated energy system are remarkably improved.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

The invention discloses a full-stack NPU system supporting a multistage fault mitigation mechanism, and the system comprises a plurality of NPU functional blocks which are used for executing a neural network calculation task; the plurality of hardware protection modules are used for providing error detection and correction capabilities for at least one NPU functional block in the NPU or a data path in the NPU; and a control mechanism for coordinating operation of the plurality of hardware protection modules. By means of the scheme, NPU functional block calculation errors or data path transmission errors caused by hardware faults and the like can be detected and corrected in time, wrong calculation results are prevented from being continuously used or output, and the accuracy of final results is guaranteed. Meanwhile, even if part of hardware breaks down, an error correction mechanism can also cover errors to a large extent, normal operation of the system is maintained, the overall availability and task success rate of the system are improved, and therefore the reliability and robustness of the NPU are remarkably improved.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

The present disclosure describes apparatuses and methods for implementing secure verification of a physical unclonable function (PUF). In various aspects, a PUF verifier generates a PUF reagent value by obtaining a key from a PUF and a message value useful for PUF verification. The PUF verifier computes a digest value of the PUF key and the message value and selects a portion of the hash digest as a PUF reagent value. The PUF verifier writes the PUF reagent value to a non-volatile memory to enable subsequent verification of the PUF. The PUF verifier may also generate error-correction code information for the PUF reagent value and write this information to the non-volatile memory to enable error correction. Upon device hardware reset, the PUF verifier can securely verify PUF operation by generating a PUF key hash digest and comparing the hash digest with the PUF reagent value without exposing the PUF key.

The invention discloses a control gateway for multi-protocol conversion and an equipment access and data transmission method thereof, and belongs to the technical field of protocol conversion, and the control gateway comprises a protocol conversion module which is used for identifying a plurality of communication protocols and carrying out bidirectional conversion on different communication protocols; the data processing module is used for performing error detection and correction on the data and preprocessing the data; the security management module is used for providing multi-level security protection, including encryption, identity authentication, authorization and network security protection, for data transmission and equipment access; the flow control module is used for dynamically adjusting the transmission rate, the priority and the resource allocation of the data according to the network state and the user configuration; the equipment management module is used for managing equipment connected to the gateway; and the user interface module is used for providing an interactive interface and an API (Application Program Interface) of a user and the gateway. Through architecture design and function arrangement, an efficient, safe and flexible solution is provided for communication between networks and devices of different protocols.

The invention discloses an NAND Flash bad block management method and system based on artificial intelligence, and belongs to the technical field of solid-state storage, the method comprises the following steps: S1, carrying out multi-dimensional data acquisition and preprocessing on a bad Page based on preset parameters and preset indexes; s2, inputting the preprocessed multi-dimensional data into a space-time diagram convolutional network model, and outputting the failure probability of each Page; and S3, according to the failure probability obtained in the step S2, a hierarchical isolation strategy is determined, and then error correction code dynamic loading and preventive data migration are carried out. Actual measurement shows that more than 85% of normal Pages can be recycled in a Block with a single bad page, and the effective capacity is improved by 10 times compared with that of a traditional scheme; the overall service life of the chip is prolonged by about 30% by reducing the discarding of the whole chip caused by local damaged pages. The method also has a real-time risk management and control function, the prediction accuracy of the AI model to a potential risk area reaches 92%, and the secondary failure rate is reduced by 70% compared with a static isolation scheme.

A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

The invention relates to the technical field of Internet of Things communication, and provides a low-power-consumption semiconductor communication method based on Internet of Things, which comprises the following steps: acquiring temperature, electromagnetic interference intensity and signal attenuation coefficient data through a multi-mode sensor node, and generating an original environment data set; performing dynamic noise classification on the original environment data set, dividing noise levels and marking noise types; performing hierarchical processing on the data by adopting a multi-stage self-adaptive noise reduction algorithm to generate a preprocessed data set; extracting dynamic characteristic parameters of a communication channel, constructing an energy efficiency prediction model, and dynamically calculating a combination of optimal transmitting frequency, power and modulation order; generating a multi-system modulation signal, superposing a dynamic coding strategy, and adjusting the symbol block length and the error correction code density; and the receiving end analyzes the signal quality index, feeds back the signal quality index to the transmitting end to optimize the parameters and updates the energy efficiency prediction model. According to the invention, the energy efficiency ratio and the anti-interference capability of the Internet of Things communication system can be improved.

A bank of a memory device is divided into column planes. Each column plane is associated with column selects. A portion of a column plane associated with one column select used to store metadata associated with data of the remaining column selects. Both the metadata and the data are provided to an error correction code circuit as a combined code word that provides error correction for both the data and the metadata.

According to the RS error correction decoding method and system compatible with the multiple two-dimensional codes, a finite field and module value corresponding table is defined, a corresponding relation table between power and data is constructed, and the decoding requirements of the multiple two-dimensional code types are met. The method comprises the following steps: acquiring image data by using an image sensor, extracting two-dimensional code data, and converting the two-dimensional code data into a data code word stream; and performing error detection and correction on the two-dimensional code data based on a preset power data corresponding table, including judging whether an error exists or not by calculating a syndrome, if an error is detected, calculating an error position polynomial by using a Berlekamp-Massey algorithm, then positioning an error position by using a Chien search algorithm, and finally calculating an error value by using a Forne algorithm and performing correction. According to the method, the decoding efficiency and the fault-tolerant capability of the two-dimensional code are remarkably improved, the method is suitable for various standards, and especially when the two-dimensional code is partially damaged or an error occurs in data transmission, the original coding information can be effectively recovered.

The invention provides an intelligent instruction execution method, system and device and a medium. The intelligent instruction execution method comprises the steps that current environment state information of a robot and a natural language task instruction input by a user are obtained; generating cue words at least based on the environment state information, the task instruction, a predefined standardized function interface document and a thinking chain example, and inputting the generated cue words into a large language model; the method comprises the following steps: decomposing a task instruction into sub-task sequences by utilizing a large language model, and organizing the decomposed sub-task sequences into complete executable code blocks; performing static logic verification on the code blocks before code execution; if verification is not passed, error description is generated and fed back to the large language model for code correction; and in a code execution stage, if abnormal information is returned after the code is executed, the abnormal information is returned to the large language model, so that the large language model regenerates a correction code according to an abnormal reason. The autonomous decision-making level and the task execution success rate of the robot are improved.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

The invention discloses a river surface flow velocity measurement method and system based on physical constraint and multi-modal fusion, and relates to the technical field of multi-modal data processing, a target area is determined, and river surface image sequence data, depth information and environment data of the target area are acquired; preprocessing the collected data, embedding redundant codes in data representation, and synthesizing to form a basic data set; and based on the basic data set, performing preliminary optical flow estimation on the river surface image sequence data by using an optical flow method. According to the method, optical flow information, depth information and environment data are fused, comprehensive utilization of multi-source data is achieved, in the data fusion process, redundant codes in data representation are combined for error detection and correction, error points in the data are effectively recognized and corrected, the reliability and accuracy of the data are improved, and the data fusion efficiency is improved. And by utilizing a multi-modal data fusion and error correction mechanism, the robustness of the system is remarkably enhanced, so that the system can stably operate in a complex and changeable river environment.

Techniques for applying a generative artificial intelligence (AI) model to identify and correct anomalies in remediation records are disclosed. A system trains and applies a generative AI model to displayed datasets to predict remediation record anomalies. If the system detects the generation of a remediation record in a dataset to reconcile the displayed datasets, the system generates a generative AI prompt that includes the remediation record. The generative AI model generates an output that identifies anomalies in the remediation record and the datasets being reconciled. The generative AI model further generates recommendations for remediating errors in the remediation record.

The invention provides a data processing method, device and system, and relates to the technical field of computers. According to the data processing method, an access logic address of a user in the storage system is converted into a first physical address and a second physical address, an error correction code is read or written according to the first physical address and the second physical address, and the first physical address and the second physical address correspond to different address spaces of different storage particles in a memory. Under the condition that the storage medium fault area has aggregation characteristics and the fault areas of different storage particles are the same or similar, code words of error correction codes are written or read in different address spaces, namely different bit fault rate areas, in different storage particles, so that the code words of the error correction codes are dispersed in the address spaces of the different bit fault rate areas; the maximum error bit number of the code word of the error correction code can be reduced, the error bit number difference of accessing different address spaces is reduced, the waste of error correction code resources is reduced, and the reliability of a memory is improved while the utilization rate of the error correction code resources is improved.

The invention discloses an information storage method based on DNA (deoxyribonucleic acid) coding, which comprises the following steps: converting digital information to be stored into a quaternary code, converting the quaternary code into a DNA sequence consisting of adenine A, cytosine C, guanine G and thymine T according to a preset mapping rule, and expressing an additional information dimension by using a chemical modification state of a nucleotide pair; inserting error detection and correction codes in the DNA sequence every a predetermined number of basic group positions, segmenting the encoded DNA sequence into a plurality of fragments with the length of 100-150bp, and adding a specific recognition sequence and an index marker at two ends of each fragment; a reversible thermosensitive response DNA nanostructure is used as a carrier, DNA fragments are selectively combined to the carrier, and hierarchical storage and rapid retrieval of information are realized through a temperature gradient control system; the DNA storage information density can be remarkably improved, the service life of DNA storage can be remarkably prolonged, and a novel technical path is provided for large-scale, long-term and safe molecular information storage.

The invention discloses a detection and correction device and method based on an RISC-V architecture, belongs to the technical field of processor micro-architectures, and aims to solve the technical problem of how to carry out error detection and correction on an instruction execution process, hardware resources, system reliability, instruction storage, a data path and related system performance in the RISC-V architecture. Comprising a computing core, a cross validation module, a dynamic voting module, a lock step execution module and a hardware multiplexing module, the processor is used for comparing and checking the instruction execution results output by the three calculation cores based on a triple modular redundancy technology and a dynamic voting fault-tolerant technology, and determining the instruction execution result with correct voting through a two-out-of-three voting mode; the lock step execution module is used for controlling lock step execution and assembly line rollback operation of the calculation core; and the hardware multiplexing module is used for multiplexing the same RISC-V pipeline to process normal execution, lock step and rollback operations.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention discloses a multi-level coding modulation transmitting method suitable for a hybrid automatic repeat request system, which belongs to the wireless communication technology and comprises the following steps of: performing high-code-rate channel coding on a first information bit sequence of a transmitting end to obtain a first coding bit sequence, and performing low-bit-rate coding on the second information bit sequence to obtain a second coded bit sequence. In the first transmission, the first coded bit sequence and the second coded bit sequence are combined and pass through an interleaver to obtain a first transmission bit sequence, and the first transmission bit sequence is modulated to obtain a first transmission modulation symbol sequence; and if the first transmission fails, performing channel coding with a lower code rate on the second group of information bit sequences to obtain a first retransmission bit sequence, and modulating the first retransmission bit sequence to obtain a first retransmission modulation symbol sequence. Compared with a BICM scheme with the same spectrum efficiency, the transmitting method provided by the invention has the advantages that the demodulation and error correction code decoding complexity is greatly reduced, and meanwhile, the performance similar to that of an incremental redundancy HARQ is obtained.

A host server computer with an uncorrectable memory error can be repaired without a reboot operation. While initially booting a hypervisor, a special software Application Programming Interface (API) can be loaded between a BIOS System Management Mode (SMM) code and the hypervisor. Once the host server computer is booted and a number of virtual machines are executing, a memory error (e.g., uncorrectable error correction code (UECC)) can occur. In response, the hypervisor calls into the special software API identifying the defective memory rows that the BIOS needs to repair. The BIOS starts a soft Post Package Repair (PPR) process on those rows and gives back control to the hypervisor. When the repair is completed, the hypervisor loads a scrubbing virtual machine and validates that the memory is corrected. After the repair is validated, the hypervisor allows the available partition to take a new customer instance.

The invention belongs to the technical field of quantum communication, and particularly relates to a discrete variable quantum key distribution data coordination method and system based on a code rate adaptive multi-system LDPC code. Aiming at the defect of performance bottleneck of an existing discrete variable quantum key distribution system adopting a binary low-density parity check code in a long-distance and high-noise environment, the invention provides a discrete variable quantum key distribution data coordination method. The method comprises the following steps: preparing and transmitting a quantum state; screening data; error rate estimation and eavesdropping detection; data coordination based on symbol-level code rate adaptation and / or bit-level code rate adaptation; and confidentiality enhancement. According to the method disclosed by the invention, the construction and storage pressure of the system on error correction codes with different code rates is obviously reduced, the robustness of the system under a complex channel condition is enhanced, and efficient and unconditionally safe key distribution is ensured; the eavesdropping attack can be effectively resisted, and the communication security is ensured.

The invention provides a hard disk data processing method and device, electronic equipment and a storage medium. Relates to the technical field of computers. Based on the access frequency of the to-be-processed data, classifying the to-be-processed data to obtain a first type of data and a second type of data; the access frequency of the first type of data is greater than that of the second type of data; in response to the situation that a first storage unit storing the first type of data does not meet a first storage condition, performing data processing on the first type of data based on a first type of error correction code; in response to the situation that a second storage unit storing the second type of data does not meet a second storage condition, performing data processing on the second type of data based on a second type of error correction code; the error correction speed of the first type of error correction codes is higher than that of the second type of error correction codes. Through the application, the service life of the hard disk can be prolonged, and the data processing efficiency is improved.

The invention discloses a spaceflight electromagnetic relay failure early warning and diagnosis method based on multi-physics field coupling, relates to the technical field of spacecraft electrical system reliability monitoring, and is used for solving the problems of lack of comprehensive consideration of multi-physics field coupling characteristics under spaceflight special working conditions and low interference resistance to complex environments. The method comprises the following steps: monitoring a network state, obtaining real-time data, calculating an optimal transmission strategy by using an intelligent regulation and control model, dynamically adjusting a coding mode, adaptively adjusting a transmission rate, further ensuring data integrity through an error code detection and error correction mechanism, and adjusting transmission parameters according to a real-time network condition in combination with packet optimization and flow priority management. Effective recognition and early warning of typical failure modes such as contact adhesion and coil burnout are achieved, and the failure early warning accuracy and diagnosis efficiency of the spaceflight electromagnetic relay in complex environments such as high radiation, extreme temperature and strong vibration are improved.

A memory may include: a memory core; an error correction code (ECC) engine configured to generate an error correction code to be stored in the memory core together with write data by using the write data during an encoding operation, and to correct an error of read data read from the memory core using the error correction code read from the memory core during a decoding operation; and an error determination circuit configured to determine that during the encoding operation, a 1-bit error exists when upper index portions of syndromes generated by the ECC engine have odd weights, and to determine that a correctable 2-bit error exists when the upper index portions of the syndromes are one of predetermined even weight patterns.

A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.