366 results about "Correction code" patented technology

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

A bank of a memory device is divided into column planes. Each column plane is associated with column selects. A portion of a column plane associated with one column select used to store metadata associated with data of the remaining column selects. Both the metadata and the data are provided to an error correction code circuit as a combined code word that provides error correction for both the data and the metadata.

The invention provides an intelligent instruction execution method, system and device and a medium. The intelligent instruction execution method comprises the steps that current environment state information of a robot and a natural language task instruction input by a user are obtained; generating cue words at least based on the environment state information, the task instruction, a predefined standardized function interface document and a thinking chain example, and inputting the generated cue words into a large language model; the method comprises the following steps: decomposing a task instruction into sub-task sequences by utilizing a large language model, and organizing the decomposed sub-task sequences into complete executable code blocks; performing static logic verification on the code blocks before code execution; if verification is not passed, error description is generated and fed back to the large language model for code correction; and in a code execution stage, if abnormal information is returned after the code is executed, the abnormal information is returned to the large language model, so that the large language model regenerates a correction code according to an abnormal reason. The autonomous decision-making level and the task execution success rate of the robot are improved.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Techniques for applying a generative artificial intelligence (AI) model to identify and correct anomalies in remediation records are disclosed. A system trains and applies a generative AI model to displayed datasets to predict remediation record anomalies. If the system detects the generation of a remediation record in a dataset to reconcile the displayed datasets, the system generates a generative AI prompt that includes the remediation record. The generative AI model generates an output that identifies anomalies in the remediation record and the datasets being reconciled. The generative AI model further generates recommendations for remediating errors in the remediation record.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention relates to a machine question answering technology, in particular to a code generation and correction method based on multilevel context awareness and memory iteration, which comprises the following steps of: S1, receiving a preliminary fuzzy demand, proposing a clear question and generating a structured demand document according to content supplement and question answer; s2, learning the context of the item and generating an initial code according to a learning result and the structured demand document; s3, running the initial code; s4, monitoring operation, capturing logs, if the operation is successful, ending circulation, and if the operation is not successful, entering S5; s5, analyzing the log and positioning errors; updating the error to a problem pool and a correction history, and triggering a correction request; the positioning error comprises extraction abnormity, files and line numbers; the correction request comprises an error code snippet, error information and a correction history; and S6, analyzing the correction request and generating a correction code, wherein the correction code comprises construction of an enhanced diagnosis prompt word. According to the invention, rapid, efficient and accurate project code generation can be realized.

The invention relates to the technical field of static storage, and particularly discloses an anti-radiation SRAM (Static Random Access Memory) unit, array and storage and calculation integrated system, which realizes the balance of anti-radiation capability and engineering feasibility through the collaborative design of a circuit and the system. A polarity-reinforced RHCIM-16T unit structure is adopted as the core, and directional conductive constraint is introduced, so that complex multi-node flipping is simplified into a single'lock 0 'error, and the error rate is reduced from the source. On the basis, a lightweight single error correction code is combined to form an efficient fault-tolerant mechanism of circuit simplification and SEC coding. According to the scheme, through the design of splitting word lines and the like, logic operations such as AND and NOR are compatible, and stable execution of the storage and calculation integrated function in a radiation environment is ensured. Simulation and experiment results show that the robustness and the expandability of the memory array in the radiation environment can be remarkably enhanced while the relatively low area and the relatively low power consumption overhead are maintained.

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

The embodiment of the invention provides a flash memory testing method, electronic equipment and a computer readable storage medium. The method comprises the following steps: acquiring particle type information of a to-be-detected flash memory product; determining at least one flash memory operation mode according to the particle type information; aiming at any flash memory operation mode, performing erasing operation on each flash memory block in the flash memory product to be detected under a preset temperature condition; under the condition that the flash memory blocks are successfully erased, performing read operation on the flash memory pages in the corresponding flash memory blocks to obtain the total number of error correction codes and the total number of code words; and comparing the error correction code average value with a corresponding preset test threshold value so as to carry out grading screening processing on the corresponding flash memory blocks. According to the scheme of the embodiment of the invention, the test of the flash memory product can be more refined and more accurate.

A memory controller configured to write, read, and erase data for a nonvolatile memory device storing first meta data and first journal data indicating first changes of the first meta data, the memory controller comprising: a buffer memory circuit including a buffer memory and a buffer controller, wherein the buffer memory stores second meta data and second journal data indicating second changes of the second meta data, and wherein the buffer controller controls the buffer memory; and an accelerator managing the first meta data, the second meta data, the first journal data, and the second journal data, wherein the buffer controller includes: a first error correction code (a first ECC) engine configured to correct a first error of first data that includes the second meta data; and a second error correction code (a second ECC) engine configured to correct a second error of second data including the second journal data.

The invention relates to a robust watermarking method of a diffusion model based on an error correction code, which belongs to the technical field of large model watermarking, and comprises the following steps of: encoding a watermark message by using a Reed-Solomon error correction code to generate a code word containing redundancy check information; carrying out randomization processing on the code word to generate a pseudo-random bit stream; embedding the pseudo-random bit stream into a variable of an initial Gaussian potential space of a diffusion model by adopting a distribution preserving sampling technology; and finally, generating an image with a watermark through a denoising process of the diffusion model. When the watermark is extracted, reverse diffusion processing is carried out on an image which is possibly damaged to recover an approximate value of a potential space variable, a code word which is possibly damaged is extracted from the approximate value, and original watermark information is recovered by utilizing the error correction capability of a Reed-Solomon decoder. On the premise of keeping the generation performance, the robustness of the watermark to compression, noise, cutting and other potential tampering attacks is enhanced.

The application provides a nucleic acid sequencing data quality evaluation method and screening method. The difference between a sequencing signal and a corrected signal is used to evaluate base sequencing quality or to screen nucleic acid sequencing data. In particular, the difference between a dephasing corrected signal and an error correction corrected signal is used. This is the first quality evaluation method and screening method specially applicable to error correction code sequencing. The method of the application is also applicable to sequencing data obtained by other sequencing methods, and has a wide range of applications.

The invention relates to the technical field of intelligent chips, in particular to an NAND wear leveling method based on integrated circuit ECC (error correction code) and read delay, which comprises the following steps: acquiring read delay data and error correction code usage amount of a three-layer unit page of a target block in an NAND flash memory chip; on the basis of the read delay increment and the error correction code increment of the middle-layer page, the health index of the target block is calculated by combining the read delay difference value of the middle-layer page and the lower-layer page, the target block is divided into a plurality of health levels, and logic blocks of different health levels are mapped to different physical planes of the NAND flash memory chip; synchronously executing data migration and erasure operations of the plurality of blocks to be migrated by utilizing the parallel erasure capability of the multi-plane architecture for the target block of which the health level is degraded to a preset threshold value; and monitoring the deviation degree between the current read delay and the specification read delay in real time, and selecting the error correction strength grade of the error correction code according to the deviation degree.

According to the memory controller and the microcontroller chip provided by the invention, on the basis of a memory controller architecture with an ECC (Error Correction Code) verification logic module, an intelligent copying control module is additionally added, and when a CPU (Central Processing Unit) reads corresponding contents in a first memory, the corresponding contents in the first memory are copied; according to the method, the soft failure position can be accurately identified through the ECC verification logic module, errors of 1 bit or 2 bit or several bits can be corrected, and when the error correction capability range of ECC verification is exceeded, the error correction requirements of the soft failure position and the system can be corrected by the intelligent copy control module according to the conditions of different ECC verification errors and the condition of the soft failure position. Different error correction modes are selected to process the soft failure in the first memory, and it is not necessary to generate reset to destroy coherent execution of a program when the error correction capability range of ECC verification is exceeded every time, so that quick correction of soft failure errors is realized under different soft failure conditions, the system operation coherence is improved, and the error correction efficiency is improved. And high reliability of system operation is considered, and various reliability demand scenes are covered.

An object of a system according to an embodiment is to automatically correct an error caused by RPA.SOLUTION: A system includes a collection unit, an analysis unit, and a generation unit. The collection unit collects error information. The analysis unit analyzes the error information collected by the collection unit. The generation unit generates a corrected code based on the analysis result obtained by the analysis unit.SELECTED DRAWING: Figure 1

Transformer neural network based decoder for decoding Quantum Error Correction Codes (QECC), comprising, an input layer, a plurality of decoding layers, and an output layer. The input layer is adapted to receive initial noise estimation computed by a noise estimator for noise injected to syndrome bits of codewords encoded using QECC and transmitted over transmission channel(s) subject to interference, and create embeddings for the syndrome bits. The decoding layers adapted to compute an estimated logical operator matrix of each codeword, each comprises a self-attention layer constructed according to a mask indicative of a relation between the embeddings derived from a parity-check matrix of the error correction code. The plurality of decoding layers are trained using a combined loss function directed to minimize LER, BER, and error rate of the noise estimator. The output layer is adapted to produce a vector representing predicted soft error of the codeword's logical operator matrix.

This invention relates to a method, apparatus, and medium for automatically generating test cases by integrating multi-source human programming experience. The method includes: a preparation step: based on a target programming problem P, searching for existing correct human programming code for the target programming problem P, as well as human error submission code and human correction code for each error submission; a multi-dimensional analysis step: obtaining a first analysis result generated by a large language model; a difference analysis step: obtaining a second analysis result generated by the large language model; and a test case generation step: based on the first and second analysis results, generating executable test script construction prompts to obtain a test script generated by the large language model, and running the script to generate test cases for the programming problem P. Compared with existing technologies, this invention has advantages such as significantly improving the discriminative power of test cases.

To provide a system, method and device for managing error corrections for a data storage system.SOLUTION: A data storage system 400 includes a data storage device 410 comprising at least one memory 412 and a memory controller including at least one first error correction code (ECC) decoder 414. The memory controller reads data from the at least one memory, executes an ECC test on the read-out data using the at least one first ECC decoder, and transmits the read-out data to an external device having at least one second ECC decoder for decoding the read-out data in response to a determination that the read-out data has not passed the ECC test. The external device 420 is located external of the data storage device. A second ECC decoder 422 has an ECC function stronger than the first ECC decoder.SELECTED DRAWING: Figure 4

An ECC engine of a semiconductor memory device includes an ECC encoder and an ECC decoder. The ECC encoder generates parity data based on main data based on a primitive polynomial and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page based on an address to generate a syndrome and corrects at least one error bit in the read codeword based on the syndrome by respectively applying different syndromes to a single bit error in the read codeword, adjacent bit errors and non-adjacent bit errors occurring in non-adjacent two memory cells in the target page. The ECC decoder generates the different syndromes based on a parity check matrix generated as a function of the primitive polynomial. The primitive polynomial has an alpha matrix as a solution belonging to a Galois field.

While the error correction capability can be altered by changing the redundancy level, requiring different error correction circuits to achieve this increases the circuit size. [Solution] The communication system according to the disclosed technology comprises a transmitting device having an error correction code generation unit and a receiving device having an error correction unit. The error correction code generation unit selects a k-bit data signal, generates an encoded signal by adding (mk) bits of fixed-value signals to the data signal, and generates an n-bit parity signal from the encoded signal. The transmitting device transmits the data signal and the parity signal to the receiving device. The receiving device receives a k-bit received data signal corresponding to the data signal and an n-bit received parity signal corresponding to the parity signal. The error correction unit performs error correction on the error-correction target signal, which consists of the received data signal, the (mk) bits of fixed-value signals, and the received parity signal.

The present application provides a data storage device and a method for generating a check code, wherein the data storage device comprises a controller and a non-volatile memory, the non-volatile memory is used to store a plurality of instructions, and the controller is used to execute the plurality of instructions to implement the method for generating a check code, which comprises: judging a minimum unit of the non-volatile memory using a check code; dividing the minimum unit into at least two sub-units; and respectively performing error correction code encoding operations on the at least two sub-units to generate sub-check codes. In this way, data storage devices with different capacities have the same decoding capability.

A memory controller manages a refresh. The memory controller is configured to communicate with a memory device including a memory cell array that include of a plurality of word lines may include a scheduler configured to control commands provided to the plurality of word lines, an error correction code engine that has a register including N entries and is configured to store, in the register, a first parameter which includes address information and active number information of N word lines among the plurality of word lines based on counting the number of actives of the plurality of word lines, a comparator configured to compare the first parameter with a threshold parameter, and a refresh management (RFM) decision circuit configured to determine refresh frequency of the plurality of word lines based on results output from the comparator and to generate an RFM command.

A method for memory system initialization to bootstrap error correction code (ECC) regions during system boot is described. The method includes partitioning a memory sub-system into sub-system memory segments. The method also includes using a last level cache coprocessor (LCP) to initialize a first of the sub-system memory segments to provide a first ECC region. The method also includes booting a system through the first ECC region of the memory sub-system. The method also includes using the LCP to initialize remaining ones of the sub-system memory segments during the boot to enable a second ECC region of the memory sub-system.

According to example aspects of the application, an apparatus is provided that is configured to perform outer encoding of data based on an outer error correction code to obtain an outer codeword, perform inner encoding of a segment of the outer codeword based on an inner error correction code to obtain an inner codeword, wherein a codeword length of the inner error correction code is based at least in part on a channel coherence of a wireless communication channel through which the data is to be transmitted, and perform a transmission through the wireless communication channel based at least in part on the inner encoding and the outer encoding.

A system includes a memory controller, multiple memories coupled to the memory controller, and multiple controlling components coupled to the memory controller. The memory controller calculates an error correction code (ECC) syndrome of a first type for a segment of data; stores the segment of data and the ECC syndrome of the first type in a first memory of the multiple memories; receives a request from a controlling component of the multiple controlling components directed to the segment of data, the controlling component implementing an ECC syndrome of a second type; transforms the ECC syndrome of the first type for the segment of data to the ECC syndrome of the second type; detects a number of errors, if any, present in the segment of data; and takes further action depending on how many errors are detected.

Provided are a method, system, and computer program product in whichdata is encoded for a plurality of tracks of a tape of a tape drive, by using an error correction code (ECC) scheme that applies a single code with code word symbols that are at least 10 bits. The code word symbols are interleaved along and across parallel tracks of the tape in the tape drive.

Systems, methods, computer-readable media, and techniques disclosed herein provide for preparing a solution to a problem comprising a constraint on a non-classical computer, comprising: (a) providing a state preparation operation, wherein the state preparation operation comprises at least a portion of an implementation of the problem comprising the constraint on the non-classical computer, wherein the state preparation operation is configured to evolve a quantum register to a solution state; (b) applying a constraint detection operation, the constraint detection operation comprising entangling an ancilla qubit with a set of data qubits; and (c) measuring the ancilla qubit to determine whether a constraint of the problem is satisfied.