1130 results about "Correction code" patented technology

A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.

Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

The invention discloses an ST code generation method based on graph alignment coding large model and multi-agent collaboration, and the method comprises the steps: receiving an ST code programming demand inputted by a user through a demand analysis module, refining and analyzing the demand based on multiple rounds of interactive conversations of the user and insight agents, and generating a standardized ST code programming demand; the retrieval module receives a standardized ST code programming requirement, and retrieves and obtains related knowledge through a retrieval agent in combination with an ST code knowledge base; and the double-agent collaborative self-correction code generation module receives standardized ST code programming requirements and retrieved related knowledge, a graph alignment coding large model constructed based on a graph neural network and a cross-modal alignment technology serves as a coding agent to cooperatively work with a review agent, ST code structure information is injected into the large model, and a final ST code is generated. According to the method, high-accuracy and high-reliability ST code automatic generation can be realized, and the development efficiency of a PLC program in the industrial control field is improved.

The invention relates to the technical field of hard disk testing and verification, in particular to a multi-thread-based solid state disk reliability automatic testing method and system.The method comprises the steps that firstly, SMART information is deeply analyzed through microsecond-level high-granularity continuous performance monitoring, and multi-thread parallel processing is assisted; according to the method, fine performance fluctuation of the solid state disk under the concurrent load can be quickly captured, a fault mode can be identified, then early warning is realized by utilizing the extracted multi-dimensional features and a machine learning model, and a detailed fault diagnosis report is generated; and through dynamic error correction code strength verification and data integrity verification under pressure, an internal error correction mechanism of the solid state disk is actively detected and optimized. And finally, in combination with prediction reliability modeling, the system can estimate the remaining service life and predict faults, and provides product optimization suggestions for design, manufacturing and firmware optimization of the solid state disk, so that automation, intelligence and full life cycle management of the fault detection reliability of the solid state disk are realized.

A system for the temporal ordering of multi-channel data streams, comprising the following: a multi-channel data reception module configured to receive real-time data streams from multiple sources, extract temporal metadata, and detect discrepancies in timestamps; a time synchronization module configured to align data packets using timestamp normalization, adaptive buffering, and AI-based predictive modeling; an AI-powered predictive modeling module trained to estimate missing or delayed timestamps and to reorder out-of-order data packets based on learned patterns; an adaptive buffer module configured to dynamically adjust buffer sizes based on real-time data arrival rates and network conditions; an ordering and output processing module configured to reconstruct the correct order of the data packets and transmit them to a processing or analysis system; and a module for error detection and correction that is configured to detect inconsistencies in timestamps, transmission delays and missing data points, thus ensuring increased reliability of the ordered data sequence.

The invention provides an intelligent scheduling and control method and device for an integrated energy system. According to the method, power, gas and heat resource operation data are acquired, multi-scale layered modeling is performed according to a time scale and a space scale, and a power resource state space model, a gas resource flow continuity model, a heat resource heat balance model and a multi-energy coupling characteristic constraint model are established; carrying out feature extraction and dimension reduction representation by adopting a deep auto-encoder network; cooperative training of multiple groups of cognitive models is carried out through a split hierarchical federal learning framework, and a global intelligent model is obtained; constructing a neural architecture search network with a hybrid bionic learning rule, setting a hierarchical scheduling target, and generating a hierarchical intelligent scheduling strategy; and a fault-tolerant control mechanism is constructed, and error detection and correction of operation deviation are realized. According to the invention, multi-time scale collaboration, collaborative learning under multi-device group privacy protection and high-reliability fault-tolerant control are realized, and the operation efficiency and reliability of the integrated energy system are remarkably improved.

The invention discloses a collaborative operation system and method for a photovoltaic cleaning robot and a carrying robot, relates to the technical field of automatic control, and solves the defects that an existing collaborative operation system is unstable in communication and insufficient in emergency handling capacity. According to the invention, the environmental information of the photovoltaic power station is collected in real time through the environmental perception module, and the reliability of data transmission is ensured through an automatic retransmission request mechanism and error detection and correction codes based on 5G and LoRa communication protocols; communication parameters are adaptively adjusted through the communication self-adjusting module, so that the communication quality is ensured; the path planning module dynamically allocates cleaning tasks and plans an optimal path, the collaborative obstacle avoidance module dynamically adjusts the motion trails of the robots and avoids obstacles, the operation progress tracking module records the operation states of the robots in real time, and comprehensive operation progress information is provided through data processing and visual display. According to the invention, the communication stability, the autonomous decision-making capability and the operation efficiency of the system are obviously improved.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

The invention discloses a full-stack NPU system supporting a multistage fault mitigation mechanism, and the system comprises a plurality of NPU functional blocks which are used for executing a neural network calculation task; the plurality of hardware protection modules are used for providing error detection and correction capabilities for at least one NPU functional block in the NPU or a data path in the NPU; and a control mechanism for coordinating operation of the plurality of hardware protection modules. By means of the scheme, NPU functional block calculation errors or data path transmission errors caused by hardware faults and the like can be detected and corrected in time, wrong calculation results are prevented from being continuously used or output, and the accuracy of final results is guaranteed. Meanwhile, even if part of hardware breaks down, an error correction mechanism can also cover errors to a large extent, normal operation of the system is maintained, the overall availability and task success rate of the system are improved, and therefore the reliability and robustness of the NPU are remarkably improved.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

The present disclosure describes apparatuses and methods for implementing secure verification of a physical unclonable function (PUF). In various aspects, a PUF verifier generates a PUF reagent value by obtaining a key from a PUF and a message value useful for PUF verification. The PUF verifier computes a digest value of the PUF key and the message value and selects a portion of the hash digest as a PUF reagent value. The PUF verifier writes the PUF reagent value to a non-volatile memory to enable subsequent verification of the PUF. The PUF verifier may also generate error-correction code information for the PUF reagent value and write this information to the non-volatile memory to enable error correction. Upon device hardware reset, the PUF verifier can securely verify PUF operation by generating a PUF key hash digest and comparing the hash digest with the PUF reagent value without exposing the PUF key.

The invention belongs to but not limited to the technical field of text extraction, and particularly relates to an automatic construction method and system for a process industry text knowledge extraction dataset. Firstly, based on a word segmentation tool and a TF-IDF algorithm, an unlabeled text in the process industry field is converted into a large language model fine tuning dataset, and a large language model is subjected to fine tuning; the system has specific knowledge of the field; then, generating an initial knowledge extraction sample set with confidence through multi-stage exploration-utilization ratio adjustment based on the fine-tuned large language model; and finally, through a confidence-based large-scale sample set error detection and correction method, obtaining a sample data set which is finally used for domain knowledge extraction model training. Through the low-cost and high-efficiency industrial text knowledge extraction sample set construction and application method, the input-output ratio of resources is increased to the maximum extent, and the construction and application efficiency of an industrial safety knowledge extraction algorithm is improved.

The invention discloses a control gateway for multi-protocol conversion and an equipment access and data transmission method thereof, and belongs to the technical field of protocol conversion, and the control gateway comprises a protocol conversion module which is used for identifying a plurality of communication protocols and carrying out bidirectional conversion on different communication protocols; the data processing module is used for performing error detection and correction on the data and preprocessing the data; the security management module is used for providing multi-level security protection, including encryption, identity authentication, authorization and network security protection, for data transmission and equipment access; the flow control module is used for dynamically adjusting the transmission rate, the priority and the resource allocation of the data according to the network state and the user configuration; the equipment management module is used for managing equipment connected to the gateway; and the user interface module is used for providing an interactive interface and an API (Application Program Interface) of a user and the gateway. Through architecture design and function arrangement, an efficient, safe and flexible solution is provided for communication between networks and devices of different protocols.

The invention discloses an NAND Flash bad block management method and system based on artificial intelligence, and belongs to the technical field of solid-state storage, the method comprises the following steps: S1, carrying out multi-dimensional data acquisition and preprocessing on a bad Page based on preset parameters and preset indexes; s2, inputting the preprocessed multi-dimensional data into a space-time diagram convolutional network model, and outputting the failure probability of each Page; and S3, according to the failure probability obtained in the step S2, a hierarchical isolation strategy is determined, and then error correction code dynamic loading and preventive data migration are carried out. Actual measurement shows that more than 85% of normal Pages can be recycled in a Block with a single bad page, and the effective capacity is improved by 10 times compared with that of a traditional scheme; the overall service life of the chip is prolonged by about 30% by reducing the discarding of the whole chip caused by local damaged pages. The method also has a real-time risk management and control function, the prediction accuracy of the AI model to a potential risk area reaches 92%, and the secondary failure rate is reduced by 70% compared with a static isolation scheme.

The invention discloses an LED display screen display encryption method and encryption system, and relates to the technical field of screen display encryption. Comprising a secret key management module which is responsible for generating, distributing and updating secret keys and ensuring safe storage and transmission of the secret keys; the encryption and decryption module is used for realizing encryption and decryption algorithms and supporting multiple encryption strength selections; the data transmission module is responsible for transmitting and receiving encrypted data and comprises an error detection and correction mechanism; and the user interface module provides a user operation interface and has encryption parameter setting and key input functions. According to the invention, through the intelligent key management module, a key generation strategy is dynamically adjusted according to historical data and real-time analysis and prediction of a possible attack mode, so that the security of the key is improved; in combination with an artificial intelligence algorithm, the encryption strength is automatically adjusted according to the environment where the LED display screen is located and the sensitivity of the display content, and the safety and the system resource consumption are balanced.

A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

The invention relates to the technical field of Internet of Things communication, and provides a low-power-consumption semiconductor communication method based on Internet of Things, which comprises the following steps: acquiring temperature, electromagnetic interference intensity and signal attenuation coefficient data through a multi-mode sensor node, and generating an original environment data set; performing dynamic noise classification on the original environment data set, dividing noise levels and marking noise types; performing hierarchical processing on the data by adopting a multi-stage self-adaptive noise reduction algorithm to generate a preprocessed data set; extracting dynamic characteristic parameters of a communication channel, constructing an energy efficiency prediction model, and dynamically calculating a combination of optimal transmitting frequency, power and modulation order; generating a multi-system modulation signal, superposing a dynamic coding strategy, and adjusting the symbol block length and the error correction code density; and the receiving end analyzes the signal quality index, feeds back the signal quality index to the transmitting end to optimize the parameters and updates the energy efficiency prediction model. According to the invention, the energy efficiency ratio and the anti-interference capability of the Internet of Things communication system can be improved.

An example CXL (Compute eXpress Link)-based memory module includes a memory device and a controller. The memory device includes a plurality of volatile memory cells and stores data or reads the stored data. The controller communicates with a host device through a CXL interface and controls the memory device. The controller includes an error correction code (ECC) circuit that generates a first codeword by adding a parity vector generated based on Reed-Solomon encoding to data received from the host device, an error injecting circuit that generates an error symbol and generates a second codeword by injecting the error symbol into at least a portion of the first codeword, and a memory device interface that controls the memory device such that the second codeword where the error symbol is injected is stored in the memory device. The controller determines a number of error symbols to be injected into the second codeword.

A bank of a memory device is divided into column planes. Each column plane is associated with column selects. A portion of a column plane associated with one column select used to store metadata associated with data of the remaining column selects. Both the metadata and the data are provided to an error correction code circuit as a combined code word that provides error correction for both the data and the metadata.

The invention discloses an artificial intelligence acceleration system based on vertical integration of a nonvolatile memory and a logic chip, and belongs to the field of chip integration, one layer or multiple layers of nonvolatile memory chips are vertically integrated on the logic chip, and the multiple layers of nonvolatile memory chips are vertically integrated through bumps, micro bumps or a hybrid bonding process. The multi-layer nonvolatile storage chip is used for storing model data, and the physical distance between the position where the model data is stored and the position where the model data is used in the logic chip is as short as possible. The error correction code (ECC) function in the invention can be put on the NVM and also can be put on the logic chip; when the ECC is placed on the NVM chip, the transmission path is long, and when the ECC is placed on the logic chip, the delay is shorter, and the bandwidth is higher.

According to the RS error correction decoding method and system compatible with the multiple two-dimensional codes, a finite field and module value corresponding table is defined, a corresponding relation table between power and data is constructed, and the decoding requirements of the multiple two-dimensional code types are met. The method comprises the following steps: acquiring image data by using an image sensor, extracting two-dimensional code data, and converting the two-dimensional code data into a data code word stream; and performing error detection and correction on the two-dimensional code data based on a preset power data corresponding table, including judging whether an error exists or not by calculating a syndrome, if an error is detected, calculating an error position polynomial by using a Berlekamp-Massey algorithm, then positioning an error position by using a Chien search algorithm, and finally calculating an error value by using a Forne algorithm and performing correction. According to the method, the decoding efficiency and the fault-tolerant capability of the two-dimensional code are remarkably improved, the method is suitable for various standards, and especially when the two-dimensional code is partially damaged or an error occurs in data transmission, the original coding information can be effectively recovered.

The invention provides an intelligent instruction execution method, system and device and a medium. The intelligent instruction execution method comprises the steps that current environment state information of a robot and a natural language task instruction input by a user are obtained; generating cue words at least based on the environment state information, the task instruction, a predefined standardized function interface document and a thinking chain example, and inputting the generated cue words into a large language model; the method comprises the following steps: decomposing a task instruction into sub-task sequences by utilizing a large language model, and organizing the decomposed sub-task sequences into complete executable code blocks; performing static logic verification on the code blocks before code execution; if verification is not passed, error description is generated and fed back to the large language model for code correction; and in a code execution stage, if abnormal information is returned after the code is executed, the abnormal information is returned to the large language model, so that the large language model regenerates a correction code according to an abnormal reason. The autonomous decision-making level and the task execution success rate of the robot are improved.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

An electronic device may include a reception circuit configured to generate a plurality of reception data bits based on a voltage level of an analog signal received through a link, and to generate a plurality of bit reliability values indicating probabilities of error occurrence of the plurality of reception data bits based on the voltage level of the analog signal, an alignment circuit configured to group the plurality of reception data bits into a plurality of error correction code (ECC) symbols, and to generate a plurality of symbol reliability values indicating probabilities of error occurrence of the plurality of ECC symbols based on the plurality of bit reliability values, and a decoding circuit configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

The invention discloses a river surface flow velocity measurement method and system based on physical constraint and multi-modal fusion, and relates to the technical field of multi-modal data processing, a target area is determined, and river surface image sequence data, depth information and environment data of the target area are acquired; preprocessing the collected data, embedding redundant codes in data representation, and synthesizing to form a basic data set; and based on the basic data set, performing preliminary optical flow estimation on the river surface image sequence data by using an optical flow method. According to the method, optical flow information, depth information and environment data are fused, comprehensive utilization of multi-source data is achieved, in the data fusion process, redundant codes in data representation are combined for error detection and correction, error points in the data are effectively recognized and corrected, the reliability and accuracy of the data are improved, and the data fusion efficiency is improved. And by utilizing a multi-modal data fusion and error correction mechanism, the robustness of the system is remarkably enhanced, so that the system can stably operate in a complex and changeable river environment.

An apparatus comprises a storage configured to store data items associated with error correction codes (ECCs); data retrieval circuitry responsive to a data retrieval request specifying a retrieval address to retrieve a retrieved data item and an associated ECC from a storage location corresponding to the retrieval address; and ECC decoding circuitry to generate a syndrome value by performing an ECC decoding operation on a decoding input value comprising data bits of the retrieved data item, code bits of the associated ECC, and address bits of the retrieval address, and to determine based on the syndrome value whether an error condition has occurred. Each bit of the syndrome value depends on a different combination of bits of the decoding input value. For each data bit of the decoding input value, an odd number of bits of the syndrome value depend on that data bit. For each address bit of the decoding input value, an even number of bits of the syndrome value depend on that address bit.

Techniques for applying a generative artificial intelligence (AI) model to identify and correct anomalies in remediation records are disclosed. A system trains and applies a generative AI model to displayed datasets to predict remediation record anomalies. If the system detects the generation of a remediation record in a dataset to reconcile the displayed datasets, the system generates a generative AI prompt that includes the remediation record. The generative AI model generates an output that identifies anomalies in the remediation record and the datasets being reconciled. The generative AI model further generates recommendations for remediating errors in the remediation record.