607 results about "Correction code" patented technology

The invention discloses an ST code generation method based on graph alignment coding large model and multi-agent collaboration, and the method comprises the steps: receiving an ST code programming demand inputted by a user through a demand analysis module, refining and analyzing the demand based on multiple rounds of interactive conversations of the user and insight agents, and generating a standardized ST code programming demand; the retrieval module receives a standardized ST code programming requirement, and retrieves and obtains related knowledge through a retrieval agent in combination with an ST code knowledge base; and the double-agent collaborative self-correction code generation module receives standardized ST code programming requirements and retrieved related knowledge, a graph alignment coding large model constructed based on a graph neural network and a cross-modal alignment technology serves as a coding agent to cooperatively work with a review agent, ST code structure information is injected into the large model, and a final ST code is generated. According to the method, high-accuracy and high-reliability ST code automatic generation can be realized, and the development efficiency of a PLC program in the industrial control field is improved.

The invention relates to the technical field of hard disk testing and verification, in particular to a multi-thread-based solid state disk reliability automatic testing method and system.The method comprises the steps that firstly, SMART information is deeply analyzed through microsecond-level high-granularity continuous performance monitoring, and multi-thread parallel processing is assisted; according to the method, fine performance fluctuation of the solid state disk under the concurrent load can be quickly captured, a fault mode can be identified, then early warning is realized by utilizing the extracted multi-dimensional features and a machine learning model, and a detailed fault diagnosis report is generated; and through dynamic error correction code strength verification and data integrity verification under pressure, an internal error correction mechanism of the solid state disk is actively detected and optimized. And finally, in combination with prediction reliability modeling, the system can estimate the remaining service life and predict faults, and provides product optimization suggestions for design, manufacturing and firmware optimization of the solid state disk, so that automation, intelligence and full life cycle management of the fault detection reliability of the solid state disk are realized.

The invention provides an intelligent scheduling and control method and device for an integrated energy system. According to the method, power, gas and heat resource operation data are acquired, multi-scale layered modeling is performed according to a time scale and a space scale, and a power resource state space model, a gas resource flow continuity model, a heat resource heat balance model and a multi-energy coupling characteristic constraint model are established; carrying out feature extraction and dimension reduction representation by adopting a deep auto-encoder network; cooperative training of multiple groups of cognitive models is carried out through a split hierarchical federal learning framework, and a global intelligent model is obtained; constructing a neural architecture search network with a hybrid bionic learning rule, setting a hierarchical scheduling target, and generating a hierarchical intelligent scheduling strategy; and a fault-tolerant control mechanism is constructed, and error detection and correction of operation deviation are realized. According to the invention, multi-time scale collaboration, collaborative learning under multi-device group privacy protection and high-reliability fault-tolerant control are realized, and the operation efficiency and reliability of the integrated energy system are remarkably improved.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

A bank of a memory device is divided into column planes. Each column plane is associated with column selects. A portion of a column plane associated with one column select used to store metadata associated with data of the remaining column selects. Both the metadata and the data are provided to an error correction code circuit as a combined code word that provides error correction for both the data and the metadata.

The invention provides an intelligent instruction execution method, system and device and a medium. The intelligent instruction execution method comprises the steps that current environment state information of a robot and a natural language task instruction input by a user are obtained; generating cue words at least based on the environment state information, the task instruction, a predefined standardized function interface document and a thinking chain example, and inputting the generated cue words into a large language model; the method comprises the following steps: decomposing a task instruction into sub-task sequences by utilizing a large language model, and organizing the decomposed sub-task sequences into complete executable code blocks; performing static logic verification on the code blocks before code execution; if verification is not passed, error description is generated and fed back to the large language model for code correction; and in a code execution stage, if abnormal information is returned after the code is executed, the abnormal information is returned to the large language model, so that the large language model regenerates a correction code according to an abnormal reason. The autonomous decision-making level and the task execution success rate of the robot are improved.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

The invention discloses a river surface flow velocity measurement method and system based on physical constraint and multi-modal fusion, and relates to the technical field of multi-modal data processing, a target area is determined, and river surface image sequence data, depth information and environment data of the target area are acquired; preprocessing the collected data, embedding redundant codes in data representation, and synthesizing to form a basic data set; and based on the basic data set, performing preliminary optical flow estimation on the river surface image sequence data by using an optical flow method. According to the method, optical flow information, depth information and environment data are fused, comprehensive utilization of multi-source data is achieved, in the data fusion process, redundant codes in data representation are combined for error detection and correction, error points in the data are effectively recognized and corrected, the reliability and accuracy of the data are improved, and the data fusion efficiency is improved. And by utilizing a multi-modal data fusion and error correction mechanism, the robustness of the system is remarkably enhanced, so that the system can stably operate in a complex and changeable river environment.

Techniques for applying a generative artificial intelligence (AI) model to identify and correct anomalies in remediation records are disclosed. A system trains and applies a generative AI model to displayed datasets to predict remediation record anomalies. If the system detects the generation of a remediation record in a dataset to reconcile the displayed datasets, the system generates a generative AI prompt that includes the remediation record. The generative AI model generates an output that identifies anomalies in the remediation record and the datasets being reconciled. The generative AI model further generates recommendations for remediating errors in the remediation record.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention provides a hard disk data processing method and device, electronic equipment and a storage medium. Relates to the technical field of computers. Based on the access frequency of the to-be-processed data, classifying the to-be-processed data to obtain a first type of data and a second type of data; the access frequency of the first type of data is greater than that of the second type of data; in response to the situation that a first storage unit storing the first type of data does not meet a first storage condition, performing data processing on the first type of data based on a first type of error correction code; in response to the situation that a second storage unit storing the second type of data does not meet a second storage condition, performing data processing on the second type of data based on a second type of error correction code; the error correction speed of the first type of error correction codes is higher than that of the second type of error correction codes. Through the application, the service life of the hard disk can be prolonged, and the data processing efficiency is improved.

The invention discloses a spaceflight electromagnetic relay failure early warning and diagnosis method based on multi-physics field coupling, relates to the technical field of spacecraft electrical system reliability monitoring, and is used for solving the problems of lack of comprehensive consideration of multi-physics field coupling characteristics under spaceflight special working conditions and low interference resistance to complex environments. The method comprises the following steps: monitoring a network state, obtaining real-time data, calculating an optimal transmission strategy by using an intelligent regulation and control model, dynamically adjusting a coding mode, adaptively adjusting a transmission rate, further ensuring data integrity through an error code detection and error correction mechanism, and adjusting transmission parameters according to a real-time network condition in combination with packet optimization and flow priority management. Effective recognition and early warning of typical failure modes such as contact adhesion and coil burnout are achieved, and the failure early warning accuracy and diagnosis efficiency of the spaceflight electromagnetic relay in complex environments such as high radiation, extreme temperature and strong vibration are improved.

The invention discloses an efficient data flow transceiving controller applicable to a multi-core storage and calculation system, which comprises two transmitting controllers and two receiving controllers, and the transmitting controllers and the receiving controllers are arranged on the peripheries of cores and are used for performing data packaging and transmitting and data flow judgment work; wherein the sending controller comprises a configurable asynchronous FIFO (First In First Out), a data packaging unit and an error correction code generating unit; the receiving controller comprises an error correction code decoding unit, a data packet unpacking unit and a microchip detection unit; the flit detection unit is used for detecting information in a head flit to judge whether data meet the calculation requirement of the current core particle or not, and if the data do not belong to the task range of the current core particle, the data are redirected to the sending controller through a bypass transmission mechanism. According to the application, the transmission speed of the data stream among different core particles is improved, and the data stream can be dynamically planned and transmitted according to the preset rule by constructing the efficient data transceiving controller.

The invention relates to the technical field of medical informatics, in particular to a method for determining a drug code, which comprises the following steps of: acquiring a specification text, a chemical structure, an active component and target information, and integrating into task input; respectively extracting a molecular topological vector and a semantic topological vector based on topological coherence, injecting the molecular topological vector and the semantic topological vector into a sparse high-dimensional super-vector, and mapping the sparse high-dimensional super-vector into a continuous vector through binding transformation; generating a preliminary code by using a generative neural network combining diffusion denoising and a converter, and calculating a super-dimensional residual error; constructing a causal model in the pharmacological knowledge graph, and outputting a correction code after residual error calibration; the joint probability variance is evaluated through Monte Carlo discarding, and automatic confirmation, manual recheck or anti-fact search are realized through two-stage threshold values; and writing the combined super vector, the final code and the variance into an experience library, and optimizing the generation network and the causal model at the same time by using a hierarchical Bayesian near-end strategy. According to the invention, the extrapolation capability and interpretability of new drugs are considered, the coding accuracy is obviously improved, and the labor cost is reduced.

The invention relates to a machine question answering technology, in particular to a code generation and correction method based on multilevel context awareness and memory iteration, which comprises the following steps of: S1, receiving a preliminary fuzzy demand, proposing a clear question and generating a structured demand document according to content supplement and question answer; s2, learning the context of the item and generating an initial code according to a learning result and the structured demand document; s3, running the initial code; s4, monitoring operation, capturing logs, if the operation is successful, ending circulation, and if the operation is not successful, entering S5; s5, analyzing the log and positioning errors; updating the error to a problem pool and a correction history, and triggering a correction request; the positioning error comprises extraction abnormity, files and line numbers; the correction request comprises an error code snippet, error information and a correction history; and S6, analyzing the correction request and generating a correction code, wherein the correction code comprises construction of an enhanced diagnosis prompt word. According to the invention, rapid, efficient and accurate project code generation can be realized.

A memory device includes a syndrome calculator configured to generate an error location signal based on first data and an error correction code; an error corrector configured to generate second data by correcting an error in the first data according to the error location signal; and a data mask (DM) calculation circuit configured to generate a DM signal according to logic high bits of the first data and change a logic level of the DM signal according to at least one of an increase signal and a decrease signal, by activating the increase signal when an error bit is detected in logic low bits of the first data and activating the decrease signal when the error bit is detected in the logic high bits of the first data, based on the error location signal.

The invention relates to the technical field of static storage, and particularly discloses an anti-radiation SRAM (Static Random Access Memory) unit, array and storage and calculation integrated system, which realizes the balance of anti-radiation capability and engineering feasibility through the collaborative design of a circuit and the system. A polarity-reinforced RHCIM-16T unit structure is adopted as the core, and directional conductive constraint is introduced, so that complex multi-node flipping is simplified into a single'lock 0 'error, and the error rate is reduced from the source. On the basis, a lightweight single error correction code is combined to form an efficient fault-tolerant mechanism of circuit simplification and SEC coding. According to the scheme, through the design of splitting word lines and the like, logic operations such as AND and NOR are compatible, and stable execution of the storage and calculation integrated function in a radiation environment is ensured. Simulation and experiment results show that the robustness and the expandability of the memory array in the radiation environment can be remarkably enhanced while the relatively low area and the relatively low power consumption overhead are maintained.

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

The embodiment of the invention provides a flash memory testing method, electronic equipment and a computer readable storage medium. The method comprises the following steps: acquiring particle type information of a to-be-detected flash memory product; determining at least one flash memory operation mode according to the particle type information; aiming at any flash memory operation mode, performing erasing operation on each flash memory block in the flash memory product to be detected under a preset temperature condition; under the condition that the flash memory blocks are successfully erased, performing read operation on the flash memory pages in the corresponding flash memory blocks to obtain the total number of error correction codes and the total number of code words; and comparing the error correction code average value with a corresponding preset test threshold value so as to carry out grading screening processing on the corresponding flash memory blocks. According to the scheme of the embodiment of the invention, the test of the flash memory product can be more refined and more accurate.

A memory controller configured to write, read, and erase data for a nonvolatile memory device storing first meta data and first journal data indicating first changes of the first meta data, the memory controller comprising: a buffer memory circuit including a buffer memory and a buffer controller, wherein the buffer memory stores second meta data and second journal data indicating second changes of the second meta data, and wherein the buffer controller controls the buffer memory; and an accelerator managing the first meta data, the second meta data, the first journal data, and the second journal data, wherein the buffer controller includes: a first error correction code (a first ECC) engine configured to correct a first error of first data that includes the second meta data; and a second error correction code (a second ECC) engine configured to correct a second error of second data including the second journal data.

The invention relates to a robust watermarking method of a diffusion model based on an error correction code, which belongs to the technical field of large model watermarking, and comprises the following steps of: encoding a watermark message by using a Reed-Solomon error correction code to generate a code word containing redundancy check information; carrying out randomization processing on the code word to generate a pseudo-random bit stream; embedding the pseudo-random bit stream into a variable of an initial Gaussian potential space of a diffusion model by adopting a distribution preserving sampling technology; and finally, generating an image with a watermark through a denoising process of the diffusion model. When the watermark is extracted, reverse diffusion processing is carried out on an image which is possibly damaged to recover an approximate value of a potential space variable, a code word which is possibly damaged is extracted from the approximate value, and original watermark information is recovered by utilizing the error correction capability of a Reed-Solomon decoder. On the premise of keeping the generation performance, the robustness of the watermark to compression, noise, cutting and other potential tampering attacks is enhanced.

A method of operating a non-volatile memory (NVM) device includes: reading, by a memory controller of the NVM device, first metadata bits and first redundant bits stored in an erase sector of a memory cell array of the NVM device, where the first redundant bits are generated using an error-correction code (ECC) for protection of the first metadata bits; and performing an ECC decoding process for the first metadata bits, which includes: forming a first data frame by filling the first data frame with the first metadata bits, a first number of dummy bits, and the first redundant bits; computing, by the memory controller, a syndrome vector for the first data frame in accordance with the error-correction code; and in response to determining that the syndrome vector comprises a non-zero element, performing, by the memory controller, error correction for the first data frame to obtain decoded first metadata bits.

The present disclosure relates to a device which includes a processor configured to: select, using sensor data, an error correction code from two or more error correction codes, the sensor data representing a physical state of the processor and / or the device; generate channel-coded data by channel-coding input data using the selected error correction code; and provide a representation of the channel-coded data to a transmitter for wireless data transmission.

The application provides a nucleic acid sequencing data quality evaluation method and screening method. The difference between a sequencing signal and a corrected signal is used to evaluate base sequencing quality or to screen nucleic acid sequencing data. In particular, the difference between a dephasing corrected signal and an error correction corrected signal is used. This is the first quality evaluation method and screening method specially applicable to error correction code sequencing. The method of the application is also applicable to sequencing data obtained by other sequencing methods, and has a wide range of applications.

The invention relates to the technical field of intelligent chips, in particular to an NAND wear leveling method based on integrated circuit ECC (error correction code) and read delay, which comprises the following steps: acquiring read delay data and error correction code usage amount of a three-layer unit page of a target block in an NAND flash memory chip; on the basis of the read delay increment and the error correction code increment of the middle-layer page, the health index of the target block is calculated by combining the read delay difference value of the middle-layer page and the lower-layer page, the target block is divided into a plurality of health levels, and logic blocks of different health levels are mapped to different physical planes of the NAND flash memory chip; synchronously executing data migration and erasure operations of the plurality of blocks to be migrated by utilizing the parallel erasure capability of the multi-plane architecture for the target block of which the health level is degraded to a preset threshold value; and monitoring the deviation degree between the current read delay and the specification read delay in real time, and selecting the error correction strength grade of the error correction code according to the deviation degree.

According to the memory controller and the microcontroller chip provided by the invention, on the basis of a memory controller architecture with an ECC (Error Correction Code) verification logic module, an intelligent copying control module is additionally added, and when a CPU (Central Processing Unit) reads corresponding contents in a first memory, the corresponding contents in the first memory are copied; according to the method, the soft failure position can be accurately identified through the ECC verification logic module, errors of 1 bit or 2 bit or several bits can be corrected, and when the error correction capability range of ECC verification is exceeded, the error correction requirements of the soft failure position and the system can be corrected by the intelligent copy control module according to the conditions of different ECC verification errors and the condition of the soft failure position. Different error correction modes are selected to process the soft failure in the first memory, and it is not necessary to generate reset to destroy coherent execution of a program when the error correction capability range of ECC verification is exceeded every time, so that quick correction of soft failure errors is realized under different soft failure conditions, the system operation coherence is improved, and the error correction efficiency is improved. And high reliability of system operation is considered, and various reliability demand scenes are covered.