39 results about "Truth table" patented technology

The invention discloses a logic design system for controller hardware acceleration, which relates to the technical field of controllers and comprises a target column extractor, a long-bit-width parallel comparator, a matrix multiplier and a truth table lookup device. The target column extractor is used for extracting target column data information from a preset page and sending the target column data information to the long-bit-width parallel comparator; the target column extractor does not need to read the column data information one by one, but directly reads the target column data information, so that the reading speed can be increased. Further, the long-bit-width parallel comparator is used for copying the target column data information to the corresponding long-bit-width register according to the data type, obtaining a comparison result according to the comparison operation instruction code and the target column data information, and sending the comparison result to the matrix multiplier; as the long-bit-width parallel comparator can compare the target column data information in parallel, the throughput rate of database calculation can be effectively improved, and the delay rate is reduced.

The invention relates to a Boolean function calculation method and device based on fully homomorphic encryption and electronic equipment, and the method comprises the steps: carrying out the format conversion of each received first type of ciphertext based on a target conversion format, and obtaining at least one second type of ciphertext; constructing a multi-layer cascaded CMUX circuit, and based on a preset logic rule, controlling the multi-layer cascaded CMUX circuit to dynamically select pre-encrypted truth table data by taking the second type ciphertext as a control signal to obtain at least one third type ciphertext; and extracting the third type ciphertext coefficient to obtain at least one fourth type ciphertext, and performing blind rotation operation reconstruction on the fourth type ciphertext to obtain at least one encrypted data. Therefore, the problems of low function calculation efficiency, poor expandability and limited calculation precision in the prior art are solved, the resource utilization rate and the parallel processing capability of fully homomorphic encryption in ciphertext calculation are remarkably improved, and meanwhile, the calculation precision and the safety of encrypted data are ensured.

The application relates to a logic truth table acquisition method and device, electronic equipment and a storage medium, and belongs to the technical field of integrated circuits. The logic truth table acquisition method comprises the following steps: finding a register array from a netlist, wherein the register array comprises a plurality of registers; finding an enabling signal for controlling each register from the netlist; changing the value of an address control signal, and obtaining a logic truth table based on each enabling signal under different address control signals, wherein the logic truth table comprises the corresponding relationship between each enabling signal and the address control signal, and is used for determining the register corresponding to each enabling signal. The method can automatically find the enabling signal related to the register array from the netlist, change the value of the address control signal, obtain the logic truth table based on each enabling signal under different address control signals, and improve the problems of low efficiency and easy errors in manually acquiring the logic truth table of the register array.

The embodiment of the present application discloses a logic circuit truth table determination method, device and electronic equipment, relates to the technical field of electronic circuits, and can quickly extract the truth table of a logic circuit. The method comprises the following steps: based on a first group of input truth values in an input truth value list, input ports of a logic circuit described by a netlist are valued; the input truth value list is generated in advance according to the input ports of the logic circuit described by the netlist; based on the valuation of the input ports, the level value of the output ports of the logic circuit described by the netlist is calculated; it is judged whether the output ports have level values calculated; if the output ports have level values calculated, the calculated level value of the output ports is taken as the output truth value corresponding to the first group of input truth values. The present application is suitable for extracting the truth table of a logic circuit.

The invention discloses a method for constructing a first-order elastic five-spectrum value function based on disjoint linear codes, which is characterized by comprising the following steps of: obtaining a group of disjoint linear codes according to the relation among related knowledge, set parameters and the set parameters of a finite field so as to divide the whole space; on the basis of a group of disjoint linear codes, resetting the value range of parameters, and generating one linear code and one linear code according to the generation principle of the disjoint linear codes; setting two sets to define a support set of a function; constructing a first-order elastic five-spectrum value function by using a one selection mode through giving two definition methods of the function; a truth table and a Walsh spectrum are given according to the defined first-order elastic five-spectrum value function to be depicted and verified, and therefore a Boolean function is constructed to be used for encryption. According to the method, a direct construction method of the first-order elastic five-spectrum value function is researched on the basis of the disjoint linear codes, starting from an existing Boolean function is not needed, application conditions and construction complexity are reduced, and construction efficiency can be improved.

The invention discloses an information flow tracking model generation method and a security verification method for an LUT-level netlist, and the method comprises the steps: obtaining all original signals of each logic unit, obtaining a tag signal, building a new LUT module based on the original signals and the tag signal of the LUT module, obtaining a new truth table of the LUT module, and carrying out the truth verification of the new truth table. Converting the truth table of the new LUT module into a Boolean logic expression to obtain an LUT information flow model; processing the original signal and the tag signal of the primitive by using a gate-level information flow tracking algorithm to obtain a primitive information flow model; obtaining an assign statement information flow model based on the tag signal of the assign statement; and obtaining an information flow model of the LUT-level netlist based on the LUT information flow model, the primitive information flow model and the assign statement information flow model. The technical problem that an accurate information flow model cannot be automatically generated based on the FPGA netlist in the prior art is solved.

The invention belongs to the technical field of knowledge questions and answers, and discloses a large model question and answer method and device based on a logic expression and a knowledge graph. The method comprises the steps of extracting a to-be-queried question from a text input by a user by using a large language model; inputting a to-be-queried question into the trained logic extraction and conversion module to generate a true value expression; inputting the truth value expression into the knowledge graph for query to obtain an effective truth value expression and a corresponding query result; and inputting the effective true value expression, the query result and the to-be-queried question into the large language model to generate a final answer. Through a small-scale large language model, questions and answers with high credibility and good interpretability can be provided for users.

The invention relates to a method for generating a test case meeting functional safety requirements, which comprises the following steps of: extracting input and output information of a tested function through a front end of a compiler; based on the input and output information, constructing a program logic model of the tested function through static analysis and dynamic analysis; based on the program logic model, generating a test case truth table covered by correction condition judgment; generating constraint conditions based on the input and output information and the test case truth table; and based on the constraint condition, generating a test case through a satisfiability model theory solver or a large language model. According to the method, the test case is generated through the logic portrait input and output by the tested function in combination with the satisfaction model theory solver or the large language model, so that the coverage rate, accuracy and adaptability of the test case are improved.

The invention discloses a photon logic gate which comprises (1) electromagnetic waves; (2) lookup table electromagnetic waves which are used as carriers for transmitting data, data addresses and control signals of logic operation and are used for transmitting at least one of the data, the data addresses and the control signals; the carrier signal of the electromagnetic wave comprises at least one of millimeter wave, centimeter wave, sub-6GHz and optical fiber; carrier signals of electromagnetic waves are determined based on application scenarios of the electromagnetic waves, the lookup table is a table based on an internal memory (RAM), corresponding data or results can be quickly obtained through various corresponding truth tables in the lookup table, and an important function of the lookup table is to be used as a logic function generator and a logic function generator. Essentially, the logic function generator stores the content of a truth table, the truth table is obtained through a Boolean expression, the truth tables of various logic gates or combinational logic are filled into an internal memory RAM, and the internal memory RAM has the capability of performing operation according to the logic gates or combinational logic functions. Therefore, when a signal is input for logical operation, the operation that an address is input for table look-up, content corresponding to the address is found out and then output is carried out, and then complex logical operation is completed through repeated transmitting, receiving and processing. The method is a technology for processing information by using electromagnetic waves as a carrier, has the advantages of large bandwidth, low time delay, low power consumption and the like, and can exponentially improve the efficiency of logical operation.

A cause-effect graph generation device according to one aspect of the present disclosure comprises: a requirement analysis unit that uses a specification in which a requirement relating to a development target is described in natural language as input and uses a large language model to generate a condition relating to business logic represented by the specification and a truth table representing a relationship between the authenticity of the condition and the authenticity of results related to the business logic; a logical expression generation unit that uses the condition and the truth table as input and uses the large language model to generate, for each of the results, a logical expression which derives the results from the condition; and a cause-effect graph generation unit that uses the logical expression as input to generate a cause-effect graph which visualizes a relationship between the condition and the results.

The invention discloses a side channel attack-oriented fine-grained security tracking model modeling method and system. The method comprises the following steps of: defining a sensitive tag; constructing a side channel tracking logic formula of the basic logic gate according to the input and output signals and the truth table of the corresponding sensitive tag; logic information in a circuit to be modeled is extracted, and a time label is added to each signal in the logic information; adding the basic logic gate and side channel tracking logic formulas of other gate-level structures to a side channel tracking logic library; mapping the logic information of the circuit to be modeled to a side channel tracking logic library, adding a side channel tracking logic formula for each logic unit of the circuit to be modeled, and generating a safety tracking model; verifying whether all logic units of the security tracking model generate corresponding side channel tracking logic expressions or not; solving the safety tracking model by using a Z3 solver, and generating a leakage path; the method has the advantage that the information leakage path is accurately positioned.

This invention discloses a method and system for inspecting the layout layers of an integrated circuit. The method includes the following steps: obtaining a first truth table for all layers of the integrated circuit; classifying different types of devices according to the first truth table; inspecting the layout according to a first-type specific layer rule for the same type of device in the seed layer region to obtain confirmed first-type specific layer rules; combining the confirmed first-type specific layer rules with second-type specific layer rules for the corresponding type of device in the seed layer region to construct a second truth table; obtaining calculation formulas for each layer in the seed layer region of the corresponding type of device according to the second truth table; extracting the seed layer from the layout according to the calculation formulas; if it cannot be extracted, the layer corresponding to the second-type specific layer rule in the layout has an error; otherwise, it is error-free. This invention greatly improves the efficiency and accuracy of layout inspection.

The present disclosure provides a method, device and storage medium for implementing a user-defined primitive of a sequential logic. The method comprises: receiving a description of the user-defined primitive, the description comprising at least a first input, a second input and an output associated with the first input and the second input; generating a first truth table and a second truth table corresponding to the first input and the second input respectively according to the description, wherein the first truth table comprises a first previous input value and a previous output value of the first input and the second input and the output at a previous time, and a first current input value of the first input at a current time; determining a first element value in the first truth table corresponding to the first previous input value, the previous output value and the first current input value; and determining a current output value of the output of the user-defined primitive at the current time in the first truth table based on the first element value.

The invention provides a self-anti-S box construction method and system based on m-sequence generation and logic optimization, and belongs to the technical field of cryptography and hardware security. The method comprises the following steps: firstly, constructing an n-level linear feedback shift register according to a set S box number n and a primitive polynomial, generating an m sequence in a non-all-zero initial state, and adding an all-zero state at the tail; a self-reverse S box lookup table is constructed through a symmetric mapping strategy, so that the ith element in the sequence and the element at the symmetric position form mapping, and the same S box is used for encryption and decryption. Thirdly, the lookup table serves as a Boolean function truth table, is simplified into a simplest expression through a logic minimization algorithm and is decomposed into a layered logic circuit; during actual processing, N data blocks are converted into a bit plane format from block type storage, then parallel operation is carried out through a hierarchical circuit, and finally a result is transposed back to block type storage. According to the method, the same S box hardware module can be reused in the encryption and decryption process, and hardware resources are remarkably saved.

A neural network system, method and apparatus are provided. A truth table matrix, an index vector and an input data tensor are read from a memory. At least a portion of the input data tensor is flattened into an input data vector. A scatter accumulate instruction is executed on the index vector and the input data vector to generate an intermediate vector. The truth table matrix and the intermediate vector are then multiplied to generate an output data vector.

The application discloses a kind of automatic identification MOS tube gate circuit logic method, device and electronic equipment, the method includes the following steps: S1, check the source-drain sequence of all MOS devices in circuit, and adjust to flip the MOS device that does not comply with connection sequence therein;S2, check whether all pin attributes in circuit are correct, the pin attribute is divided into power supply / ground input pin, signal input pin, signal output pin;S3, calculate circuit diagram truth table: according to the switching characteristic of MOS tube, automatically calculate circuit diagram truth table;S4, truth table is converted into operation logic: call truth table conversion model, and truth table is converted into and or formula logic expression.The application automatically identifies the gate circuit logic formed by MOS tube under integrated circuit reverse analysis, by simulating the analysis logic of experienced engineer, quickly generates truth table to a large number of gate circuits and analyzes, reduces the time of manual analysis, reduces cost, improves the accuracy of circuit analysis.

Some embodiments include an encoder to convert a thermometer code into a binary code output information or a Gray code output information. The encoder supports blind input swapping, such that it provides correct output information without prior knowledge of the input swapping. Some embodiments also include a truth table that has additional rows to describe output information when input information at inputs of the encoder is swapped. The encoder includes symmetrical logic functions with respect to information at its inputs as building blocks.

The invention discloses a gated clock conversion method and device, electronic equipment and a storage medium, and relates to the field of chip development and chip test.The method comprises the steps that each gated clock unit in electronic circuit design is obtained, and each gated clock unit is configured in each field programmable logic gate array; obtaining a truth table of each gated clock unit according to the logic expression of each gated clock unit, and splitting the truth table into different sub-truth tables according to the clock signal value to obtain a target sub-truth table with an inconstant output result; and obtaining a sub-logic expression after the clock signal is deleted according to the target sub-truth table, and obtaining an enable signal of the sequential logic device according to the sub-logic expression. According to the technical scheme provided by the embodiment of the invention, not only is the conversion duration of the gated clock shortened and the logic comprehensive performance of the electronic circuit design greatly improved, but also the conversion complexity of the gated clock is reduced.

The invention belongs to the technical field of transformer power distribution systems, and particularly discloses a multi-transformer interlocking design method based on a digital logic principle, and the method comprises the steps: carrying out the analysis of a two-transformer, three-transformer and four-transformer power distribution system, and giving a logic expression of each circuit breaker based on a truth table and a Carnot diagram; then, concepts of side circuit breakers and middle circuit breakers are provided, and the circuit breakers of the multi-transformer power distribution system are divided into two categories through physical positions. Meanwhile, concepts of virtual circuit breakers and virtual transformers are provided, and side circuit breakers are also converted into intermediate circuit breakers, so that the multi-transformer interlocking design only needs to carry out analysis and discussion aiming at the intermediate circuit breakers. Finally, a double-L-shaped structure diagram is provided, the general logic relation of all the circuit breakers is given based on a logic non-expression, and the method is suitable for interlocking design of a transformer inlet wire circuit breaker and a busbar interconnecting circuit breaker. The method is suitable for interlocking design of any number of transformers, and the design process of multi-transformer interlocking is greatly simplified.

This invention discloses a post-mapping optimization method for RSFQ circuits based on path balancing, comprising: parsing the topological connection relationships of nodes in the netlist and presetting the number of iterations; constructing candidate supergates and calculating P-class truth tables, classifying and storing them after P-class transformations, with each P-class truth table storing only the candidate supergate with the fewest JJs, forming a supergate library; perturbing the node hierarchy of the netlist, randomly assigning logic levels, and inserting DFFs; traversing the netlist in reverse to extract fan-out free cones, calculating Boolean function truth tables and performing P-class transformations, matching equivalent structures, and if the number of JJs in the library is smaller, performing an inverse P-class transformation and replacing them in the netlist; performing retiming optimization on the netlist, deleting D flip-flops and continuing iterations or outputting the final netlist. This method has significant advantages in reducing the number of JJs, reducing DFF overhead, and improving the optimization space and efficiency of the mapped RSFQ circuit netlist.

Disclosed are a method and system for redundancy switch between two controllers for supplementary damping of a governor, relating to the technical field of control methods. The method includes acquiring a participation condition according to an output result, listing the participation condition in a truth value table and supplementing correlation logic; outputting the correlation logic as an image language, and simplifying the image language; and acquiring switch logic by a simplified image language, and transforming the switch logic into a programming language of the controller. A complex control relation can be decomposed in the disclosure, so that the difficulty can be reduced, and a correct and comprehensive control purpose can be achieved. Moreover, the method has universality.

The invention discloses a filtering instruction code generation method applied to a controller, and relates to the technical field of controller logic design. According to the filtering instruction code generation method, a structured query statement input by a user is obtained, then the structured query statement input by the user is processed to obtain a first instruction code, and a second instruction code is generated according to the first instruction code; generating a first truth table according to the logical operation in the first instruction code, and generating a second truth table according to the first truth table; finally, a third instruction code is generated according to the second instruction code, and a permutation matrix is determined according to the third instruction code; and determining the second instruction code, the second truth table and the permutation matrix as a filtering instruction code applied to the controller, and configuring the filtering instruction code applied to the controller into the controller. By the adoption of the technical scheme, the speed of database calculation operation can be increased, and the throughput rate of database calculation can be effectively increased and delay can be effectively reduced for calculation-intensive operation in the database.

A method and system for automatically converting a software rule code specifying a policy rule into a human comprehensible document are disclosed. The method includes receiving the software rule code; obfuscating the software rule code prior to submission to a machine learning (ML) model; decomposing the obfuscated software rule code into at least one then block and at least one when block; performing code logic simplification on the at least one then block for separating the at least one then block into at least one logic and at least one action; creating a truth table using the at least one logic; constructing a decision table by combining the truth table, the at least one when block and the at least one action; and outputting the human comprehensible document for display on the display screen.

The present application provides a kind of function automatic generation method and system based on truth table, including: the scientific law that the relationship of each syntax symbol of logic expression in the problem based on truth table and their distance size in actual processing sequence are irrelevant, the generation semantic rule of logic expression is irrelevant with the result length of Boolean vector function example sampling, as the scientific basis for solving the problem of truth table function automatic generation.Besides, a kind of neural network model of encoder-decoder structure is designed to solve the problem of truth table function generation, the model uses two self-attention mechanism encoders to encode input and output respectively, and uses 1 self-attention mechanism decoder to output corresponding logic expression autoregressively, and uses attention mechanism between encoder and decoder;For solving the problem of truth table function automatic generation, a technical scheme is provided, which achieves better results on the specified data set compared with the mainstream benchmark model at the same period.

The present invention discloses a method for establishing and querying a logical relationship system of an integrated circuit. The method for establishing the logical relationship system includes: traversing all combinational logic devices in the integrated circuit design; creating a signal association table for each combinational logic device; and generating a logical relationship system based on all the signal association tables and all the signals connected to the combinational logic devices in the integrated circuit design. The logical relationship system includes the driving relationships between all the signal association tables and all the signals associated with the combinational logic devices. The present application establishes a logical relationship system containing the logical relationships between signals through the driving relationships between the associated signals of the combinational logic devices and their truth tables. By querying the logical relationship system, the logical relationships between certain signals can be directly and simply known, and thus a better optimization effect can be achieved in the subsequent optimization process based on the logical relationships between certain signals.

The invention discloses a test case generation method and device, electronic equipment, a storage medium and a vehicle, and relates to the technical field of system tests.The test case generation method comprises the steps that a logic expression, variables included in the logic expression and constraint conditions among the variables are obtained; according to the logic expression and the constraint condition, constructing a truth table meeting a preset correction condition judgment coverage test criterion; obtaining a value range of the variable, and generating an assignment table based on the value range and the truth table; and traversing the assignment table line by line, and automatically generating all test cases related to the logic expression. The automatic generation of the test case of the highly coupled system is realized, and the test response speed and coverage are remarkably improved, so that the research and development period is shortened, and the test quality and the automation level are improved.

The invention relates to the technical field of integrated circuits, and discloses a sensitive path judgment method and device based on a truth table, equipment and a medium, and the method comprises the steps: obtaining a target lookup table in a circuit netlist, and truth table data corresponding to the target lookup table; performing binary bit operation on the input combination of the target lookup table to obtain at least one group of verification data; the verification data comprises a verification input combination and a verification output; based on the at least one group of verification data and truth table data, obtaining a sensitivity analysis result; and judging a time sequence arc type of the time sequence path based on a sensitive analysis result. According to the scheme, the binary bit operation is used for processing the input combination of the lookup table, and verification data can be quickly generated; and obtaining a sensitivity analysis result of the lookup table based on the verification data and the truth table data, so that the time sequence arc type of the time sequence path can be efficiently and accurately judged.

The application discloses a method, system and medium for generating a combination logic expression of a decoding component, and the method comprises the following steps: generating a truth table for any wth bit of W bits of a target decoding signal; for an nth possible value of N instruction code possible values, if the wth bit is derived from any xth bit of the nth possible value, changing the value of the xth bit of the nth possible value from 1'bx to 1'b1, keeping the values of other bits unchanged to obtain a new value of the nth possible value, and the new value of the nth possible value corresponds to the value 1'b1 of the wth bit of the target decoding signal; otherwise, the nth possible value corresponds to the value 1'b1 or 1'b0 of the wth bit of the decoding signal; and inputting the corresponding relationship formed by the nth possible value and the value of the wth bit of the target decoding signal into the truth table of the wth bit of the decoding signal. The application can effectively control the size of the truth table and generate an optimized combination logic expression.

Embodiments herein relate to applying a Boolean matrix factorization operation to selected neurons, represented as truth tables, in LUT based neural networks. Applying the Boolean matrix factorization operation replaces the original truth table representing the neuron of the neural network with a simplified, approximated truth table derived from the original truth table. The neural network is then simulated, and the cost of the simulated result, as evaluated by a cost function which may for instance incorporate accuracy and resource cost, is compared to a cost threshold value to decide whether to replace the original neuron with its approximated representation.

The present application discloses a logic design system for controller hardware acceleration, which relates to the field of controller technology, including a target column extractor, a long bit width parallel comparator, a matrix multiplier and a truth table finder; the target column extractor is used to extract target column data information from a preset page, and send the target column data information to the long bit width parallel comparator; since the target column extractor does not need to read the column data information one by one, but directly reads the target column data information, the reading speed can be accelerated. Further, the long bit width parallel comparator is used to copy the target column data information to the corresponding long bit width register according to the data type, and obtain the comparison result according to the comparison operation instruction code and the target column data information, and send the comparison result to the matrix multiplier; since the long bit width parallel comparator can compare the target column data information in parallel, the throughput of database calculation can be effectively improved and the delay rate can be reduced.