5 results about "Truth table" patented technology

A neural network system, method and apparatus are provided. A truth table matrix, an index vector and an input data tensor are read from a memory. At least a portion of the input data tensor is flattened into an input data vector. A scatter accumulate instruction is executed on the index vector and the input data vector to generate an intermediate vector. The truth table matrix and the intermediate vector are then multiplied to generate an output data vector.

The application discloses a kind of automatic identification MOS tube gate circuit logic method, device and electronic equipment, the method includes the following steps: S1, check the source-drain sequence of all MOS devices in circuit, and adjust to flip the MOS device that does not comply with connection sequence therein;S2, check whether all pin attributes in circuit are correct, the pin attribute is divided into power supply / ground input pin, signal input pin, signal output pin;S3, calculate circuit diagram truth table: according to the switching characteristic of MOS tube, automatically calculate circuit diagram truth table;S4, truth table is converted into operation logic: call truth table conversion model, and truth table is converted into and or formula logic expression.The application automatically identifies the gate circuit logic formed by MOS tube under integrated circuit reverse analysis, by simulating the analysis logic of experienced engineer, quickly generates truth table to a large number of gate circuits and analyzes, reduces the time of manual analysis, reduces cost, improves the accuracy of circuit analysis.

This invention discloses a post-mapping optimization method for RSFQ circuits based on path balancing, comprising: parsing the topological connection relationships of nodes in the netlist and presetting the number of iterations; constructing candidate supergates and calculating P-class truth tables, classifying and storing them after P-class transformations, with each P-class truth table storing only the candidate supergate with the fewest JJs, forming a supergate library; perturbing the node hierarchy of the netlist, randomly assigning logic levels, and inserting DFFs; traversing the netlist in reverse to extract fan-out free cones, calculating Boolean function truth tables and performing P-class transformations, matching equivalent structures, and if the number of JJs in the library is smaller, performing an inverse P-class transformation and replacing them in the netlist; performing retiming optimization on the netlist, deleting D flip-flops and continuing iterations or outputting the final netlist. This method has significant advantages in reducing the number of JJs, reducing DFF overhead, and improving the optimization space and efficiency of the mapped RSFQ circuit netlist.

The present application provides a kind of function automatic generation method and system based on truth table, including: the scientific law that the relationship of each syntax symbol of logic expression in the problem based on truth table and their distance size in actual processing sequence are irrelevant, the generation semantic rule of logic expression is irrelevant with the result length of Boolean vector function example sampling, as the scientific basis for solving the problem of truth table function automatic generation.Besides, a kind of neural network model of encoder-decoder structure is designed to solve the problem of truth table function generation, the model uses two self-attention mechanism encoders to encode input and output respectively, and uses 1 self-attention mechanism decoder to output corresponding logic expression autoregressively, and uses attention mechanism between encoder and decoder;For solving the problem of truth table function automatic generation, a technical scheme is provided, which achieves better results on the specified data set compared with the mainstream benchmark model at the same period.

Embodiments herein relate to applying a Boolean matrix factorization operation to selected neurons, represented as truth tables, in LUT based neural networks. Applying the Boolean matrix factorization operation replaces the original truth table representing the neuron of the neural network with a simplified, approximated truth table derived from the original truth table. The neural network is then simulated, and the cost of the simulated result, as evaluated by a cost function which may for instance incorporate accuracy and resource cost, is compared to a cost threshold value to decide whether to replace the original neuron with its approximated representation.