16 results about "Truth table" patented technology

The embodiment of the present application discloses a logic circuit truth table determination method, device and electronic equipment, relates to the technical field of electronic circuits, and can quickly extract the truth table of a logic circuit. The method comprises the following steps: based on a first group of input truth values in an input truth value list, input ports of a logic circuit described by a netlist are valued; the input truth value list is generated in advance according to the input ports of the logic circuit described by the netlist; based on the valuation of the input ports, the level value of the output ports of the logic circuit described by the netlist is calculated; it is judged whether the output ports have level values calculated; if the output ports have level values calculated, the calculated level value of the output ports is taken as the output truth value corresponding to the first group of input truth values. The present application is suitable for extracting the truth table of a logic circuit.

The invention discloses a method for constructing a first-order elastic five-spectrum value function based on disjoint linear codes, which is characterized by comprising the following steps of: obtaining a group of disjoint linear codes according to the relation among related knowledge, set parameters and the set parameters of a finite field so as to divide the whole space; on the basis of a group of disjoint linear codes, resetting the value range of parameters, and generating one linear code and one linear code according to the generation principle of the disjoint linear codes; setting two sets to define a support set of a function; constructing a first-order elastic five-spectrum value function by using a one selection mode through giving two definition methods of the function; a truth table and a Walsh spectrum are given according to the defined first-order elastic five-spectrum value function to be depicted and verified, and therefore a Boolean function is constructed to be used for encryption. According to the method, a direct construction method of the first-order elastic five-spectrum value function is researched on the basis of the disjoint linear codes, starting from an existing Boolean function is not needed, application conditions and construction complexity are reduced, and construction efficiency can be improved.

The invention discloses a photon logic gate which comprises (1) electromagnetic waves; (2) lookup table electromagnetic waves which are used as carriers for transmitting data, data addresses and control signals of logic operation and are used for transmitting at least one of the data, the data addresses and the control signals; the carrier signal of the electromagnetic wave comprises at least one of millimeter wave, centimeter wave, sub-6GHz and optical fiber; carrier signals of electromagnetic waves are determined based on application scenarios of the electromagnetic waves, the lookup table is a table based on an internal memory (RAM), corresponding data or results can be quickly obtained through various corresponding truth tables in the lookup table, and an important function of the lookup table is to be used as a logic function generator and a logic function generator. Essentially, the logic function generator stores the content of a truth table, the truth table is obtained through a Boolean expression, the truth tables of various logic gates or combinational logic are filled into an internal memory RAM, and the internal memory RAM has the capability of performing operation according to the logic gates or combinational logic functions. Therefore, when a signal is input for logical operation, the operation that an address is input for table look-up, content corresponding to the address is found out and then output is carried out, and then complex logical operation is completed through repeated transmitting, receiving and processing. The method is a technology for processing information by using electromagnetic waves as a carrier, has the advantages of large bandwidth, low time delay, low power consumption and the like, and can exponentially improve the efficiency of logical operation.

A cause-effect graph generation device according to one aspect of the present disclosure comprises: a requirement analysis unit that uses a specification in which a requirement relating to a development target is described in natural language as input and uses a large language model to generate a condition relating to business logic represented by the specification and a truth table representing a relationship between the authenticity of the condition and the authenticity of results related to the business logic; a logical expression generation unit that uses the condition and the truth table as input and uses the large language model to generate, for each of the results, a logical expression which derives the results from the condition; and a cause-effect graph generation unit that uses the logical expression as input to generate a cause-effect graph which visualizes a relationship between the condition and the results.

The present disclosure provides a method, device and storage medium for implementing a user-defined primitive of a sequential logic. The method comprises: receiving a description of the user-defined primitive, the description comprising at least a first input, a second input and an output associated with the first input and the second input; generating a first truth table and a second truth table corresponding to the first input and the second input respectively according to the description, wherein the first truth table comprises a first previous input value and a previous output value of the first input and the second input and the output at a previous time, and a first current input value of the first input at a current time; determining a first element value in the first truth table corresponding to the first previous input value, the previous output value and the first current input value; and determining a current output value of the output of the user-defined primitive at the current time in the first truth table based on the first element value.

The invention provides a self-anti-S box construction method and system based on m-sequence generation and logic optimization, and belongs to the technical field of cryptography and hardware security. The method comprises the following steps: firstly, constructing an n-level linear feedback shift register according to a set S box number n and a primitive polynomial, generating an m sequence in a non-all-zero initial state, and adding an all-zero state at the tail; a self-reverse S box lookup table is constructed through a symmetric mapping strategy, so that the ith element in the sequence and the element at the symmetric position form mapping, and the same S box is used for encryption and decryption. Thirdly, the lookup table serves as a Boolean function truth table, is simplified into a simplest expression through a logic minimization algorithm and is decomposed into a layered logic circuit; during actual processing, N data blocks are converted into a bit plane format from block type storage, then parallel operation is carried out through a hierarchical circuit, and finally a result is transposed back to block type storage. According to the method, the same S box hardware module can be reused in the encryption and decryption process, and hardware resources are remarkably saved.

A neural network system, method and apparatus are provided. A truth table matrix, an index vector and an input data tensor are read from a memory. At least a portion of the input data tensor is flattened into an input data vector. A scatter accumulate instruction is executed on the index vector and the input data vector to generate an intermediate vector. The truth table matrix and the intermediate vector are then multiplied to generate an output data vector.

The application discloses a kind of automatic identification MOS tube gate circuit logic method, device and electronic equipment, the method includes the following steps: S1, check the source-drain sequence of all MOS devices in circuit, and adjust to flip the MOS device that does not comply with connection sequence therein;S2, check whether all pin attributes in circuit are correct, the pin attribute is divided into power supply / ground input pin, signal input pin, signal output pin;S3, calculate circuit diagram truth table: according to the switching characteristic of MOS tube, automatically calculate circuit diagram truth table;S4, truth table is converted into operation logic: call truth table conversion model, and truth table is converted into and or formula logic expression.The application automatically identifies the gate circuit logic formed by MOS tube under integrated circuit reverse analysis, by simulating the analysis logic of experienced engineer, quickly generates truth table to a large number of gate circuits and analyzes, reduces the time of manual analysis, reduces cost, improves the accuracy of circuit analysis.

The invention discloses a gated clock conversion method and device, electronic equipment and a storage medium, and relates to the field of chip development and chip test.The method comprises the steps that each gated clock unit in electronic circuit design is obtained, and each gated clock unit is configured in each field programmable logic gate array; obtaining a truth table of each gated clock unit according to the logic expression of each gated clock unit, and splitting the truth table into different sub-truth tables according to the clock signal value to obtain a target sub-truth table with an inconstant output result; and obtaining a sub-logic expression after the clock signal is deleted according to the target sub-truth table, and obtaining an enable signal of the sequential logic device according to the sub-logic expression. According to the technical scheme provided by the embodiment of the invention, not only is the conversion duration of the gated clock shortened and the logic comprehensive performance of the electronic circuit design greatly improved, but also the conversion complexity of the gated clock is reduced.

This invention discloses a post-mapping optimization method for RSFQ circuits based on path balancing, comprising: parsing the topological connection relationships of nodes in the netlist and presetting the number of iterations; constructing candidate supergates and calculating P-class truth tables, classifying and storing them after P-class transformations, with each P-class truth table storing only the candidate supergate with the fewest JJs, forming a supergate library; perturbing the node hierarchy of the netlist, randomly assigning logic levels, and inserting DFFs; traversing the netlist in reverse to extract fan-out free cones, calculating Boolean function truth tables and performing P-class transformations, matching equivalent structures, and if the number of JJs in the library is smaller, performing an inverse P-class transformation and replacing them in the netlist; performing retiming optimization on the netlist, deleting D flip-flops and continuing iterations or outputting the final netlist. This method has significant advantages in reducing the number of JJs, reducing DFF overhead, and improving the optimization space and efficiency of the mapped RSFQ circuit netlist.

Disclosed are a method and system for redundancy switch between two controllers for supplementary damping of a governor, relating to the technical field of control methods. The method includes acquiring a participation condition according to an output result, listing the participation condition in a truth value table and supplementing correlation logic; outputting the correlation logic as an image language, and simplifying the image language; and acquiring switch logic by a simplified image language, and transforming the switch logic into a programming language of the controller. A complex control relation can be decomposed in the disclosure, so that the difficulty can be reduced, and a correct and comprehensive control purpose can be achieved. Moreover, the method has universality.

The present application provides a kind of function automatic generation method and system based on truth table, including: the scientific law that the relationship of each syntax symbol of logic expression in the problem based on truth table and their distance size in actual processing sequence are irrelevant, the generation semantic rule of logic expression is irrelevant with the result length of Boolean vector function example sampling, as the scientific basis for solving the problem of truth table function automatic generation.Besides, a kind of neural network model of encoder-decoder structure is designed to solve the problem of truth table function generation, the model uses two self-attention mechanism encoders to encode input and output respectively, and uses 1 self-attention mechanism decoder to output corresponding logic expression autoregressively, and uses attention mechanism between encoder and decoder;For solving the problem of truth table function automatic generation, a technical scheme is provided, which achieves better results on the specified data set compared with the mainstream benchmark model at the same period.

The application discloses a method, system and medium for generating a combination logic expression of a decoding component, and the method comprises the following steps: generating a truth table for any wth bit of W bits of a target decoding signal; for an nth possible value of N instruction code possible values, if the wth bit is derived from any xth bit of the nth possible value, changing the value of the xth bit of the nth possible value from 1'bx to 1'b1, keeping the values of other bits unchanged to obtain a new value of the nth possible value, and the new value of the nth possible value corresponds to the value 1'b1 of the wth bit of the target decoding signal; otherwise, the nth possible value corresponds to the value 1'b1 or 1'b0 of the wth bit of the decoding signal; and inputting the corresponding relationship formed by the nth possible value and the value of the wth bit of the target decoding signal into the truth table of the wth bit of the decoding signal. The application can effectively control the size of the truth table and generate an optimized combination logic expression.

Embodiments herein relate to applying a Boolean matrix factorization operation to selected neurons, represented as truth tables, in LUT based neural networks. Applying the Boolean matrix factorization operation replaces the original truth table representing the neuron of the neural network with a simplified, approximated truth table derived from the original truth table. The neural network is then simulated, and the cost of the simulated result, as evaluated by a cost function which may for instance incorporate accuracy and resource cost, is compared to a cost threshold value to decide whether to replace the original neuron with its approximated representation.

The invention discloses a logging instrument circuit board fault detecting and positioning method, which comprises the following specific steps: step 1, arranging a plurality of key detection points on an intact standard circuit board, and building a logging instrument circuit board fault detecting device; and step 2, establishing a standard circuit board oscillogram library, performing real-time testing by adopting the logging instrument circuit board fault detection device in the step 1, performing comparative analysis with the standard circuit board oscillogram library, analyzing the logic sequence and the relationship of each key detection point, and establishing a logic judgment fault diagnosis table based on a truth table, so that a fault point can be effectively determined. And if the measurement points are more refined, the fault points and the fault components are accurately judged. The method solves the problems that according to an existing logging instrument circuit board fault detection method, circuit board diagnosis is difficult, and the fault recognition rate is low, operation is easy, and safety is high.

The present application relates to the technical field of integrated circuits, and discloses a sensitive path judgment method, device and equipment based on a truth table and a medium, the method comprising: obtaining a target lookup table in a circuit netlist and truth table data corresponding to the target lookup table; performing a binary bit operation on an input combination of the target lookup table to obtain at least one set of verification data; the verification data comprising a verification input combination and a verification output; obtaining a sensitive analysis result based on the at least one set of verification data and the truth table data; and judging a timing arc type of a timing path based on the sensitive analysis result. The above scheme uses a binary bit operation to process the input combination of the lookup table, which can quickly generate verification data; based on the verification data and the truth table data, the sensitive analysis result of the lookup table is obtained, so that the timing arc type of the timing path can be efficiently and accurately judged.