35 results about "Technology mapping" patented technology

While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.

A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.

A simple SCM (Self Cascode MOSFET) structure to generate a sub-1V reference voltage in the SCM intermediate node. The structure requires only 2 transistors to create a temperature-compensated reference voltage. When sized correctly, the transistors in the SCM will operate both at weak, moderate or strong inversion, and in the saturation region or saturation and triode regions, providing good correspondence and low part to part variation. The following proposal innovates by operating with supply voltages on a broad variation range, from 3.6V through below 1V (sub-1V operation), with bias currents in the range of tens of nA (nano Amperes) and temperature variation smaller than ±1% from −40° C. through 85° C. This is an extremely low cost implementation (in terms of area and complexity), compatible with standard CMOS manufacturing processes, and very robust (in terms of fab-to-fab transference, technology mapping, and also well controlled part-to-part variation).

A technique of minimizes circuit area on programmable logic with fracturable logic elements by using “balancing” in the technology mapping stage of the programmable logic computer-aided-design flow. A fracturable LE can be used for logic implementation in many ways, such as being used as one maximum-sized look-up table (LUT) or multiple smaller LUTs. One of more inputs of the multiple smaller LUTs may be shared. By balancing, this means mean that the technology mapping algorithm is tuned to use more small LUTs and fewer maximum-sized LUTs to implement the circuit. Although this is counterintuitive since the larger LUTs are more effective at absorbing gates, the technique achieves a smaller final circuit area by packing small LUTs into fracturable LEs.

Local searches are provided for improving technology mapping for programmable logic integrated circuits. A local search algorithm is applied to a solution for mapping logic gates in a netlist to lookup tables (LUTs) on a programmable logic IC. The local search algorithm applies a series of local moves to the solution. At each move, a small change to the LUT mapping is proposed, and the change in cost for that LUT mapping change is computed. If the cost is improved, the change is accepted and the LUT mapping is replaced by the changed LUT mapping. Otherwise, the change in solution is either rejected, or accepted with a probability that depends on the cost change. The cost function can be chosen to represent one or more features of the LUT mapping, such as area, speed, power consumption, or a combination thereof.

Valid implementations of functions with programmable logic blocks are efficiently determined by creating an approximation of a hardware configuration of programmable logic blocks to quickly screen out configurations unlikely to provide a valid results. If a configuration passes this first phase, the approximation is refined to search for valid function implementations with the hardware configuration. The approximation and refinement may use a partitioning of function input variables to logic blocks to reduce the search space. Additional conflict clauses may be used to further reduce the search space. Implementations of sample functions or other previously considered functions may be analyzed to identify conflict clauses that are reusable for analyzing other functions. A representation of potential implementations of a function can be subdivided into subsets and analyzed separately. The intersection of the solutions from each subset are valid implementations of the function.

Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions. In some embodiments, this method is performed to map a design to a particular technology library. Some embodiments provide a data storage structure that stores a plurality of sub-networks based on parameters derived from the output functions of the sub-networks.

Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions. In some embodiments, this method is performed to map a design to a particular technology library. Some embodiments provide a data storage structure that stores a plurality of sub-networks based on parameters derived from the output functions of the sub-networks.

Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions. In some embodiments, this method is performed to map a design to a particular technology library. Some embodiments provide a data storage structure that stores a plurality of sub-networks based on parameters derived from the output functions of the sub-networks.

The invention discloses a reusable numerical control technology mapping method for a technology scheme, which aims at solving the technical problem of poor practicality in the existing reusable numerical control technology mapping method. The reusable numerical control technology mapping method adopts the technical scheme that a technology scheme structure model is established by a multi-branch tree type, a technology scheme is used as the guidance, and the reusable numerical control technology is subjected to working position, procedure and step analysis according to the processing and operation attribute information; according to the technology analysis result, the reusable numerical control technology is mapped to the technology scheme, and the technology scheme is used for instructing the reusable numerical control technology to sequence the whole technology, so as to support to generate the reasonable and complete part numerical control technology. The reusable numerical control technology mapping method has the advantages that the technical problems of low sequencing efficiency, sequencing result failing to meet actual processing requirements and the like in the technology sequencing process are effectively solved, and the practicality is good.

Technology mapping techniques for determining whether a function can be implemented using an incomplete lookup table (LUT) are provided. For example, the output of a function is compared to the output of an incomplete LUT for each binary value of the function's input signals and for each binary value of the bits stored in the incomplete LUT. For a LUT that is functionally asymmetric, the process can be repeated for multiple permutations of the input signals with respect to the input terminals of the LUT. As another example, the user function is converted into a network of multiplexers and complete LUTs, which are analyzed to determine if an incomplete LUT can implement the function. As another example, a truth table is constructed for a function. The truth table variables are then tested one by one as candidates for each input position using co-factoring and dependency checking.

The invention discloses an efficient FPGA technology mapping algorithm. Technical mapping is divided into logic optimization and structural optimization. The logic optimization part adopts an AIG model and technologies of balance, rewrite, refactor and the like to optimize a circuit. The structural optimization part adopts a DAG model and comprises three steps of partition generation, partition selection and LUT mapping. For the partition generation, a dynamic planning thought is adopted for quickly generating all k- feasible partitions for each node. For the partition selection, a partition set with a characteristic that a time delay and an area are optimized at the same time is finally selected through multi-time forward traversal and backward traversal iteration based on an iterative heuristic thought with an adaptively changeable iterative frequency. Meanwhile, a node area stream calculation formula is corrected and the randomness of the partition selection is improved. Through the LUT mapping, partition combination generated by the partition selection is mapped into an LUT network.

The invention relates to a technology mapping method for integrated circuits for improved logic cells, which comprises the following steps of: firstly, decomposing a universal combinational logic circuit into circuits consisting of input logic cells 2; then, taking the input logic cell 2 as a node, partitioning the node based on an improved logic cell, and finding out all partitions of the node; taking a partition corresponding to the maximum ratio of the number of nodes covered by each partition PGCN(Propagate Gate Cover Number) to the number of actually-used improved logic cells PRUN(Propagate Resource Usage Number) as the optimal partition; and finally, converting the optimal partition into a corresponding improved logic cell. By using the method provided by the invention, through fully using the structural advantages of the improved logic cells, an improved circuit is more efficient on area and time. The method provided by the invention can be widely applied to technology mapping of integrated circuits.

Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping, without degrading the power, speed or area of the design implementation for PLDs. The method of the algorithm involves performing a high level synthesis of the logic to generate a netlist, performing a multilevel synthesis on the netlist to generate a gate implementation of the netlist; and performing technology mapping on the gate implementation to map the gate implementation to actual resources on the target device. During the high level synthesis of the logic into the netlist, technology mapping is performed on a selected portion of the logic to improve the predictability of the power, area and/or frequency of the logic design without substantially degrading the performance of the power, area and frequency of the logic design.

The invention discloses a technical mapping control method, device and system based on rear-end requirements. The method comprises the steps that a rear-end processing device reads a comprehensive rear netlist generated by a front-end logic comprehensive device and judges whether a technical mapping result in the comprehensive rear netlist is matched with the rear-end requirements or not; when thejudgment result is no, technical mapping guide information is generated and fed back to the front-end logic synthesis device; when the technical mapping guide information fed back by the back-end processing device is received, the front-end logic comprehensive device executes local mapping operation on logic resources in user design according to the technical mapping guide information to obtain anew technical mapping result and updates the new technical mapping result to the comprehensive rear netlist to generate a new comprehensive rear netlist, and the comprehensive rear netlist generatedby the front-end logic comprehensive device is used for being provided for the rear-end processing device. Visibly, by implementing the method and the device, accurate guide information can be provided for technical mapping according to the back-end requirements, the quality of the mapping result is improved, and the matching degree of the mapping result and the back-end requirements can be further improved.