30 results about "Logical element" patented technology

The invention relates to the field of document processing, and particularly provides a document format processing method, system, terminal and medium based on a large language model.The method comprises the steps that a generation instruction containing a target document type and a source material are received, and original text content is generated through the large language model integrating domain knowledge; obtaining a matched structured format template, and analyzing the style rule into a format instruction set; identifying logic elements and hierarchical relationships thereof in the original text based on a natural language processing technology; performing association mapping on the format instruction and the logic element, and performing automatic style rendering by calling a document object model interface to generate an intermediate document with a standard format; and finally, outputting after quality verification. According to the method, an automatic process of content generation and intelligent formatting is constructed, and the document writing efficiency and normalization are improved.

The invention provides a system, method and device for detecting an abnormal call chain and electronic equipment, and the system comprises a node analysis tree construction module, a logic relation graph construction module and an abnormal call automatic detection and dynamic verification module. The node analysis tree construction module is used for performing static analysis on source codes of the to-be-detected program through a node analysis model and integrating logic elements obtained through static analysis according to logic meanings to obtain a node analysis tree; the logic relation graph construction module is used for converting logic information contained in logic elements of a node analysis tree in the to-be-detected program into a logic relation to obtain a logic relation graph; and the abnormal call automatic detection and dynamic verification module is used for detecting and dynamically verifying the abnormal call chain in the to-be-detected program through the logic relation graph stored in the database. Through the method, the effect of accurately detecting the abnormal call chain can be achieved.

According to one embodiment, a document classification apparatus includes a processing circuit. The processing circuit is configured to: acquire text content for each of logical elements for semi-structured document data including text data stored for each of the logical elements; select logical elements from the logical elements and generating logical element sets each including the logical elements; analyze text contents for the respective logical element sets and constructing respective word embedded spaces; select a first word embedded space and a second word embedded space including a common word shared with the first word embedded space from the word embedded spaces, and update the first word embedded space based on similarity to the common word in the second word embedded space; and output a classification result of the document data using the first word embedded space and embedding information of a feature quantity of a classification target.

The invention discloses an XML-based video template language definition method and device, and the method comprises the steps: creating a VTL video template, and setting a plurality of XML attributes for a template element for definition; embedding one or more scene elements in the template element through a parent-child relationship of XML (Extensible Markup Language); various content elements are nested in each scene element; and introducing a plurality of logic elements with the same level as the template element, wrapping the template element and the plurality of logic elements by using a root element, and realizing dynamic logic processing and data binding in cooperation with a dynamic calculation expression so as to generate the VTL video template capable of being analyzed and rendered. Through the method provided by the invention, the VTL completely, accurately and flexibly defines a complex video item as a standardized text file by utilizing the structuralization, extensibility and self-description characteristics of the XML, so that comprehensive description from static layout to dynamic content generation is realized; standardized description of the video content is achieved, high dynamic performance is achieved, secondary editing and cross-terminal unified construction are easy, and the efficiency and flexibility of video production are improved.

The invention relates to a network planning method and device, computer equipment, a storage medium and a program product. The method comprises the following steps: receiving business demand information input by a user, and performing intention analysis on the business demand information to obtain a structured intention object; converting the intention object into a logic element, and adding the logic element into a preset meta-model to trigger a logic element updating event; the meta-model is used for providing semantic standards of logic elements and data elements; responding to the logic element updating event through a co-processing framework, and calling an intelligent mapping engine to convert the logic element into a corresponding data parameter; and filling the data parameters in a data filling interface, and generating a network planning scheme containing the logic elements and the data parameters. By adopting the method, collaboration of a logic arrangement layer and a data filling layer can be realized, and the problem that logic design and data filling are disjointed is solved.

The present application relates to a logic diagram compilation detection method, system, electronic device, and storage medium. The method comprises: obtaining an initial logic diagram to be compiled and extracting the logical elements and logical structure of the initial logic diagram; converting the logical elements in the initial logic diagram into intermediate code based on the logical structure; and determining whether the intermediate code is consistent with the initial logic diagram based on a comparison result between the intermediate code and the initial logic diagram. This application avoids errors in the logic diagram compilation process, ensuring the correct output of the control system. This solves the problem in related technologies of additional losses caused by the process control system failing to output correct results, thereby achieving detection of the logic diagram compilation process.

The purpose is to reduce the burden of ensuring system quality. [Solution] This is a program for causing a computer to execute a first acquisition step of acquiring test code that describes one or more logical elements 2 to be tested and the test content for the one or more logical elements 2, a second acquisition step of acquiring the results of the test using the test code, and a generation step of generating presentation information that indicates the correspondence between the test indicated by the test code and each of the one or more logical elements 2, and the results of the test using the test code.

A system for processing a plurality of concurrent threads comprising: a reconfigurable processing grid, comprising logical elements and a context storage for storing thread contexts, each thread context for one of a plurality of concurrent threads, each implementing a dataflow graph comprising an identified operation; and a hardware processor configured for configuring the at reconfigurable processing grid for: executing a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in the context storage; while waiting for completion of the identified operation by identified logical elements, executing the identified operation of a second thread by the identified logical element; and when execution of the identified operation of the first thread completes: retrieving the runtime context value of the first thread from the context storage; and executing another operation of the first thread.

A system for processing a plurality of concurrent threads comprising: a reconfigurable processing grid, comprising logical elements and a context storage for storing thread contexts, each thread context for one of a plurality of concurrent threads, each implementing a dataflow graph comprising an identified operation; and a hardware processor configured for configuring the at reconfigurable processing grid for: executing a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in the context storage; while waiting for completion of the identified operation by identified logical elements, executing the identified operation of a second thread by the identified logical element; and when execution of the identified operation of the first thread completes: retrieving the runtime context value of the first thread from the context storage; and executing another operation of the first thread.

The invention relates to a virtual test logic model construction method. The method comprises the following steps: step 1, constructing logic elements; 2, constructing a logic unit; and 3, constructing a logic model. According to the technical scheme, the construction process of the virtual test logic model is standardized, organic integration and flexible cooperation of multiple elements in the virtual test logic model are achieved, and the expansibility and reusability of the model in a complex and dynamic test scene are improved.

A software defined (SD) process control system (SDCS) implements controller and other process control-related business logic as logical abstractions (e.g., application layer services executing in containers, VMs, etc.) decoupled from hardware and software computing platform resources. An SD networking layer of the SDCS utilizes process control-specific operating system support services to manage the usage of the computing platform resources and the creation, deletion, modifications, and networking of application layer services with devices disposed in the field environment and with other services, responsive to the requirements and needs of the business logic and dynamically changing conditions of SDCS hardware and / or software assets during run-time of the process plant (such as performance, faults, addition / deletion of hardware and / or software assets, etc.). A visualization system of the SDCS provides a user with a view as to the state of the SDCS as currently configured / running on the computing platform to enable a user to view currently configured interrelationships between logical elements of the control system and other logical and / or physical elements of the control system. The visualization system also provides performance metrics of the system as currently configured to enable a user to understand the operational health of the control system as currently configured.

This invention pertains to the overall design of aircraft equipment systems, specifically a method for rapidly generating functional logic models of aircraft-based equipment systems. By analyzing target scenarios, it defines structured natural language text syntax rules for interconnected logical elements and behavioral rule atomic elements, such as the hierarchical composition of the equipment system, interaction ports, key attributes, and mode transformations. This supports the standardized structured natural language text expression of the system's functional architecture model. Combining the characteristics of aircraft design, it constructs a combined mapping relationship between natural language text descriptions and system architecture models, enabling the direct and rapid conversion of functional logic design elements and models of aircraft equipment systems for target scenarios. This supports model-based optimization of functional logic architecture design. This invention utilizes structured natural language text syntax, a hallmark of the aircraft field, to closely integrate functional logic architecture modeling with classic equipment system design conventions. It is intuitive, concise, and consistent with the characteristics and design process thinking of equipment system design.

The invention belongs to the crossing field of artificial intelligence and software engineering, and discloses an intelligent supervision audit inference code generation method and system based on a knowledge graph and templated mapping. The method comprises the following steps: firstly, constructing a supervision and audit domain knowledge graph comprising laws and regulations, rules, cases, entities, risk nodes and association relationships thereof; secondly, according to a predefined node mapping rule set, various nodes in the map are analyzed into a standardized logic element tuple, a corresponding preset Python code template is called according to the node type, and a point execution function is generated; meanwhile, a control code for describing inference logic between nodes is generated based on a predefined relation mapping rule; and finally, dynamically aggregating related node functions and control codes into an executable complete audit reasoning program according to a dependency relationship among nodes from target entity nodes by utilizing an automatic reasoning chain assembly algorithm based on graph traversal. According to the invention, the intelligent level and response speed of monitoring and auditing work are obviously improved.

A system for processing a plurality of concurrent threads includes a reconfigurable processing grid comprising logic elements and context storage means for storing thread contexts, each thread context corresponding to one of the plurality of concurrent threads, each concurrent thread implementing a dataflow graph comprising identified operations; and a hardware processor configured to configure the reconfigurable processing grid: execute a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in a context storage; when waiting for the identified logic element to complete the identified operation, executing the identified operation of the second thread by the identified logic element; and when execution of the identified operation of the first thread is completed, retrieving a runtime context value of the first thread from the context storage, and executing another operation of the first thread.

The invention provides a sequence control chart configuration editing and layout method and device, a medium and equipment, and the method comprises the steps: obtaining a sequence control chart, obtaining a new operation event based on a control logic needed by a site, and carrying out the validity verification and logic adjustment of the logic of the sequence control chart after the operation event is newly added according to a sequence control chart configuration rule; and sorting all the logic elements according to the logic execution sequence and the configured sequence control graph logic, and carrying out layout on the logic elements according to a sorting result. According to the method, the sequence control chart configuration can be correctly guided, adding guiding of different elements is achieved, correct guiding can be provided for the situation that execution logic is illegal, and the configuration efficiency is improved; and after the sequence control chart logic configuration is completed, the logic elements can be automatically arranged according to the logic execution sequence, so that manual configuration and position adjustment are avoided, and the working efficiency is improved.

Systems and method for generating tunable jitter are disclosed. The system can include a delay circuit having a plurality of stages and configured to receive an input signal. Each stage can include logical elements, and the delay circuit can be configured to transmit at least a first version of the input signal and a second version of the input signal through the stages such that the first version travels through a first path and the second version travels through a second path of the delay circuit. The system can include a controller that is configured to apply a number to the stages and the stages are configured to receive a portion of the number that controls which logical element of the respective stage processes the first and second versions. The system can include a combiner that combines the first version and the second version to form a jittered output signal.

To efficiently verify a control logic including a large number of logic elements without requiring an environment in which a dedicated application is installed.SOLUTION: The present disclosure relates to a control logic analysis device for analyzing a control logic for performing automatic control of plant equipment. The control logic analysis apparatus obtains binary data corresponding to the control logic, and converts the binary data into natural language data by performing decoding processing on the binary data. Based on the converted natural language data, a data frame in which logic element information on logic elements included in the control logic is listed is created.SELECTED DRAWING: Figure 3

The invention provides a primary embedded device, and the device comprises a receiving module which is used for receiving an application file; the application analysis module is used for analyzing the application file; the logic execution module is used for processing the analyzed application file based on a preset logic engine so as to realize application logic of the application file in the primary embedded equipment; wherein the preset logic engine is preset in the primary embedded equipment, and the preset logic engine comprises logic elements and can be used for configuring the logic elements; the level embedded device is not configured with an operating system. A control system and a method of configuring a primary embedded device are also provided.

The invention discloses a special effect processing method, device and system and a storage medium, and the method comprises the steps: analyzing a prop package of a special effect, and obtaining a special effect logic element set of the special effect; matching each special effect logic element in the special effect logic element set with a standard special effect logic element in a special effect performance database; if the matched standard special effect logic elements exist in the special effect performance database, obtaining target element performance information corresponding to the matched standard special effect logic elements in the special effect performance database; determining a performance test result of the special effect according to the target element performance information; wherein the standard special effect logic elements and the corresponding element performance information in the special effect performance database are obtained by performing a dynamic performance test according to the prop package of the reference special effect through a dynamic performance test platform, so that the problem of low test efficiency of the performance test of the special effect is solved, and the accuracy of a performance test result is improved.

A system for processing a plurality of concurrent threads comprising: a reconfigurable processing grid, comprising logical elements and a context storage for storing thread contexts, each thread context for one of a plurality of concurrent threads, each implementing a dataflow graph comprising an identified operation; and a hardware processor configured for configuring the at reconfigurable processing grid for: executing a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in the context storage; while waiting for completion of the identified operation by identified logical elements, executing the identified operation of a second thread by the identified logical element; and when execution of the identified operation of the first thread completes: retrieving the runtime context value of the first thread from the context storage; and executing another operation of the first thread.

A method and system are directed to protecting hardware intellectual property (IP) of hardware designs. The method comprises receiving a hardware locking request comprising a register transfer level (RTL) design file, generating a circuit representation of the RTL design file, wherein the circuit representation comprises a translation of the RTL design file into one or more logic elements. The method may further comprise inserting a plurality of key programmable integrated clock gates (ICGs) into the circuit representation and generating a clock gated and locked netlist based on the insertion of the plurality of key programmable ICGs into the circuit representation.

To provide a system for processing a plurality of concurrent threads.SOLUTION: A system 200 comprises: a reconfigurable processing grid 210 comprising each thread context for one of a plurality of concurrent threads, each implementing a dataflow graph including an identified operation; and a hardware processor 201 configuring the reconfigurable processing grid for: executing a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in a context storage; while waiting for completion of the identified operation by identified logical elements, executing the identified operation of a second thread by the identified logical element; and when execution of the identified operation of the first thread completes: acquiring the runtime context value of the first thread from the context storage; and executing another operation of the first thread.SELECTED DRAWING: Figure 2

Embodiments of the present disclosure relate to methods and systems for facilitating dynamic hardware resource allocation in an active switch. A dynamic resource allocation system in a switch is provided. During operation, the system may represent a first subset of hardware elements of the switch to an operating unit of the switch, the first subset being assigned to the operating unit as a logical element. The system may then determine a request for dynamically reallocating the hardware elements to the operating unit. Accordingly, the system may determine whether reallocation of the hardware elements is feasible in the switch. If reallocation of the hardware elements is feasible, the system may allocate a second subset of the hardware elements to the operating unit during runtime of the switch. The system may then merge the second subset of the hardware elements into the logical element.

The embodiment of the invention provides a breakpoint setting method and device and a breakpoint debugging method and device based on a ladder diagram, and relates to the technical field of programmable logic controllers. The method comprises the steps of displaying a first ladder diagram, obtaining a first structured text code, and determining logic elements capable of setting breakpoints in the displayed first ladder diagram as first logic elements; in response to a breakpoint adding instruction aiming at any first logic element, determining a logic line corresponding to the first logic element aiming at the breakpoint adding instruction as a first logic line based on a preset corresponding relationship between the logic line in the first structured text code and the logic element in the first ladder diagram; a breakpoint is added before the first logic row. According to the embodiment of the invention, a user can add the breakpoint in front of the logic row corresponding to the first logic element needing to add the breakpoint according to own requirements, and flexible setting of the breakpoint of the ladder diagram is realized.

The invention belongs to the field of biological computer technology and DNA nanotechnology, and particularly relates to a logic element based on a DNA nanostructure and application of the logic element in manufacturing of a true random number generator. According to the logic element based on the DNA nano-structure, a two-dimensional cross DNA nano-structure is used as a main body of the element, and the logic element bearing different information is constructed through site programming by utilizing the basic characteristics that the DNA nano-structure is uniform in size, accurate in site programming and rich in extensible side chains; the extensible side chain serves as a sticky tail end to achieve a stable and reliable coaxial physical connection relation between the logic elements, and only when the sticky tail ends between the logic elements have a complementary relation, a dimer or a multimer can be formed through self-assembly, so that when the logic element is applied to manufacturing of a random number generator, the random number generator can be manufactured through self-assembly, and the reliability of the random number generator is greatly improved. It can be guaranteed that the polymer formed by connecting a plurality of cross-shaped origami still has good rigidity, and the correctness of a random generation result is guaranteed.

A system for processing a plurality of concurrent threads comprising: a reconfigurable processing grid, comprising logical elements and a context storage for storing thread contexts, each thread context for one of a plurality of concurrent threads, each implementing a dataflow graph comprising an identified operation; and a hardware processor configured for configuring the at reconfigurable processing grid for: executing a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in the context storage; while waiting for completion of the identified operation by identified logical elements, executing the identified operation of a second thread by the identified logical element; and when execution of the identified operation of the first thread completes: retrieving the runtime context value of the first thread from the context storage; and executing another operation of the first thread.

The present invention discloses a page development and rendering method and device, and relates to the field of computer technology. A specific implementation of the method includes: obtaining multiple logical elements, wherein each logical element corresponds to a category; using multiple logical elements and corresponding categories to construct a logical relationship diagram, the logical relationship diagram represents the page logic; adding corresponding attributes to the logical elements in the logical relationship diagram, the attributes include page rendering information. This implementation reduces the coupling between the developed page and the logic, and the page logic can be realized by constructing a logical relationship diagram through logical elements, which can effectively improve the development efficiency.

To prevent an error from occurring in a logical circuit, and prevent resources for logical operations from being compressed.SOLUTION: A logical circuit (100, 100A) comprises: a plurality of logical elements 30; storages 10, 11, 12, 13 storing a plurality of pieces of configuration data CF0, CF1, CF2, CF3; a circuit reconfiguration unit 23; and a comparison circuit 32. A plurality of first logical elements and a plurality of second logical elements forming a first arithmetic circuit and a second arithmetic circuit on the basis of the pieces of configuration data, and a plurality of first logical elements and a plurality of second logical elements forming a first arithmetic circuit and a second arithmetic circuit on the basis of the other configuration data, are partially different from each other and partially common to each other. When notified that an error occurs, the circuit reconfiguration unit selects another configuration data different from selected configuration data, and executes reconfiguration of at least one of the first arithmetic circuit and the second arithmetic circuit.SELECTED DRAWING: Figure 1

The application belongs to the cross field of artificial intelligence and software engineering, and discloses an intelligent supervision and audit reasoning code generation method and system based on a knowledge graph and a templated mapping. The method first constructs a supervision and audit field knowledge graph containing regulations, rules, cases, entities and risk nodes and their associated relationships. Secondly, through a pre-defined node mapping rule set, various nodes in the graph are parsed into standardized logical element tuples, and a point execution function is generated according to the node type and the corresponding pre-set Python code template. At the same time, control code describing the reasoning logic between nodes is generated based on the pre-defined relationship mapping rules. Finally, using a reasoning chain automatic assembly algorithm based on graph traversal, starting from the target entity node, the related node functions and control code are dynamically aggregated into an executable complete audit reasoning program according to the dependency relationship between nodes. The application significantly improves the intelligent level and response speed of supervision and audit work.

The application provides a sequential control diagram configuration editing and layout method, device, medium and equipment, the method comprises the following steps: acquiring a sequential control diagram, and acquiring a new operation event based on the control logic required on site, and performing legality verification and logic adjustment on the sequential control diagram logic after the newly added operation event according to the sequential control diagram configuration rule; according to the completed sequential control diagram logic, all logic elements are sorted according to the logical execution sequence, and the logic elements are laid out according to the sorting result. The method can correctly guide the sequential control diagram configuration, realize the addition guidance of different elements, give correct guidance in the case of illegal execution logic, improve the configuration efficiency; and after completing the sequential control diagram logic configuration, the logic elements can be automatically laid out according to the logical execution sequence, manual configuration adjustment position is avoided, and the work efficiency is improved.