81results about "Synchronisation error correction" patented technology

The vehicle control system includes an abnormality diagnosis unit for determining whether a synchronization abnormality between a master ECU and a slave ECU has occurred. The abnormality diagnosis unit transmits and receives a signal between the master ECU and the slave ECU and acquires time information. The slave ECU calculates a delay time of transmission based on the acquired time information. Then, the abnormality diagnosis unit first determines whether or not there is a periodic shift. When determining that there is no periodic deviation, the abnormality diagnosis unit determines whether or not there is an offset deviation based on the difference obtained by subtracting the delay time from the second time and the first time. The abnormality diagnosis unit determines that a synchronization abnormality has occurred when it is determined that there is a periodic deviation or when it is determined that there is the offset deviation.

To provide a system for surely authenticating a message, a vehicle and a method.SOLUTION: A system is provided with an authentication part for authenticating a message at least including control data transmitted and received between a plurality of on-vehicle devices and a first counter that is counted each time a power source is turned on by using at least the control data and the first counter in the case of authenticating the message including the control data exchanged between the plurality of on-vehicle devices. The authentication part authenticates a message including a second counter to be incremented over time without including the first counter transmitted and received between the on-vehicle devices, without using the second counter instead of the first counter in the case of confirming whether synchronization is performed between the plurality of on-vehicle devices.SELECTED DRAWING: Figure 3

A light communication system, receiver, and method for synchronizing a receiver with a transmitter so as to decode a data input stream transmitted by the transmitter and received at the receiver. The method includes: receiving a data input stream at a receiver, the data input stream having a first data rate that is set based on a transmitter clock rate; generating a wave; obtaining a phase error between the data input stream and the generated wave; determining a synchronized clock rate by using the phase error to adjust the frequency of the generated wave so as to match the frequency of the generated wave to the transmitter clock rate of the data input stream; and using the synchronized clock rate to decode the data input stream so as to obtain data encoded in the data input stream.

The invention discloses a multi-path frequency-adjustable signal generation system based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of signal generation. The system comprises an adjustable frequency signal generation module, an FPGA register read-write control module, an SPI communication module and a top layer module. The top layer module adopts a generate block statement to realize batch instantiation of a multi-path signal output module, a positioning register mechanism is introduced, and a group of register resources are used for controlling a multi-path output channel, so that the problem of register resource waste caused by repeated instantiation of the module in the traditional design is effectively solved. According to the system, remote configuration of an FPGA internal register by a CPU is achieved through an SPI communication interface, and the frequency-adjustable signal generation module supports independent adjustment of parameters such as frequency, high pulse width and low pulse width. And when the positioning register is matched with a specific output channel and the data updating flag bit is valid, the system accurately sends the characteristic parameters to the corresponding channel, so that the accuracy of each path of signal parameters is ensured. According to the method, the code redundancy and the development time are remarkably reduced, and the system maintainability is improved.

An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

In order to maintain synchronization of wireless communication, a remote wireless device (20) is provided with: a communication unit (120) whereby a synchronization maintenance signal (SM) transmitted from a base wireless device (10) in a transmission cycle (Tt) which is a plurality of times the length of a predetermined cycle (Tu) is received in a reception cycle (Tr) which is a predetermined number (N) of times the length of the transmission cycle (Tt); and a synchronization unit (122) that maintains the synchronization. The predetermined number is an integer of 1 or more. The reception cycle is the sum of a first period (T1) in which the communication unit receives the synchronization maintenance signal and a second period (T2) in which the communication unit does not receive the synchronization maintenance signal. The first period is a period including one or more of the predetermined cycles included in the reception cycle.

The present invention is directed to electrical circuits. In an embodiment, the present invention provides a clock compensation device configured to correct timing discrepancies in differential clock signals. The circuit comprises positive and negative lines with multiple inverters, including crossover inverters that generate correction signals to maintain synchronization between the clock signals. There are other embodiments as well.

Synchronizing time-of-day (TOD) between TOD components includes issuing an order for a plurality of TOD components, each including a local time, an offset, and an effective time as a sum of the local time and the offset. The effective time of a reference TOD component is the reference time to which target TOD component(s) are to be synchronized. The order directs each of the plurality of TOD components to synchronously, at a point in time, snapshot its local time. This provides a snapshot of the effective time of the reference TOD component, and thus the reference time. The synchronizing synchronizes each target TOD component to the reference time by setting the respective offset as a difference between the target TOD component's snapshot local time and the snapshot of the reference time. Based on the synchronizing, the effective times of the plurality of TOD components match and are the reference time.

Embodiments of the present application relate to a method for synchronizing audio data and a data sending end, the method comprising: obtaining first time information of a first sending end and second time information of a second sending end; determining, by using a preset synchronization algorithm, a next sampling time of the first sending end based on the first time information and a sampling period, and determining a next sampling time of the second sending end based on the second time information and the sampling period; controlling the first sending end to collect audio data at the next sampling time of the first sending end, and controlling the second sending end to collect audio data at the next sampling time of the second sending end. Thus, the next sampling times of the first sending end and the second sending end are synchronized by using the preset synchronization algorithm, and then the first sending end and the second sending end are controlled to collect audio data at the synchronized sampling times, so that the synchronization of the sending end in collecting audio data can be improved.

[0009] Embodiments of the present application provide a communication method, a communication device, and a communication system. The communication method applied to a first device includes the steps of: transmitting a first signal to a second device, where the transmitted first signal has a first phase; and receiving a second signal from the second device, where the second signal and the first signal are two signals whose transmission directions are opposite to each other on a first transmission path, and the received second signal has a second phase, and the first and second phases are used to adjust a data signal on the first transmission path. Based on this technical solution, the phase difference between the first and second phases indicates the effect of two bidirectional transmissions on the phase of the first transmission path, and the first and second phases can be used to adjust the data signal to improve the reliability of data signal transmission on the first transmission path.

Clock domain phase adjustment techniques and systems for memory operations are described. In one example, a physical memory is communicatively coupled to a physical layer via a first clock domain and a memory controller is communicatively coupled to the physical layer via a second clock domain that is different than the first clock domain. A buffer is implemented in the physical layer. The buffer is configured to set a phase adjustment for a latency setting between the first and second clock domains. The phase adjustment is based on whether a mismatch has occurred in data output by the buffer to the memory controller based on a comparison to the latency setting.

The invention discloses a communication method, a communication device, communication equipment and a computer readable storage medium, which are applied to the field of serial communication, and comprise the following steps of: adding a wakeup prefix sequence in front of a current data frame and adding a calibration pulse sequence behind the current data frame through a sending end to obtain a processed data frame; sending the processed data frame through an asynchronous communication line; when a low-power-consumption edge detection circuit of the receiving end identifies a wake-up prefix sequence on an asynchronous communication line, activating a main clock of the receiving end, and sampling effective data in a processed data frame corresponding to a current data frame based on an initial sampling point position or a sampling point position after last dynamic calibration; and when the sampling is completed, receiving and measuring the actual duration of the calibration pulse sequence through a receiving end, calculating clock skew according to the actual duration and the ideal duration, and adjusting the sampling point position of the next data frame based on the clock skew. According to the invention, the problems of asynchronous communication clocks and high power consumption are solved.

A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.

A phase interpolator includes a plurality of source-coupled transistor pairs and a plurality of current sources. The plurality of source-coupled transistor pairs may be configured to receive different phase shifted versions of an input signal. A differential output of each source-coupled transistor pair may be coupled to a differential output of the phase interpolator. Each current source in the plurality of current sources may be configured to supply a portion of a tail current to one or more source-coupled transistor pairs in the plurality of source-coupled transistor pairs at a level defined by a codeword. Step changes in amplitude of the tail current may occur in response to incremental changes in the codeword. The step changes in amplitude may vary with the amplitude of the tail current.

Some methods for triggering cameras in an autonomous vehicle (AV). The methods include receiving, by a programmable circuit, Generalized Precision Time Protocol (gPTP) information for synchronizing the programmable circuit with a gPTP Grand Master (GM); generating, by the programmable circuit, a pulse per second (PPS) signal having a peri-od of one second based on the gPTP time information; generating, by the programmable circuit, a synchronizing signal having a period less than the period of the PPS signal; generating, by the programmable circuit, a triggering signal based on the PPS signal, wherein a period of the triggering signal is the same as the period of the synchronizing signal; and sending, by the programmable circuit and to one or more cameras of an AV, the triggering signal for triggering the one or more cameras to capture one or more images. Systems and computer program products are also provided.

The invention provides a permanent magnet synchronous motor high-speed position acquisition system based on an FPGA and an SSI. The technical problem that the control requirement of a high-speed permanent magnet synchronous motor cannot be met is solved. Comprising a DSP which provides a reference clock, a control signal, an address bus and a data bus communicating with an FPGA through an XINTF interface; the FPGA is communicated with the DSP, forms a clock interface and a data interface which are communicated with the absolute value encoder, and provides a data transmission process between a system clock and the DSP and an acquisition and processing process of position data of the absolute value encoder; the differential signal transceiver forms a differential transmission channel between the FPGA and the absolute value encoder, outputs a system clock and receives a serial signal; and the absolute value encoder is used for collecting position information of the permanent magnet synchronous motor rotor and outputting a position signal through an SSI interface. And parallel processing of data acquisition and transmission based on clock synchronization is realized. And the control requirement of the high-speed permanent magnet synchronous motor is met.

The application discloses a kind of data transmission processing method and system of semiconductor production equipment, it is related to semiconductor data transmission technical field, including, establishing the alias mapping of accessory equipment and main equipment and setting mutual signal gate control rule, process stage window is mapped as network time slot generation time slot scheduling table, establishment release theme, complete timing synchronization, output synchronization ready identification;According to the set of tracing keys and the gap list, when serial number is continuous, seal the current process stage window tracing record and backfill token trigger next window scroll, when there is gap, call guide frame switching and execute gap retransmission in the time slot of next window, update time slot scheduling table, alias mapping table and corresponding release theme.The application forms the set of tracing keys and the gap list by comparing window serial number and reply handle, and when detecting gap, it is executed minimum back-off retransmission and dynamic time slot self-healing update, so that data transmission process has self-recovery characteristics.

The invention discloses a digital phased-array antenna synchronization method and device, particularly relates to the field of digital communication, and is used for solving the problem that framing boundaries and time identifier mapping of service data streams are difficult to stably align under the conditions of cache jitter and clock micro-drift. The sending end inserts a first synchronous anchor frame and a second synchronous anchor frame after the calibration synchronization is triggered, writes an alignment element identifier and a count value of a sending sampling counter, and registers a sending cache record table; a receiving end verifies the error detection code, pairs anchor frames according to a fixed anchor spacing rule, calculates an alignment offset and a forward inter-anchor stepping steady-state length, and generates an alignment proof message; checking the sending cache record table and the proof code, counting that the return proof reaches consistent continuity, indexing an offline training confidence matrix and outputting an alignment credibility level, and when conditions are met, updating framing boundary and time identifier mapping and sending a mapping effective message; and the receiving end starts the mapping version identifier, rechecks the stability of the alignment offset by means of the monitoring anchor frame, and sends a resynchronization request when the alignment offset fails.

This application discloses a communication method. The method includes: A first apparatus generates and sends a first optical signal, where the first optical signal is a signal obtained by combining a first clock signal with a downlink digital signal, and the first clock signal includes a first transmission delay; and a second clock signal is obtained by transmitting the first clock signal on a transmission link, a sum of a transmission delay of the transmission link and the first transmission delay is zero. A second apparatus performs time synchronization based on the second clock signal. In technical solutions of this application, digital-analog hybrid transmission and simultaneous transmission of the clock signal and the downlink digital signal may be completed through one transmission link, and an independent clock signal transmission link does not need to be established. In addition, after transmission of the first clock signal on the transmission link, the first transmission delay in the first clock signal may be canceled by the transmission delay of the transmission link, and the transmission delay of the transmission link does not need to be measured or calculated, thereby improving accuracy of time synchronization.

A clock determining method includes: when both a second network device and a first network device are synchronous with a reference clock, simulating, by using delay information between the second network device and the first network device and clock frequency information of the second network device, a second virtual clock synchronized with a first virtual clock, where the first virtual clock is used to simulate a clock of the first network device. A clock of the second network device can thus be simulated to perform a subsequent operation by using the simulated clock. For example, the simulated clock may be used to estimate precision time protocol (PTP) message synchronization performance of the second network device. Therefore, the PTP message synchronization performance of the second network device may be pre-determined before a global navigation satellite system (GNSS) fails, to guide network operation and maintenance activities.

Systems and methods for remote collaborative audio recording are disclosed. One aspect includes a studio computing system receiving a base track of a first audio recording. The studio computing system may transmit the base track over a computer network. A client computing system may receive the base track via the computer network, and record an audio track of a second audio recording. The audio track may be substantially time-synchronized with the base track. The client computing system may combine the audio track with the base track to generate a combined audio track, and transmit the combined audio track over the computer network. The studio computing system may receive the combined audio track via the computer network, and play the combined audio track without any network-induced time quantization error or time synchronization error between the base track and the audio track.

Technologies for periodic and synchronous phase error detection and compensation are described. An integrated circuit includes a clock source to generate a clock signal having a first frequency, and an analog-to-digital converter (ADC) to sample an incoming signal to obtain data samples using a sampling clock. The data samples include a periodic and synchronous phase error caused by the clock signal. The periodic and synchronous phase error has a harmonic of the first frequency. The integrated circuit also includes a signal processing circuit coupled to the ADC and the clock source. The signal processing circuit includes a harmonic phase correction block to detect and compensate for the periodic and synchronous phase error in the data samples to obtain corrected data samples.

A translation device includes a first input / output circuit configured to transmit and receive a first signal having a first signal speed modulated based on a non-return to zero (NRZ) method through a plurality of first pins; a second input / output circuit configured to transmit and receive a second signal having a second signal speed modulated based on a pulse amplitude modulation-3 (PAM-3) method through a plurality of second pins; and a translation circuit configured to translate the first signal to the second signal, or translate the second signal to the first signal, wherein the second signal speed is equal to or greater than the first signal speed.

A media access control (MAC) processor of a network device receives a timing packet to be transmitted by the network device. The MAC processor generates one or more indicators to be used by a PHY device of the network device for embedding timing information into the timing packet. The one or more indicators include at least an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded, an indicator of a location of a field in the timing packet at which the timing information is to be embedded, and an indicator of whether timing information in the timing packet needs to be updated. The MAC processor transfers the timing packet and the one or more indicators to the PHY device for further processing of the timing packet and subsequent transmission of the timing packet from the network device.

The present disclosure relates to a method for radio communication of a plurality of utility meters (5) being installed at distributed installation locations with a data receiver (11), wherein the method comprises: - receiving, at the data receiver (11), data (313) from any of the utility meters (5), wherein the data (313) is modulated on a received signal (301), wherein the received signal (301) has a time-varying phase offset; and - compensating (309) for the time-varying phase offset of the received signal (301) by using decision-directed phase tracking; characterised in that the method further comprises: - coherently demodulating (311) the compensated received signal (309) to extract the data (313); - modulating (315) the extracted data (313) to reconstruct a replica (317) of the received signal (301); - estimating (325) a phase offset prediction error (329) based on a comparison between the compensated received signal (309) and the replica (317) of the received signal (301); - estimating (327) a phase offset prediction error covariance (331) based on how much the amplitude of the compensated received signal (309) diverges from an amplitude reference value and / or the phase offset prediction error (329) diverges from an error reference value; - providing a Kalman filter (307) with both the estimated phase offset prediction error (329) and the estimated phase offset prediction error covariance (331) as inputs for the Kalman filter (307); and using an output (333) of the Kalman filter as a prediction of the time-varying phase offset in a feedback loop to compensate (309) for the time-varying phase offset of the received signal (301) before the compensated received signal (309) is coherently demodulated (311) to extract the data (313).

A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

The application provides a clock recovery method, device and system. The method can be applied to an optical transport network. The method comprises the following steps: receiving a first optical transport network (OTN) frame data stream, obtaining a service layer clock and phase difference information carried by a second OTN frame from the first OTN frame data stream, and then adjusting a reference clock of the second OTN frame according to the service layer clock and the phase difference information, wherein the reference clock of the second OTN frame is used for recovering a clock of the second OTN frame. The clock recovery method provided by the application can improve the accuracy of clock recovery of the OTN frame, thereby achieving the purpose of improving system performance.

Some methods for triggering a camera in an autonomous vehicle (AV). These methods include receiving, with a programmable circuit, universal precision time protocol (gPTP) information, the gPTP information for synchronizing the programmable circuit with a gPTP master clock (GM); generating, with a programmable circuit, a pulse per second (PPS) signal having a period of one second based on the gPTP time information; generating, using a programmable circuit, a synchronization signal having a period smaller than that of the PPS signal; generating, using a programmable circuit, a trigger signal based on the PPS signal, in which the cycle of the trigger signal is the same as the cycle of the synchronization signal; and transmitting, with the programmable circuit, a trigger signal to one or more cameras of the AV for triggering the one or more cameras to capture the one or more images. A system and a computer program product are also provided.

Methods, systems, and apparatus, for enhanced clock frequency control. In some implementations, a clock system tracks time using a clock signal having a clock frequency. An interface receives a time reference from a reference clock, and a feedback loop synchronizes the clock system with the reference clock. The feedback loop includes a feedback loop controller configured to determine a clock frequency adjustment for the clock system based on an offset between the time reference and a time indicated by the clock system. The feedback loop also includes a smoothing filter configured to alter the clock frequency adjustment determined using the feedback loop controller. The feedback loop updates the clock frequency of the clock system based on the altered clock frequency adjustment.

A correction device included in a communication system is configured to determine whether a communication parameter, which is set in a transmission setting for transmitting a frame in at least one target device, needs to be corrected based on time information included in a frame. The correction device is configured to adjust the communication parameter to suppress a deterioration in a communication quality in response to determining that the communication parameter needs to be corrected. Then, the correction devices is configured to notify the at least one target device of a new communication parameter that has been adjusted.