169results about "Synchronisation error correction" patented technology

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

A clock circuit, a receiver, and a passive optical communication network system are disclosed. The clock circuit is applied to a receiver in a passive optical communication network and is configured to adjust the clock frequency of an output clock signal based on a transmission protocol, the clock circuit comprises at least one clock path and a frequency divider, and the at least one clock path comprises a first clock path; wherein the first clock path receives a reference clock signal from the first phase-locked loop circuit and a control signal from the clock data recovery circuit, and interpolates a conversion signal of the reference clock signal by using the reference clock signal so as to output a multi-phase clock signal; and the frequency divider receives the multi-phase clock signal and performs frequency division on the multi-phase clock signal based on a preset frequency division value, and the preset frequency division value is determined based on a transmission protocol. The clock circuit can be compatible with fast clock switching schemes of data rates of different PON protocols, so that the adaptability and the locking performance of a receiver in a burst mode are improved.

A first device includes a transceiver to communicate with a second device over an interposer, the interposer comprising a plurality of conductive traces between the first device and the second device. The first device also includes control logic, coupled to the transceiver associated with the first device, configured to send first data to the second device over a conductive trace of the plurality of conductive traces, simultaneously receive second data from the second device over the conductive trace, and extract the second data from a combined signal comprising the first data and the second data.

The vehicle control system includes an abnormality diagnosis unit for determining whether a synchronization abnormality between a master ECU and a slave ECU has occurred. The abnormality diagnosis unit transmits and receives a signal between the master ECU and the slave ECU and acquires time information. The slave ECU calculates a delay time of transmission based on the acquired time information. Then, the abnormality diagnosis unit first determines whether or not there is a periodic shift. When determining that there is no periodic deviation, the abnormality diagnosis unit determines whether or not there is an offset deviation based on the difference obtained by subtracting the delay time from the second time and the first time. The abnormality diagnosis unit determines that a synchronization abnormality has occurred when it is determined that there is a periodic deviation or when it is determined that there is the offset deviation.

The invention relates to the technical field of low-orbit satellite communication, and discloses a multi-channel simultaneous calibration method, system and device based on FDM (frequency division multiplexing) and a medium, which realize high-precision synchronous estimation and compensation of multi-channel amplitude, phase and delay parameters through a frequency division multiplexing and parallel processing mechanism based on FDM. The problem of channel inconsistency in coaxial cable FDM transmission is effectively solved, the calibration efficiency and the system transmission performance are remarkably improved on the premise that the high precision that the amplitude error is not larger than 0.2 dB, the phase error is not larger than 2 degrees and the delay error is lower than 0.01 sampling point is ensured, meanwhile, the calculation complexity and the sequence overhead are reduced, and the system performance is improved. The method is suitable for calibration requirements of high-frequency-width multi-channel systems such as a large phased array of a low-orbit satellite and the like.

The present disclosure provides techniques for measuring and compensating for clock drift errors in time-aware networks and time-sensitive applications, where a time-aware system (TAS) measures clock drift, and compensates for the measured clock drift, and makes predictions of future clock drift values based on history and other physical measurements. Existing messages used for measuring link delay and / or used for time synchronization can be used for frequency measurement (and thus clock drift measurement), and this measured drift can be applied as a correction factor whenever synchronization is determined and / or used. The predicted clock drift rate can be based on various probability distributions including linear, Kalman filters, and / or others. Other embodiments may be described and / or claimed.

The invention relates to the technical field of signal processing, and discloses a time slot control method and system for an inter-satellite link time division communication system, and the method comprises the steps: carrying out the clock domain crossing synchronization and jitter elimination processing of a pulse per second signal inputted externally, and detecting the validity of the processed pulse per second signal; extracting a time error between a local clock and an external clock based on the second pulse signal after validity detection; performing continuous health detection on the time error to generate a health state indication; performing second-order filtering processing on error information by referring to the health state indication and the time error, taking a processing result as an adjustment amount of a frequency control word of an NCO counter, and driving the NCO counter to generate a time reference; and detecting whether an external pulse per second signal is subjected to slip adjustment or not, and distributing a time slot control signal by using the time reference. Accurate distribution of time information is achieved, misreading of externally input time information is avoided, and the adaptive capacity of the system under different working conditions is improved.

To provide a system for surely authenticating a message, a vehicle and a method.SOLUTION: A system is provided with an authentication part for authenticating a message at least including control data transmitted and received between a plurality of on-vehicle devices and a first counter that is counted each time a power source is turned on by using at least the control data and the first counter in the case of authenticating the message including the control data exchanged between the plurality of on-vehicle devices. The authentication part authenticates a message including a second counter to be incremented over time without including the first counter transmitted and received between the on-vehicle devices, without using the second counter instead of the first counter in the case of confirming whether synchronization is performed between the plurality of on-vehicle devices.SELECTED DRAWING: Figure 3

The application discloses a kind of radio frequency synchronous signal circuit and synchronization method, belong to wireless communication technical field, solve the problem that existing device with full integration self-calibration function is difficult to meet miniaturization, low cost and wide frequency range synchronization demand;It includes radio frequency synchronous signal source, radio frequency synchronous signal source includes the phase detection circuit, FPGA circuit, DAC circuit, radio frequency circuit and output port connected in turn;The input end of phase detection circuit is respectively connected with two symmetrically arranged first frequency divider circuit and second frequency divider circuit in parallel.The full integration circuit of radio frequency synchronous signal source and automatic synchronization method are used in the application, miniaturization, low cost, wide frequency range and high-precision synchronization are realized, the port-to-port synchronization output of multi-channel radio frequency signal is realized, and the dependence on external equipment is eliminated and cable phase offset is compensated.

A method of reducing bit error rate in a PAM4 clock data recovery circuit is described. The method includes determining a first target value of a slicing level, sweeping down from an upper voltage threshold to determine a first reference voltage value, and detecting a first filtered analog output associated with the first reference voltage value. The method also includes sweeping up from a lower voltage threshold to determine a second reference voltage value and detecting a second filtered analog output associated with the second reference voltage value. The first reference voltage value and the second reference voltage value are averaged to determine a calculated threshold value.

Embodiments of this application provide an information transmission method, a communications device and system, and a computer-readable storage medium, and are applicable to information exchange inside an intelligent vehicle in the field of autonomous driving. In the embodiments of this application, a full counter value maintained by each ECU device includes a global counter value and a local counter value. The global counter value keeps globally synchronized in an entire CAN network, and the local counter value is obtained by each device performing counting by using a local counter. In this way, when a second device sends a CAN message, the CAN message carries a second counter value. When receiving the CAN message, the first device may determine whether a locally maintained first counter value matches the second counter value. If the locally maintained first counter value does not match the second counter value, the CAN message may be verified by using the second counter value and the global counter value. In this way, the technical solutions provided in the embodiments of this application can improve security and stability of an in-vehicle network of the intelligent vehicle.

A light communication system, receiver, and method for synchronizing a receiver with a transmitter so as to decode a data input stream transmitted by the transmitter and received at the receiver. The method includes: receiving a data input stream at a receiver, the data input stream having a first data rate that is set based on a transmitter clock rate; generating a wave; obtaining a phase error between the data input stream and the generated wave; determining a synchronized clock rate by using the phase error to adjust the frequency of the generated wave so as to match the frequency of the generated wave to the transmitter clock rate of the data input stream; and using the synchronized clock rate to decode the data input stream so as to obtain data encoded in the data input stream.

The invention discloses a multi-path frequency-adjustable signal generation system based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of signal generation. The system comprises an adjustable frequency signal generation module, an FPGA register read-write control module, an SPI communication module and a top layer module. The top layer module adopts a generate block statement to realize batch instantiation of a multi-path signal output module, a positioning register mechanism is introduced, and a group of register resources are used for controlling a multi-path output channel, so that the problem of register resource waste caused by repeated instantiation of the module in the traditional design is effectively solved. According to the system, remote configuration of an FPGA internal register by a CPU is achieved through an SPI communication interface, and the frequency-adjustable signal generation module supports independent adjustment of parameters such as frequency, high pulse width and low pulse width. And when the positioning register is matched with a specific output channel and the data updating flag bit is valid, the system accurately sends the characteristic parameters to the corresponding channel, so that the accuracy of each path of signal parameters is ensured. According to the method, the code redundancy and the development time are remarkably reduced, and the system maintainability is improved.

An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

A media access control (MAC) processor of a network device receives a timing packet to be transmitted by the network device. The MAC processor generates one or more indicators to be used by a physical layer (PHY) device of the network device to embed timing information in the timing packet. The one or more indicators include at least an indicator indicating that the timing packet is a type of packet in which the timing information is to be embedded, an indicator of the location of a field in the timing packet in which the timing information is to be embedded, and an indicator of whether the timing information in the timing packet is to be updated. The MAC processor transmits the timing packet and the one or more indicators to the PHY device for further processing of the timing packet and subsequent transmission of the timing packet from the network device.

A device may apply a first signal to a device, the first signal comprising a long training field (LTF) and one or more data packets, the one or more data packets comprising one or more pilot tones. A device may demodulate the first signal. A device may compare power in the LTF to power of the one or more pilot tones. A device may determine gain vs. time based at least in part on comparing the power in the LTF to the power of the one or more pilot tones. A device may apply one or more corrections to the device based at least in part on the determined gain vs. time.

Disclosed is a method comprising obtaining a plurality of previous clock skews, a reported temperature and a reported time, based on the plurality of previous clock skews, the reported temperature and the reported time, obtaining a prediction of the current clock skew, determining a current clock offset based on the predicted current clock skew, determining a clock adjustment based on the current clock offset and the reported time, and determining a corrected time based on the clock adjustment.

A loop filter, and a timing recovery method and apparatus are provided. The loop filter includes: N input terminals configured to receive N first signals; where N is any integer greater than or equal to 2; a source filter, including: an integral signal terminal and an addition terminal; a first gain processing module configured to perform first gain processing on the N first signals to obtain a second signal, and output the second signal to the addition terminal; a second gain processing module configured to perform second gain processing on the N first signals to obtain a third signal, and output the third signal to the integral signal terminal; and a source filter configured to integrate the third signal received by the integral signal terminal to obtain a fourth signal, and obtain a fifth signal according to the fourth signal and the second signal received by the addition terminal.

In order to maintain synchronization of wireless communication, a remote wireless device (20) is provided with: a communication unit (120) whereby a synchronization maintenance signal (SM) transmitted from a base wireless device (10) in a transmission cycle (Tt) which is a plurality of times the length of a predetermined cycle (Tu) is received in a reception cycle (Tr) which is a predetermined number (N) of times the length of the transmission cycle (Tt); and a synchronization unit (122) that maintains the synchronization. The predetermined number is an integer of 1 or more. The reception cycle is the sum of a first period (T1) in which the communication unit receives the synchronization maintenance signal and a second period (T2) in which the communication unit does not receive the synchronization maintenance signal. The first period is a period including one or more of the predetermined cycles included in the reception cycle.

The signal conditioning circuitry (400) includes logic circuitry (402), a low pass filter (404), and comparator circuitry (406). The logic circuitry (402) is configured to compare a data unit from a sequence of data units with a previous data unit and provide a logic output signal. The low pass filter (404) is coupled to the logic circuitry (402), and the low pass filter (404) is configured to provide a data transition density measure of the sequence of data units based on the logic output signal. The comparator circuitry (406) is coupled to the low pass filter (404), and the comparator circuitry (406) is configured to compare the data transition density measure to a threshold value and, based on the comparison to the threshold value, indicate a disruptive pattern in the sequence of data units.

A multi-channel synchronous acquisition and transmission system based on the JESD204B protocol includes a multi-channel AD synchronous acquisition module, a signal source module, a power module and an upper computer module, wherein the signal source module sends a reference clock and multiple analog signals to the multi-channel AD synchronous acquisition module; the multi-channel AD synchronous acquisition module includes an FPGA, a multi-channel ADC, an independent clock source and multiple devices; the independent clock source receives the reference clock and transmits a sysref signal; a time window is configured in the multi-channel ADC; the FPGA generates a sync signal and synthesizes an LMFC, and an edge of the sysref signal is taken as an edge of the LMFC; in the multi-channel ADC, a corresponding ILAS is set for each digital signal; and the FPGA receives all the ILASs and digital signals, and multiple digital signals are processed synchronously.

The present invention is directed to electrical circuits. In an embodiment, the present invention provides a clock compensation device configured to correct timing discrepancies in differential clock signals. The circuit comprises positive and negative lines with multiple inverters, including crossover inverters that generate correction signals to maintain synchronization between the clock signals. There are other embodiments as well.

Synchronizing time-of-day (TOD) between TOD components includes issuing an order for a plurality of TOD components, each including a local time, an offset, and an effective time as a sum of the local time and the offset. The effective time of a reference TOD component is the reference time to which target TOD component(s) are to be synchronized. The order directs each of the plurality of TOD components to synchronously, at a point in time, snapshot its local time. This provides a snapshot of the effective time of the reference TOD component, and thus the reference time. The synchronizing synchronizes each target TOD component to the reference time by setting the respective offset as a difference between the target TOD component's snapshot local time and the snapshot of the reference time. Based on the synchronizing, the effective times of the plurality of TOD components match and are the reference time.

Embodiments of the present application relate to a method for synchronizing audio data and a data sending end, the method comprising: obtaining first time information of a first sending end and second time information of a second sending end; determining, by using a preset synchronization algorithm, a next sampling time of the first sending end based on the first time information and a sampling period, and determining a next sampling time of the second sending end based on the second time information and the sampling period; controlling the first sending end to collect audio data at the next sampling time of the first sending end, and controlling the second sending end to collect audio data at the next sampling time of the second sending end. Thus, the next sampling times of the first sending end and the second sending end are synchronized by using the preset synchronization algorithm, and then the first sending end and the second sending end are controlled to collect audio data at the synchronized sampling times, so that the synchronization of the sending end in collecting audio data can be improved.

The invention provides a multi-channel data alignment method and device based on a virtual pointer, and the method comprises the steps: transmitting target data of a plurality of data channels to a plurality of alignment mark detection modules, and enabling the alignment mark detection modules to detect alignment marks in the target data of one data channel; the alignment mark detection module outputs data to a data storage matrix, the data storage matrix comprises a plurality of storage units, and target row addresses and target column addresses of the alignment marks of the corresponding data channels in the corresponding storage units are recorded; and the data read enabling generation module reads and enables the plurality of storage units, and the routing cross matrix module starts to read data from the target row address and the target column address of the alignment mark of the corresponding data channel and outputs the data. The invention further provides a device for implementing the method. According to the invention, alignment of multi-channel data can be realized through a simple structure.

A receiver circuit includes an equalizer configured to generate an equalized signal by equalizing an input data signal transmitted through a communication channel based on an equalization coefficient, a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalized signal, generate a data sample signal including a plurality of data bits by sampling the equalized signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalized signal in synchronization with the edge clock signal, and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.

Methods, systems, and apparatus, for enhanced clock frequency control. In some implementations, a clock system tracks time using a clock signal having a clock frequency. An interface receives a time reference from a reference clock, and a feedback loop synchronizes the clock system with the reference clock. The feedback loop includes a feedback loop controller configured to determine a clock frequency adjustment for the clock system based on an offset between the time reference and a time indicated by the clock system. The feedback loop also includes a smoothing filter configured to alter the clock frequency adjustment determined using the feedback loop controller. The feedback loop updates the clock frequency of the clock system based on the altered clock frequency adjustment.

The application discloses a time synchronization system and method of a handheld multi-sensor fusion scanning platform, and the system comprises an upper computer and a microcontroller configured as a main clock source of the system; the microcontroller is used for generating at least a message synchronization control pulse signal, a hardware trigger pulse signal and a serial time message defining a main time system; the upper computer comprises a time synchronization device running a raw data receiving module, a time stamp synchronization calibration module and a data storage and visualization module, different time synchronization strategies are adopted for different sensors, including external direct time service, time system offset calibration and trigger acquisition and low-delay near-neighbor matching strategy. The application uses a microcontroller as a synchronization core, and realizes a hardware time synchronization precision of sub-millisecond level without any expensive external synchronization equipment; the time synchronization system and method have high flexibility and robustness, and can guarantee efficient and low-delay data processing.

A method for data transmission includes dividing first data into data packets, selecting transition acceleration data among transition acceleration data preliminary packets, generating transition guarantee data packets by performing an operation on a data packet group including predetermined data packets among the data packets and the transition acceleration data, and transmitting the transition acceleration data and the transition guarantee data packets. In the selecting the transition acceleration data among the transition acceleration data preliminary packets, the transition acceleration data different from previous transition acceleration data immediately preceding the transition acceleration data in the transition acceleration data preliminary packets is selected.

[0009] Embodiments of the present application provide a communication method, a communication device, and a communication system. The communication method applied to a first device includes the steps of: transmitting a first signal to a second device, where the transmitted first signal has a first phase; and receiving a second signal from the second device, where the second signal and the first signal are two signals whose transmission directions are opposite to each other on a first transmission path, and the received second signal has a second phase, and the first and second phases are used to adjust a data signal on the first transmission path. Based on this technical solution, the phase difference between the first and second phases indicates the effect of two bidirectional transmissions on the phase of the first transmission path, and the first and second phases can be used to adjust the data signal to improve the reliability of data signal transmission on the first transmission path.