405results about "Synchronisation error correction" patented technology

The invention provides a clock error compensation method and an orthogonal frequency division multiplexing system using the clock error compensation method, and the compensation method comprises the steps: determining a second synchronous pilot symbol at a corresponding position in a received signal through a first synchronous pilot symbol of an orthogonal frequency division multiplexing symbol selected according to a system pilot signal; the method comprises the following steps: receiving a received signal, further determining a first synchronous pilot signal and a second synchronous pilot signal, after synchronizing the first synchronous pilot signal and the second synchronous pilot signal, determining the position of each orthogonal frequency division multiplexing symbol in the received signal relative to the second synchronous pilot symbol, and demodulating the received signal based on the position. According to the method, the phase deviation value of each orthogonal frequency division multiplexing symbol in the received signal relative to the second synchronous pilot symbol in the frequency domain is determined, and finally, frequency domain phase compensation is performed on each orthogonal frequency division multiplexing symbol in the received signal according to the calculated phase deviation value, so that clock error compensation of the received signal is realized, and the precision of phase compensation is improved.

The invention relates to a non-signaling test-based frequency offset calibration method, system and device and a medium, and the method comprises the steps: carrying out the parallel non-signaling frequency offset test of a plurality of target chips, collecting the output waveforms of the target chips, and determining the frequency offset values of the target chips according to the output waveforms; performing deviation analysis on the frequency deviation value, and calculating a corresponding frequency deviation calibration value based on the frequency deviation value and a preset frequency calibration coefficient under the condition that the frequency deviation value reaches a preset frequency limit range; writing the frequency offset calibration value into a corresponding target chip, and performing parallel frequency offset calibration; and carrying out calibration degree verification on the target chip after frequency offset calibration so as to confirm whether the frequency offset value of the target chip accords with a preset standard frequency. The method and the device have the effect of improving the frequency offset calibration efficiency of the chip.

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

Systems and methods for regaining phase synchronization between a CMTS core and an RPD, where the phase synchronization is regained over repeated temporal periods preferably divided between a first interval having a frequency adjustment of a first magnitude and a second interval having a frequency adjustment of a second magnitude.

A technique uses linear prediction to determine the location of spurious content in a digital phase-locked loop and suppresses the spurious content from propagating to the clock output. In at least one embodiment, the technique implements an iterative (e.g., recursive) computation.

The invention discloses a distributed phased array system and electronic equipment, and relates to the technical field of signal processing. Active transmit-receive units which are in one-to-one connection with the antenna units; a frequency source connected with each active transmit-receive unit and used for controlling frequency conversion synchronization in each active transmit-receive unit and performing synchronous calibration on a clock of each active transmit-receive unit; and the signal processing unit is connected with each active transceiving unit and is used for synchronizing the signal processing of each active transceiving unit based on the synchronously calibrated clock. By ensuring frequency conversion synchronization, clock synchronization and signal processing synchronization among the active transceiving units, the synchronism of transmission signals in the active transceiving units can be ensured, namely, the synchronism of multi-path signal input and output can be improved, and the synchronization performance among multi-path signal transceiving channels is improved.

Fast sampling phase and frequency acquisition suitable for incorporation into various high bandwidth receivers and receiving methods. One illustrative integrated circuit receiver or “deserializer” design has: a clock circuit that provides a sample clock; an analog to digital converter that samples a receive signal in accordance with the sample clock to provide receive signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock; and a feedback circuit to minimize timing error of the sample clock after the initial frequency offset and initial phase offset have been corrected.

The present disclosure discloses a two-point sampling optimized method and system for sinusoidal excitation-based frequency response measurement. A plurality of points are sampled at equal intervals within the starting frequency and ending frequency range as initial information, the interpolation error of each sub-frequency band is estimated according to existing sampling information, the sub-frequency band with the largest interpolation error is selected, two new sampling points are added within the sub-frequency band, and the above steps are repeated until the quantity of sampling points reaches the total quantity set by a user; and the user is asked whether new sampling points need to be added, if so, after the user specifies a new quantity of sampling points, the interpolation error of each sub-frequency band is estimated again and sampling continues, otherwise, the sampling ends. The present improves the practicality of a sinusoidal excitation-based frequency response measurement method.

The embodiment of the invention relates to the technical field of clock synchronization, and discloses a clock synchronization method and system, electronic equipment and a storage medium. The clock synchronization method comprises the steps that clock frequencies of a master chip and a slave chip are synchronized, and the master chip and the slave chip interact through an inter-chip communication channel; determining a clock calibration value, wherein the clock calibration value is used for representing a clock difference between the master chip and the slave chip; and according to the clock calibration value, carrying out clock calibration so as to synchronize the clocks of the master chip and the slave chip. The synchronization precision of the master chip and the slave chip is improved at least while additional interfaces are not introduced to the master chip and the slave chip.

A communication apparatus is provided that: adds data, obtained by sampling a repetitively arrived packet by a clock with a frequency that is N1-times a communication speed, to an addition result of previously arrived packets every time the packet arrives; holds a processing result of a first digital filter that processes the addition result in synchronization with a sampling clock; reproduces a clock waveform contained in bit data from a result of processing by a second digital filter, the second digital filter process, in synchronization with the sampling clock, an addition result obtained by adding data, which is obtained by sampling each bit constituting the arrived packet by the clock with a frequency that is N1-times a communication speed, to an addition result of previously arrived packet every time a next bit arrives; and reproduces a sampling clock synchronized with the arrived packet from the reproduced clock waveform.

The invention discloses a cable sensor network time service compensation method, device and equipment and a medium, and belongs to the technical field of network time service, and the method comprises the following steps: collecting process historical data of a cable network actual error compensation system, and taking error data of a satellite second clock and a crystal oscillator second clock as an initial sample; aggregating the initial samples to obtain aggregated samples under each step size scale; constructing an error feature vector containing an aggregation sample of the current scale and an accumulated error of the current time point information; performing modeling on the error feature vectors by using a Gaussian-like process regression model to obtain a Gaussian-like process regression model of each step size scale; error estimation values of all step size scales are generated in sequence, and a time service error estimation value of the current moment is obtained by combining the difference error estimation values of the lowest step size scale and the highest step size scale; and compensating the accumulated error of the crystal oscillator clock based on the time service error estimation value at the current moment. According to the invention, the synchronization precision and practicability are improved.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

Fast sampling phase and frequency acquisition suitable for incorporation into various high bandwidth receivers and receiving methods. One illustrative integrated circuit receiver or “deserializer” design has: a clock circuit that provides a sample clock; an analog to digital converter that samples a receive signal in accordance with the sample clock to provide receive signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock; and a feedback circuit to minimize timing error of the sample clock after the initial frequency offset and initial phase offset have been corrected.

A clock circuit, a receiver, and a passive optical communication network system are disclosed. The clock circuit is applied to a receiver in a passive optical communication network and is configured to adjust the clock frequency of an output clock signal based on a transmission protocol, the clock circuit comprises at least one clock path and a frequency divider, and the at least one clock path comprises a first clock path; wherein the first clock path receives a reference clock signal from the first phase-locked loop circuit and a control signal from the clock data recovery circuit, and interpolates a conversion signal of the reference clock signal by using the reference clock signal so as to output a multi-phase clock signal; and the frequency divider receives the multi-phase clock signal and performs frequency division on the multi-phase clock signal based on a preset frequency division value, and the preset frequency division value is determined based on a transmission protocol. The clock circuit can be compatible with fast clock switching schemes of data rates of different PON protocols, so that the adaptability and the locking performance of a receiver in a burst mode are improved.

The present application relates to a frequency adjustment method, device, Bluetooth headset, storage medium and program product. The method comprises: receiving a signaling packet periodically sent by a master ear, obtaining the corresponding Bluetooth clock of a slave ear according to the target sample point identifier in the signaling packet; subtracting the Bluetooth clock of the master ear from the Bluetooth clock of the slave ear to obtain a first phase difference; determining the first phase difference between the Bluetooth clock of the slave ear and the Bluetooth clock of the master ear; if the first phase difference satisfies the phase compensation condition, performing a fast phase compensation process on the clock frequency of the slave ear according to the first phase difference; after adjusting the clock frequency of the slave ear, determining the second phase difference between the Bluetooth clock of the slave ear and the Bluetooth clock of the master ear again; and adjusting the clock frequency of the slave ear again according to the first phase difference and the second phase difference. The use of this method can achieve precise synchronization of playback between the two ears in a Bluetooth headset.

The present disclosure relates to the field of memory technologies and provides a data sampling circuit, comprising a first sampling module configured to respond to a signal from the data signal terminal and a signal from the reference signal terminal and to act on the first node and the second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on the third node and the fourth node; a latch module configured to input a high level to the first output terminal and input a low level to the second output terminal, or to input the low-level signal to the first output terminal and input the high-level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and an offset compensation module connected in parallel to the second sampling module and configured to compensate an offset voltage of the second sampling module. In this data sampling circuit, the second sampling module is additionally provided, and the offset compensation module is connected in parallel to the second sampling module, such that kickback noise is reduced.

A clock synchronization method is disclosed. The method comprises receiving master timing synchronization data from a master clock device, wherein the master timing synchronization data is based at least in part on quantum data obtained from a first quantum device of the master clock device. The method comprises determining local timing synchronization data that is based at least in part on local quantum data obtained from a second local quantum device, wherein the second local quantum device is entangled with the first quantum device such that the local quantum data and the quantum data obtained from the first quantum device are identical at a same time. The method comprises using the determined local timing synchronization data and the received master timing synchronization data to determine a timing correction factor. The method comprises correcting a local system time using the timing correction factor.

A method for detecting asymmetric path delay changes in a synchronisation network comprises: monitoring a first path delay and a second path delay over a first sample period and a second sample period, wherein the first path delay is a reported time taken for a first packet transmitted by a first node of the network to be received by a second node of the network, and the second path delay is a time taken for a second packet transmitted by the second node of the network to be received by the first node of the network; determining that a change in one or both of the first and second path delays between the first sample period and the second sample period exceeds a first threshold; and determining whether the change in one or both of the first and second path delays is an asymmetric path delay change.

An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

The invention discloses a frame synchronization method and device based on soft information filtering and dephasing ambiguity. Frame synchronization is performed by using demodulated soft information, and new strategies such as soft information filtering, phase ambiguity resolution, Doppler frequency estimation and compensation, dynamic frame header adjustment, multi-frame joint detection and adaptive judgment threshold are combined, so that the accuracy and robustness of frame synchronization are remarkably improved; the method is suitable for processing the frame synchronization problem of a long frame header in a low signal-to-noise ratio environment, and effectively solves the problem of phase ambiguity under the condition that the Doppler frequency change rate is large.

A first device includes a transceiver to communicate with a second device over an interposer, the interposer comprising a plurality of conductive traces between the first device and the second device. The first device also includes control logic, coupled to the transceiver associated with the first device, configured to send first data to the second device over a conductive trace of the plurality of conductive traces, simultaneously receive second data from the second device over the conductive trace, and extract the second data from a combined signal comprising the first data and the second data.

The vehicle control system includes an abnormality diagnosis unit for determining whether a synchronization abnormality between a master ECU and a slave ECU has occurred. The abnormality diagnosis unit transmits and receives a signal between the master ECU and the slave ECU and acquires time information. The slave ECU calculates a delay time of transmission based on the acquired time information. Then, the abnormality diagnosis unit first determines whether or not there is a periodic shift. When determining that there is no periodic deviation, the abnormality diagnosis unit determines whether or not there is an offset deviation based on the difference obtained by subtracting the delay time from the second time and the first time. The abnormality diagnosis unit determines that a synchronization abnormality has occurred when it is determined that there is a periodic deviation or when it is determined that there is the offset deviation.

The invention relates to the technical field of low-orbit satellite communication, and discloses a multi-channel simultaneous calibration method, system and device based on FDM (frequency division multiplexing) and a medium, which realize high-precision synchronous estimation and compensation of multi-channel amplitude, phase and delay parameters through a frequency division multiplexing and parallel processing mechanism based on FDM. The problem of channel inconsistency in coaxial cable FDM transmission is effectively solved, the calibration efficiency and the system transmission performance are remarkably improved on the premise that the high precision that the amplitude error is not larger than 0.2 dB, the phase error is not larger than 2 degrees and the delay error is lower than 0.01 sampling point is ensured, meanwhile, the calculation complexity and the sequence overhead are reduced, and the system performance is improved. The method is suitable for calibration requirements of high-frequency-width multi-channel systems such as a large phased array of a low-orbit satellite and the like.

The embodiments of the present application relate to the technical field of clock synchronization. Disclosed are a clock synchronization method and system, and an electronic device and a storage medium. The clock synchronization method comprises: synchronizing a clock frequency of a master chip with that of a slave chip, wherein the master chip interacts with the slave chip by means of an inter-chip communication channel; determining a clock calibration value, wherein the clock calibration value is used for representing a clock difference between the master chip and the slave chip; and performing clock calibration on the basis of the clock calibration value, so as to synchronize a clock of the master chip with that of the slave chip. Therefore, an improvement in the synchronization precision of a master chip and slave chip is at least facilitated while no additional interface is introduced onto the master chip and the slave chip.

The invention provides a distributed SAR time-frequency synchronization method and device. The method comprises the following steps: determining a local pseudo range of a satellite in a distributed SAR system relative to a Beidou satellite navigation system; and adjusting a reference frequency source signal corresponding to a satellite in the distributed SAR system based on a Beidou satellite navigation system to obtain a reference frequency source signal. And the first satellite opens the inter-satellite link according to the reference frequency source signal corresponding to the first satellite. And sending a first local pseudo range corresponding to the first satellite to a second satellite in the distributed SAR system based on the inter-satellite link. A clock difference of the second satellite relative to the first satellite is determined based on the second local pseudorange and the first local pseudorange. And adjusting the frequency of a voltage-controlled constant-temperature crystal oscillator of the second satellite based on the clock difference. According to the method provided by the invention, time-frequency synchronization between satellites can be realized simply and efficiently at low cost.

The embodiment of the invention discloses a data synchronization method, device and system. In a scene of synchronizing data streams of a physical layer, the synchronization process of the data streams can be timed. Furthermore, whether the data stream with the time length meeting the timeout condition exists in the synchronization process is judged, which is equivalent to whether the situation that the synchronization time is too long exists. If the condition that the synchronization time is too long exists, it is indicated that a system fault or link deterioration may occur, then corresponding timeout processing, such as error reporting and system resetting, needs to be carried out, so that the system fault or link deterioration can be dealt with in time, and the data transmission efficiency is optimized.

Systems and methods are provided for synchronizing a lower-power idle state. The systems and methods perform operations comprising: initializing, by a master physical layer (PHY) controller, a connection over a network with a slave PHY controller; during initialization, synchronizing a low power idle (LPI) timer of the master PHY controller with a LPI timer of the slave PHY controller; establishing an offset between the LPI timer of the master PHY controller and the LPI timer of the slave PHY controller; and after synchronizing the timer of the master PHY controller with the LPI timer of the slave PHY controller, establishing a link between the master PHY controller and the slave PHY controller to enable the master PHY controller and the slave PHY controller to exchange data.

The invention discloses a broadband signal receiving and preprocessing assembly and method, and belongs to the field of communication. The broadband signal receiving and preprocessing assembly comprises a programmable logic device, an analog-to-digital converter, a clock distribution chip and a photoelectric conversion module; the analog-to-digital converter receives an input broadband radio frequency signal or a linear frequency modulation signal for correction, and outputs sampling data after analog-to-digital conversion; the programmable logic device receives an external control signal and sampling data input by the analog-to-digital converter, preprocesses the sampling data according to the control signal, and outputs the preprocessed sampling data of the broadband radio frequency signal to the photoelectric conversion module; the photoelectric conversion module receives the electric signal which is output by the programmable logic device and contains the preprocessing data, and outputs an optical signal after photoelectric conversion; and the clock distribution chip receives an external synchronizing signal and a clock signal, and outputs a clock synchronizing signal required by the programmable logic device and the analog-to-digital converter to work. According to the invention, large instantaneous bandwidth processing can be realized, adaptive amplitude-phase correction is realized, and amplitude-phase correction precision and efficiency are improved.

The present disclosure provides techniques for measuring and compensating for clock drift errors in time-aware networks and time-sensitive applications, where a time-aware system (TAS) measures clock drift, and compensates for the measured clock drift, and makes predictions of future clock drift values based on history and other physical measurements. Existing messages used for measuring link delay and / or used for time synchronization can be used for frequency measurement (and thus clock drift measurement), and this measured drift can be applied as a correction factor whenever synchronization is determined and / or used. The predicted clock drift rate can be based on various probability distributions including linear, Kalman filters, and / or others. Other embodiments may be described and / or claimed.