604results about "Synchronisation error correction" patented technology

A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2^N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

A multiple input multiple output (MIMO) calibration device (360) for calibrating a phase relationship between at least two signals present on at least two radio frequency (RF) paths coupling a wireless communication unit and the MIMO calibration device (360) is described. The MIMO calibration device (360) is operably coupleable via at least two RF paths between a wireless communication unit and an antenna arrangement (219). The calibration device (360) comprises a processing module (490) configured to: process a coupled amount of at least one first signal from a first path operably coupleable to a first polarisation of the antenna arrangement (219) to determine at least one pilot signal from said at least one first signal; process a coupled amount of at least one second signal from a second path operably coupleable to at least one second polarisation feed of antenna arrangement (219), different to the first polarisation, to determine the at least one pilot signal from said at least one second signal; and determine a first phase relationship of the same pilot signal between the at least two RF paths.

Disclosed are a wireless communication apparatus and a time synchronization method performed thereby.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

In the present invention, a method for synchronizing frequency and time in a wireless communication system and an apparatus for supporting the same are disclosed. Particularly, a method for synchronizing frequency and time performed by a terminal in a wireless communication system may include receiving a specific signal including a PSS, compensating the specific signal with at least one time offset candidate, generating at least one first differentiation value, generating at least one second differentiation value, calculating a cross correlation value between the at least one first differentiation value and the at least one second differentiation value, and estimating a time offset and a frequency offset of the PSS based on a time offset candidate that corresponds to a greatest cross correlation value among at least one cross correlation value calculated for at least one time offset candidate.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.

A method for determining an angle of arrival (AOA) of a received signal is disclosed, comprising: generating a baseband information signal by mixing a received signal with a local oscillator (LO) signal, the received signal being an in-phase signal and quadrature signal uncorrelated with each other and derived from different input data sets; obtaining baseband signal samples of the baseband information signal having an in-phase signal sample and a quadrature signal sample; determining a transmitter phase offset based on an estimated correlation between the in-phase signal samples and the quadrature signal samples; performing a plurality of phase measurements using a plurality of antennas to obtain a plurality of phase measurements; correcting the plurality of phase measurements based on the transmitter phase offset to produce a plurality of corrected phase measurement; and calculating an AOA of the received signal based on the difference between the plurality of corrected phase measurements.

A more cost effective wander jitter filter utilizes an excursion detector that receives a timing difference between a first signal and a second signal and supplies a first adjustment amount if a magnitude of the timing difference is above a predetermined threshold and otherwise supplies a second adjustment amount of zero. A summing circuit adjusts a magnitude of the timing difference by the first or second adjustment amount. A loop filter receives the summing circuit output and controls an oscillator. The excursion detector output (first adjustment value or zero according to the magnitude of the timing difference) is low pass filtered and the low pass filtered is reintroduced into the oscillator output or the feedback loop. The excursion detector output is accumulated and used to adjust a phase of the feedback signal from the oscillator.

The invention discloses a device and method for implementing a time-triggered Ethernet end system. Based on the Ethernet technology, the time-triggered Ethernet end system capable of transmitting time-triggered data and event-triggered data is implemented by increasing the functions of time synchronization and time trigger. A special protocol processing module of the device can process managementdata more conveniently; and a transmission processing module of the device can guarantee the reliability and the robustness of a network in the data transmission process. By adopting a precise clock synchronization protocol IEEE 1588, the method provided by the invention reduces the difficulty of implementing time synchronization on hardware, and has higher time synchronization stability and synchronization accuracy.

Circuits, methods, apparatus, and systems for recovering a clock from a spread spectrum signal having a periodic modulation profile. The circuits generally include an error detector circuit configured to compare the spread spectrum signal and a recovered clock signal, and to produce a first error signal corresponding to the periodic modulation profile and a second error signal corresponding to phase differences other than the spread spectrum modulation, a record and playback unit configured to record a value to a frequency memory, said value based on the first error signal and produce a third error signal corresponding to a predicted periodic modulation based at least in part on the recorded value, and a signal generator configured to produce the recovered clock signal in response to the second and third error signals.

An information processing apparatus is provided which includes a transmission unit for transmitting a query request for querying another device for a count value held by such other device, a reception unit for receiving a return of the count value from such other device, a correction unit for performing, at a predetermined period, correction processing for synchronizing sampling frequency with such other device based on the received count value, and a reproduction unit for reproducing content in synchronization with such other device based on the sampling frequency. The correction unit corrects by taking into account a Round Trip Time between the transmission of the query request and the reception of the return and residual difference occurred at a previous correction time.

Embodiments include systems and methods for using generalized pulse amplitude modulation (PAM-X) signaling with an at-rate not-return-to-zero (NRZ) clock data recovery (CDR) system. Some implementations include dual-mode signaling for an at-rate CDR (e.g., using standard NRZ signaling at lower operating frequencies and pseudo-NRZ signaling derived from PAM-X signaling at higher operating frequencies. Embodiments derive an apparent direction of signal transition from PAM-X signaling. The direction can be used to calculate pseudo-NRZ values. For example, when the PAM-X signal transitions in an upward direction, a pseudo-current NRZ value and a pseudo-previous NRZ value of ‘−1’ and ‘+1’ can be generated, respectively. An at-rate NRZ CDR can use the pseudo-NRZ values and a derived error value to make an offset determination. The offset determination can then be used to offset a generated clock signal in the CDR system.

A time synchronization system comprises a time master, a time slave, and a management node which are coupled to one another via a plurality of networks. The time master transmits to the time slave a time packet at a given timing through at least one of the plurality of networks. The time slave has a time correcting part for receiving the time packet transmitted from the time master and for correcting time based on the received time packet. The management node has: a network switching determining part for determining whether to switch the network for transmitting a time packet to another of the plurality of networks; and a network switching notifying part for notifying, in a case where it is determined that the network for transmitting the time packet is to be switched, information for identifying the switched-to network to the time slave.

The invention discloses a time domain joint synchronization method of downlinks, a receiving end and a system and belongs to the field of communication. The method includes the following steps: obtaining a to-be-analyzed sequence y from a received time domain signal; carrying out timed initial estimation after carrying out Alpha-multiple downsampling on the to-be-analyzed sequence y; carrying out frequency deviation initial estimation after carrying out frequency deviation compensation on the to-be-analyzed sequence y according to an integer-multiple frequency deviation estimation value Epsilon <^> obtained through use the timed initial estimation to obtain a decimal-multiple frequency deviation estimation value Epsilon <^> <f>; after carrying out frequency deviation compensation on the to-be-analyzed sequence y according to the integer-multiple frequency deviation estimation value Epsilon <^> and the decimal-multiple frequency deviation estimation value Epsilon <^> <f>, using a position interval estimated by an initial timing position and a main synchronization sequence to carry out timed reestimation so as to obtain an accurate timing position. The time domain joint synchronization method of the downlinks, the receiving end and the system solve a problem that the prior synchronization and frequency deviation estimation method is low in efficiency and long in consumed time and achieve an effect that the operation complexity is reduced and a timed synchronization result and a frequency deviation estimation result can be mutually combined to realize rapid synchronization is achieved.

Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.

A high sensitivity GPS receiver includes an acquisition engine and a tracking engine. The acquisition engine processes GPS satellite data at data rate that is substantially equal to twice the coarse acquisition (CA) code chip rate. This data rate advantageously enables the acquisition engine to process GPS satellite data with relatively less hardware area than traditional GPS acquisition approaches. In one embodiment, the high efficiency acquisition engine may be over-clocked, thereby allowing different phases of a CA code to be correlated quickly. The tracking engine can advantageously processes GPS satellite data at a data rate that does not have an integer relationship to the CA code chip rate.

A radio measurement apparatus comprising: an array antennal selection unit selecting array antennas corresponding to received signals; a reference path selection unit selecting a reference array antenna; a signal processing unit selecting a reference antenna channel through analysis of signal characteristics measured through two reception channels; a sequential channel multiplex unit determining sequentially inputting received signals of remaining array antennas to output the sequentially input signals to a receiver; and a correction signal input unit compensating amplitude and phase characteristics of the respective reception channels.

A method comprising generating a baseband information signal by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency; obtaining baseband signal samples of the baseband information signal having a baseband signal magnitude and a baseband signal phase; determining a cumulative phase measurement associated with baseband signal samples having a baseband signal magnitude greater than a threshold; and, applying a correction signal to compensate for an LO frequency offset of the LO frequency based on the cumulative phase.

The invention discloses a precise-point-positioning-based real-time time transfer method. According to the method, carrier phase and pseudorange data of a navigation satellite as well as a broadcasting ephemeris and a broadcasting on-board clock are measured and extracted by a measurement receiver; cycle slip detection and non-difference integer ambiguity resolution are carried out on real-time carrier phase data according to real-time ephemeris and on-board clock revised data broadcast by a network server in an IGS data center to obtain time difference between local time and satellite system time; and data exchange is carried out with a communication module after error correction is performed according to a classical precise point positioning model, thereby realizing real-time time transfer between two stations.

Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.