267results about "Synchronisation error correction" patented technology

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

Systems and methods for regaining phase synchronization between a CMTS core and an RPD, where the phase synchronization is regained over repeated temporal periods preferably divided between a first interval having a frequency adjustment of a first magnitude and a second interval having a frequency adjustment of a second magnitude.

The embodiment of the invention relates to the technical field of clock synchronization, and discloses a clock synchronization method and system, electronic equipment and a storage medium. The clock synchronization method comprises the steps that clock frequencies of a master chip and a slave chip are synchronized, and the master chip and the slave chip interact through an inter-chip communication channel; determining a clock calibration value, wherein the clock calibration value is used for representing a clock difference between the master chip and the slave chip; and according to the clock calibration value, carrying out clock calibration so as to synchronize the clocks of the master chip and the slave chip. The synchronization precision of the master chip and the slave chip is improved at least while additional interfaces are not introduced to the master chip and the slave chip.

A communication apparatus is provided that: adds data, obtained by sampling a repetitively arrived packet by a clock with a frequency that is N1-times a communication speed, to an addition result of previously arrived packets every time the packet arrives; holds a processing result of a first digital filter that processes the addition result in synchronization with a sampling clock; reproduces a clock waveform contained in bit data from a result of processing by a second digital filter, the second digital filter process, in synchronization with the sampling clock, an addition result obtained by adding data, which is obtained by sampling each bit constituting the arrived packet by the clock with a frequency that is N1-times a communication speed, to an addition result of previously arrived packet every time a next bit arrives; and reproduces a sampling clock synchronized with the arrived packet from the reproduced clock waveform.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

A clock circuit, a receiver, and a passive optical communication network system are disclosed. The clock circuit is applied to a receiver in a passive optical communication network and is configured to adjust the clock frequency of an output clock signal based on a transmission protocol, the clock circuit comprises at least one clock path and a frequency divider, and the at least one clock path comprises a first clock path; wherein the first clock path receives a reference clock signal from the first phase-locked loop circuit and a control signal from the clock data recovery circuit, and interpolates a conversion signal of the reference clock signal by using the reference clock signal so as to output a multi-phase clock signal; and the frequency divider receives the multi-phase clock signal and performs frequency division on the multi-phase clock signal based on a preset frequency division value, and the preset frequency division value is determined based on a transmission protocol. The clock circuit can be compatible with fast clock switching schemes of data rates of different PON protocols, so that the adaptability and the locking performance of a receiver in a burst mode are improved.

The present disclosure relates to the field of memory technologies and provides a data sampling circuit, comprising a first sampling module configured to respond to a signal from the data signal terminal and a signal from the reference signal terminal and to act on the first node and the second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on the third node and the fourth node; a latch module configured to input a high level to the first output terminal and input a low level to the second output terminal, or to input the low-level signal to the first output terminal and input the high-level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and an offset compensation module connected in parallel to the second sampling module and configured to compensate an offset voltage of the second sampling module. In this data sampling circuit, the second sampling module is additionally provided, and the offset compensation module is connected in parallel to the second sampling module, such that kickback noise is reduced.

A clock synchronization method is disclosed. The method comprises receiving master timing synchronization data from a master clock device, wherein the master timing synchronization data is based at least in part on quantum data obtained from a first quantum device of the master clock device. The method comprises determining local timing synchronization data that is based at least in part on local quantum data obtained from a second local quantum device, wherein the second local quantum device is entangled with the first quantum device such that the local quantum data and the quantum data obtained from the first quantum device are identical at a same time. The method comprises using the determined local timing synchronization data and the received master timing synchronization data to determine a timing correction factor. The method comprises correcting a local system time using the timing correction factor.

The invention discloses a frame synchronization method and device based on soft information filtering and dephasing ambiguity. Frame synchronization is performed by using demodulated soft information, and new strategies such as soft information filtering, phase ambiguity resolution, Doppler frequency estimation and compensation, dynamic frame header adjustment, multi-frame joint detection and adaptive judgment threshold are combined, so that the accuracy and robustness of frame synchronization are remarkably improved; the method is suitable for processing the frame synchronization problem of a long frame header in a low signal-to-noise ratio environment, and effectively solves the problem of phase ambiguity under the condition that the Doppler frequency change rate is large.

A first device includes a transceiver to communicate with a second device over an interposer, the interposer comprising a plurality of conductive traces between the first device and the second device. The first device also includes control logic, coupled to the transceiver associated with the first device, configured to send first data to the second device over a conductive trace of the plurality of conductive traces, simultaneously receive second data from the second device over the conductive trace, and extract the second data from a combined signal comprising the first data and the second data.

The vehicle control system includes an abnormality diagnosis unit for determining whether a synchronization abnormality between a master ECU and a slave ECU has occurred. The abnormality diagnosis unit transmits and receives a signal between the master ECU and the slave ECU and acquires time information. The slave ECU calculates a delay time of transmission based on the acquired time information. Then, the abnormality diagnosis unit first determines whether or not there is a periodic shift. When determining that there is no periodic deviation, the abnormality diagnosis unit determines whether or not there is an offset deviation based on the difference obtained by subtracting the delay time from the second time and the first time. The abnormality diagnosis unit determines that a synchronization abnormality has occurred when it is determined that there is a periodic deviation or when it is determined that there is the offset deviation.

The invention relates to the technical field of low-orbit satellite communication, and discloses a multi-channel simultaneous calibration method, system and device based on FDM (frequency division multiplexing) and a medium, which realize high-precision synchronous estimation and compensation of multi-channel amplitude, phase and delay parameters through a frequency division multiplexing and parallel processing mechanism based on FDM. The problem of channel inconsistency in coaxial cable FDM transmission is effectively solved, the calibration efficiency and the system transmission performance are remarkably improved on the premise that the high precision that the amplitude error is not larger than 0.2 dB, the phase error is not larger than 2 degrees and the delay error is lower than 0.01 sampling point is ensured, meanwhile, the calculation complexity and the sequence overhead are reduced, and the system performance is improved. The method is suitable for calibration requirements of high-frequency-width multi-channel systems such as a large phased array of a low-orbit satellite and the like.

The embodiments of the present application relate to the technical field of clock synchronization. Disclosed are a clock synchronization method and system, and an electronic device and a storage medium. The clock synchronization method comprises: synchronizing a clock frequency of a master chip with that of a slave chip, wherein the master chip interacts with the slave chip by means of an inter-chip communication channel; determining a clock calibration value, wherein the clock calibration value is used for representing a clock difference between the master chip and the slave chip; and performing clock calibration on the basis of the clock calibration value, so as to synchronize a clock of the master chip with that of the slave chip. Therefore, an improvement in the synchronization precision of a master chip and slave chip is at least facilitated while no additional interface is introduced onto the master chip and the slave chip.

The embodiment of the invention discloses a data synchronization method, device and system. In a scene of synchronizing data streams of a physical layer, the synchronization process of the data streams can be timed. Furthermore, whether the data stream with the time length meeting the timeout condition exists in the synchronization process is judged, which is equivalent to whether the situation that the synchronization time is too long exists. If the condition that the synchronization time is too long exists, it is indicated that a system fault or link deterioration may occur, then corresponding timeout processing, such as error reporting and system resetting, needs to be carried out, so that the system fault or link deterioration can be dealt with in time, and the data transmission efficiency is optimized.

The present disclosure provides techniques for measuring and compensating for clock drift errors in time-aware networks and time-sensitive applications, where a time-aware system (TAS) measures clock drift, and compensates for the measured clock drift, and makes predictions of future clock drift values based on history and other physical measurements. Existing messages used for measuring link delay and / or used for time synchronization can be used for frequency measurement (and thus clock drift measurement), and this measured drift can be applied as a correction factor whenever synchronization is determined and / or used. The predicted clock drift rate can be based on various probability distributions including linear, Kalman filters, and / or others. Other embodiments may be described and / or claimed.

A network devices includes multiple components including respective clocks that are synchronized with a global time. Each component includes one or more sensors and / or error detection circuitry that generate telemetry data. Each component associates the telemetry data with the global time, which enables time-correlation of telemetry data from the different components within the network device and / or from other network devices that also generate telemetry data associated with the global time.

The invention relates to the technical field of signal processing, and discloses a time slot control method and system for an inter-satellite link time division communication system, and the method comprises the steps: carrying out the clock domain crossing synchronization and jitter elimination processing of a pulse per second signal inputted externally, and detecting the validity of the processed pulse per second signal; extracting a time error between a local clock and an external clock based on the second pulse signal after validity detection; performing continuous health detection on the time error to generate a health state indication; performing second-order filtering processing on error information by referring to the health state indication and the time error, taking a processing result as an adjustment amount of a frequency control word of an NCO counter, and driving the NCO counter to generate a time reference; and detecting whether an external pulse per second signal is subjected to slip adjustment or not, and distributing a time slot control signal by using the time reference. Accurate distribution of time information is achieved, misreading of externally input time information is avoided, and the adaptive capacity of the system under different working conditions is improved.

To provide a system for surely authenticating a message, a vehicle and a method.SOLUTION: A system is provided with an authentication part for authenticating a message at least including control data transmitted and received between a plurality of on-vehicle devices and a first counter that is counted each time a power source is turned on by using at least the control data and the first counter in the case of authenticating the message including the control data exchanged between the plurality of on-vehicle devices. The authentication part authenticates a message including a second counter to be incremented over time without including the first counter transmitted and received between the on-vehicle devices, without using the second counter instead of the first counter in the case of confirming whether synchronization is performed between the plurality of on-vehicle devices.SELECTED DRAWING: Figure 3

The application discloses a kind of radio frequency synchronous signal circuit and synchronization method, belong to wireless communication technical field, solve the problem that existing device with full integration self-calibration function is difficult to meet miniaturization, low cost and wide frequency range synchronization demand;It includes radio frequency synchronous signal source, radio frequency synchronous signal source includes the phase detection circuit, FPGA circuit, DAC circuit, radio frequency circuit and output port connected in turn;The input end of phase detection circuit is respectively connected with two symmetrically arranged first frequency divider circuit and second frequency divider circuit in parallel.The full integration circuit of radio frequency synchronous signal source and automatic synchronization method are used in the application, miniaturization, low cost, wide frequency range and high-precision synchronization are realized, the port-to-port synchronization output of multi-channel radio frequency signal is realized, and the dependence on external equipment is eliminated and cable phase offset is compensated.

A method of reducing bit error rate in a PAM4 clock data recovery circuit is described. The method includes determining a first target value of a slicing level, sweeping down from an upper voltage threshold to determine a first reference voltage value, and detecting a first filtered analog output associated with the first reference voltage value. The method also includes sweeping up from a lower voltage threshold to determine a second reference voltage value and detecting a second filtered analog output associated with the second reference voltage value. The first reference voltage value and the second reference voltage value are averaged to determine a calculated threshold value.

Embodiments of this application provide an information transmission method, a communications device and system, and a computer-readable storage medium, and are applicable to information exchange inside an intelligent vehicle in the field of autonomous driving. In the embodiments of this application, a full counter value maintained by each ECU device includes a global counter value and a local counter value. The global counter value keeps globally synchronized in an entire CAN network, and the local counter value is obtained by each device performing counting by using a local counter. In this way, when a second device sends a CAN message, the CAN message carries a second counter value. When receiving the CAN message, the first device may determine whether a locally maintained first counter value matches the second counter value. If the locally maintained first counter value does not match the second counter value, the CAN message may be verified by using the second counter value and the global counter value. In this way, the technical solutions provided in the embodiments of this application can improve security and stability of an in-vehicle network of the intelligent vehicle.

A semiconductor device (10, 20) includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.

The present invention provides a communication signal timing error compensation method and device, which includes: processing a signal sent by a transmitter through upsampling, a shaping filter, a transmission channel, a matched filter, and downsampling in sequence to obtain time domain samples of the signal; convolving the filter coefficients of the shaping filter with the filter coefficients of the matched filter to obtain filter coefficients of the time domain samples, and extracting the effective filter coefficients of each time domain sample; constructing a matrix based on the effective filter coefficients of the time domain samples, extracting a submatrix from the matrix based on the number of delayed samples corresponding to each timing error, and calculating the timing compensation coefficient for each timing error based on the submatrix; querying the timing compensation coefficient corresponding to the actual timing error of the current signal, performing timing compensation on the current signal based on the timing compensation coefficient corresponding to the actual timing error, and obtaining a timing-compensated signal. The present invention has a simple structure and low computational complexity, effectively reducing computational complexity and storage space.

A light communication system, receiver, and method for synchronizing a receiver with a transmitter so as to decode a data input stream transmitted by the transmitter and received at the receiver. The method includes: receiving a data input stream at a receiver, the data input stream having a first data rate that is set based on a transmitter clock rate; generating a wave; obtaining a phase error between the data input stream and the generated wave; determining a synchronized clock rate by using the phase error to adjust the frequency of the generated wave so as to match the frequency of the generated wave to the transmitter clock rate of the data input stream; and using the synchronized clock rate to decode the data input stream so as to obtain data encoded in the data input stream.

The invention relates to the field of digital signal processing, in particular to a symbol synchronization method suitable for a THP wired communication system, which comprises the following steps of: preprocessing a baseband receiving symbol by using a feed-forward transverse filter (FFE), performing phase discrimination processing on the symbol processed by the FFE, obtaining an estimated value of the current receiving symbol through modulus and judgment in a phase discrimination processing part, and performing signal synchronization on the estimated value. Calculating an error between the received symbol and the estimated value, performing threshold comparison and compensation on the error, and correlating the compensated signal with an expected symbol to obtain sampling phase deviation information; and finally, the sampling deviation information is processed by using a direct path and an integral path of the loop filter and then is used for controlling the NCO to adjust the next sampling position. By processing the sampling phase error information in the linear domain, the influence of nonlinear modulus operation of THP on the phase discrimination algorithm is avoided, and low calculation complexity is maintained while the stability of the symbol synchronization method is improved.

The invention discloses a multi-path frequency-adjustable signal generation system based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of signal generation. The system comprises an adjustable frequency signal generation module, an FPGA register read-write control module, an SPI communication module and a top layer module. The top layer module adopts a generate block statement to realize batch instantiation of a multi-path signal output module, a positioning register mechanism is introduced, and a group of register resources are used for controlling a multi-path output channel, so that the problem of register resource waste caused by repeated instantiation of the module in the traditional design is effectively solved. According to the system, remote configuration of an FPGA internal register by a CPU is achieved through an SPI communication interface, and the frequency-adjustable signal generation module supports independent adjustment of parameters such as frequency, high pulse width and low pulse width. And when the positioning register is matched with a specific output channel and the data updating flag bit is valid, the system accurately sends the characteristic parameters to the corresponding channel, so that the accuracy of each path of signal parameters is ensured. According to the method, the code redundancy and the development time are remarkably reduced, and the system maintainability is improved.

An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

A media access control (MAC) processor of a network device receives a timing packet to be transmitted by the network device. The MAC processor generates one or more indicators to be used by a physical layer (PHY) device of the network device to embed timing information in the timing packet. The one or more indicators include at least an indicator indicating that the timing packet is a type of packet in which the timing information is to be embedded, an indicator of the location of a field in the timing packet in which the timing information is to be embedded, and an indicator of whether the timing information in the timing packet is to be updated. The MAC processor transmits the timing packet and the one or more indicators to the PHY device for further processing of the timing packet and subsequent transmission of the timing packet from the network device.

A device may apply a first signal to a device, the first signal comprising a long training field (LTF) and one or more data packets, the one or more data packets comprising one or more pilot tones. A device may demodulate the first signal. A device may compare power in the LTF to power of the one or more pilot tones. A device may determine gain vs. time based at least in part on comparing the power in the LTF to the power of the one or more pilot tones. A device may apply one or more corrections to the device based at least in part on the determined gain vs. time.