206 results about "Pulse-amplitude modulation" patented technology

Disclosed in the present invention is a non-autoregressive Transformer-based modeling method for a 4-level pulse amplitude modulation high-speed transmitter. The method involves establishing a deep learning model having an encoder-decoder architecture to predict the behavior of a 4-level pulse amplitude modulation transmitter. An encoder processes unordered non-sequential inputs, including an input signal parameter and link parameters, to generate a context vector and then transmit same to a decoder. The decoder uses both the context vector generated by the encoder and a transmitter output signal sequence to generate a categorical probability distribution for each point in the sequence one by one. The model is trained using a random masking strategy, and inference is performed by means of non-autoregressive decoding and filtering, so that the model can perform parallel prediction on an output sequence, and perform a filtering process to predict an output signal. Compared to traditional simulation methods, the present invention achieves a significant acceleration effect, particularly when processing multi-link systems.

The present application provides a display panel and a display device. Pulse width modulation modules of a plurality of sub-pixels included in the same sub-pixel group receive the same frequency sweep signal, and pulse width modulation modules and the pulse amplitude modulation modules of the plurality of sub-pixels included in the same sub-pixel group receive the same light emission control signal. The start time when pixel driving circuits of at least two of the sub-pixel groups provide flow paths for corresponding driving currents according to corresponding light emission control signals is different.

Proposed is a device for receiving a four-level pulse amplitude modulation (PAM-4) signal, which includes a first comparator for comparing a received PAM-4 signal with a predetermined threshold voltage to output a most significant bit (MSB) signal; and a second comparator for comparing the differential signal difference between the positive signal and negative signal of the received PAM-4 signal with a reference voltage to output a least significant bit (LSB) signal.

The present disclosure provides a pixel driving circuit and a display panel. An inversion control unit controls a potential of a second node to be a voltage corresponding to a first voltage signal or a second voltage signal based on a first scanning signal and a light-emitting control signal, so that a pulse width control unit improves the control speed of the signal transmission state between a first power supply terminal and the first node based on the potential of the second node, and a pulse amplitude modulation module improves the control speed of the light-emitting state of a light-emitting device based on a potential of the first node.

This disclosure relates to a receiver device for pulse amplitude modulation (PAM) signals. The receiver device calculates a transmitter dispersion eye closure quaternary (TDECQ). The receiver device first obtains a signal, wherein the signal is based on a PAM signal sent by a transmitter device over a channel to the receiver device, and filters the obtained signal. Further, the transmitter device equalizes the filtered signal using a FFE with multiple taps, and filters the equalized signal output by the FFE using a 2-tap post filter, wherein high frequency noise caused by the FFE is compressed. The receiver device applies a Max-Log-Map (MLM) algorithm on the filtered signal output by the 2-tap post filter, reconstructs a signal constellation of the PAM signal based on the result of the MLM algorithm, and calculates a TDECQ based on the reconstructed signal constellation.

A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input / output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input / output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input / output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input / output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

The invention provides a reference-clock-free clock data recovery device and a clock data recovery method thereof, and relates to the technical field of electronics. The reference-clock-free clock data recovery device comprises a linear phase discriminator used for carrying out phase discrimination processing on received four-level pulse amplitude modulation data and outputting a phase discrimination signal voltage; the frequency discriminator is used for carrying out frequency discrimination processing on the received phase discrimination voltage signal and outputting a frequency discrimination signal voltage; the first voltage-current converter is used for outputting pulse signal current; the loop filter is used for converting the pulse signal current into control voltage; the inductance-capacitance oscillator is used for converting the control voltage into an orthogonal clock signal; the self-biased multiphase clock generator is used for outputting a multiphase clock signal according to the orthogonal clock signal; and the starting circuit is used for discharging the control voltage to zero during power-on starting, so that the orthogonal clock signal is at the initial frequency, and traversal search of the control voltage is realized.

A bi-directional optical communication system employing a minimum number of single-mode high repetition rate pulsed optical signal sources to achieve cost efficiency while maintaining high data rates. The bi-directional optical communication system includes a first optical data processing unit and a second optical data processing unit. The first optical data processing unit modulates a pulsed optical source using a differential quadrature phase shift keying (DQPSK) modulation and two-level pulse amplitude (PAM-2) modulation and then demodulates it to achieve a pulse amplitude modulated signal. The second optical data processing unit reuses the same optical carrier by passing it through a regenerative wavelength converter to generate three pulsed optical carriers at different wavelengths and employs an On-off keying (OOK) modulation scheme. These carriers are employed to send uplink data at a same rate of as the downlink. As a result, large data is transmitted from one data center to another data center through a downlink and uplink free space optical link network.

A signal encoding and decoding protocol to convey discrete sets of information combined in a single carrier signal is disclosed. The protocol uses modulation of both amplitude and pulse width to carry multiple sets of information. A first signal is pulse width modulated to encode a first data and a second signal is pulse amplitude modulated to encode a second data. The two modulated signals are combined to generate a carrier signal encoded with both the first and second data.

Systems and devices are provided for receiving or transmitting IQ data (e.g., suitable for passband quadrature amplitude modulation (QAM)) over a wireline using pairs of baseband pulse amplitude modulation (PAM-n) signals. Encoding circuitry may map data from an input bit stream to IQ data that includes an in-phase component and a quadrature-phase component. Modulator circuitry may determine an in-phase PAM-n signal based on the in-phase component and a quadrature-phase PAM-n signal based on the quadrature-phase component. Driver circuitry may transmit the in-phase PAM-n signal and the quadrature-phase PAM-n signal across a wireline channel. The in-phase PAM-n signal may be different by 90° from the quadrature-phase PAM-n signal. This may enable a remote receiver on the wireline channel to detect the in-phase PAM-n signal independently of the quadrature-phase PAM-n signal.

SOLUTION: The present invention provides a pixel driving circuit and a driving method for the same, and a display panel. The pixel driving circuit includes a light-emitting element, a driving transistor, a pulse amplitude modulation module, and a pulse width modulation module that are electrically connected. The driving transistor is configured to generate driving current in order to drive to cause the light-emitting element to emit light. The pulse amplitude modulation module is configured to output an amplitude modulation voltage to the driving transistor in order to control an amplitude value of the driving current. The pulse width modulation module is configured to control a time for which the driving transistor outputs the driving current on the basis of a scan voltage.EFFECT: By combining the pulse amplitude modulation module and the pulse width modulation module, the uniformity of a display screen can be compensated and the arrangement of a feed forward circuit is no longer necessary, thus, this is advantageous in reducing the consumption power. The display panel includes the pixel driving circuit.SELECTED DRAWING: Figure 1B

A display device with combined pixel driving methods includes a pixel unit in which a plurality of pixels are arranged, each pixel including a luminous element and a pixel circuit connected to the luminous element, and a driver configured to generate and supply a driving current, a clock signal, and a driving method selection signal to the pixel unit, wherein the pixel circuit of each of the plurality of pixels drives light emission of the luminous element based on the driving method selection signal through one of a pulse width modulation (PWM) driving method or a pulse amplitude modulation (PAM) driving method.

An optical signal generation system for multi-level optical signal generation using binary keying comprises an array of light sources, a control circuit, and an optical coupling mechanism. The system may be operable to configure, using the control circuit, each of the light sources in the array of light sources in a HIGH or LOW state base on a received input signal to generate a plurality of optical output signals. The plurality of optical output signals may be communicated to the optical coupling mechanism and combined into a single optical signal thereby generating a multi-level output signal representative of the received input signal. The multi-level output signal may comprise a Pulse Amplitude Modulated (PAM) equivalent signal. The array of light sources may comprise vertical cavity surface emitting lasers (VCSELs), edge-emitting lasers, or light emitting diodes (LEDs).

Provided is a pixel including a first sub-pixel which displays a first color, and a second sub-pixel which displays a second color. Each of the first sub-pixel and the second sub-pixel includes a light-emitting element through which a driving current flows and a pulse width modulator which controls a width of the driving current. The first sub-pixel and the second sub-pixel share a pulse amplitude modulator which controls an amplitude of the driving current.

Provided are a pixel and a display device, the pixel including: a first sub-pixel displaying a first color; and a second sub-pixel displaying a second color. Each of the first sub-pixel and the second sub-pixel includes: a light emitting element through which a driving current flows; and a pulse width modulator that controls the width of the drive current. The first sub-pixel and the second sub-pixel share a pulse amplitude modulator that controls the amplitude of the drive current.

A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer / deserializer (SerDes) receiver is provided. The receiver may include an analog-front-end (AFE) block to receive a transmit signal, an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal, a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4, a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal, and a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal.

A dual-mode transmitter for a low-power double-data rate (LPDDR) interface can be operated in one of a non-return to zero (NRZ) mode and a pulse amplitude modulation (PAM)-4 mode. The dual-mode transmitter includes: a pseudorandom binary sequence (PRBS) generator configured to generate a transmission signal to be transmitted to a dual-mode receiver; at least one serializer configured to serialize the transmission signal; a single-ended to differential (S2D) configured to convert the serialized transmission signal in a form of a single-ended signal into a differential signal; a ZQ calibration configured to generate a result code for matching an impedance value at an output terminal of the dual-mode transmitter with a terminating resistance value of the dual-mode receiver; and a pre-driver configured to combine the differential signal obtained by the converting and the result code.

In various embodiments, the present disclosure includes a system for sending 50 gigabits per second (Gbps), 75 Gbps, and 100 Gbps at 50 gigabaud (GBaud) for passive optical networks (PON) downstream and upstream. The system allows for transmission of three data rates at a single baud-rate while only using 2-bits of information per sample. A motivation for sending three data rates at a single baud-rate is to allow for further granularity in the control of the data-rates for downstream and upstream traffic in a flexible PON system based on the link margin. For example, the system can use non-return-to-zero (NRZ) at 50 GBaud for 50 Gbps and can use four-level pulse-amplitude modulation (PAM-4) at 50 GBaud for 100 Gbps. In addition for 75 Gbps, a double square-8 (DSQ-8) constellation can be used at 50 GBaud.

A pixel driving circuit and a display panel. On the basis of a first scanning signal (Scan1) and a light-emission control signal (EM), an inverting control unit (201) controls the electric potential of a second node (N2) to be a voltage corresponding to a first voltage signal (VGH) or a second voltage signal (VGL), such that on the basis of the electric potential of the second node (N2), a pulse width control unit (202) increases a control speed for a signal transmission state between a first power source end (VDD_PWM) and a first node (N1), and on the basis of the electric potential of the first node (N1), a pulse amplitude modulation module (10) increases a control speed for a light-emission state of a light-emitting device (Di).

The application discloses a mode division multiplexing all-optical regenerative device, which comprises a polarization controller, a few-mode amplifier, an optical coupler, a few-mode nonlinear optical fiber, an optical carrier extractor and an optical phase shifter. Mode division multiplexing signals of multi-level pulse amplitude modulation from different users can be simultaneously regenerated by the mode division multiplexing all-optical regenerative device, the regenerated mode division multiplexing signals are amplified and shaped, and the power transfer curve of each mode channel is not affected by the change of other mode levels.

Provided are a wired transmission time division duplex system and a node device thereof. The node device comprises a receiver configured to receive a data frame; a transmitter configured to send a processed data frame; a frame header detection circuit configured to identify a frame header and a preamble in a non-return-to-zero coding format from the data frame based on a specific code sequence, and obtain frame header information accordingly, and detect a level jump edge in the frame header and the preamble, and output a reference clock signal based on the detection result; and a clock and data recovery circuit configured to map a multi-level digital signal of a data segment after the frame header and the preamble into binary data bits using a corresponding pulse amplitude modulation format based on the frame header information, and recover a local receiving clock based on the reference clock signal. The slave node device effectively overcomes the synchronization difficulty and slow clock recovery in a multi-level pulse amplitude modulation system.

Pixel circuit, comprising: light-emitting element (LD); driving transistor (DR); first circuit (514) including first capacitor (Cw) charged with first data voltage; second circuit (524) including second capacitor (Ca) charged with second data voltage; first circuit is configured to output discharge control signal (DIS) that instructs second capacitor to discharge in response to voltage change in first capacitor. Display device comprising: display panel; gate driver (Fig. 1; 120); data driver (Fig. 1; 110). Display panel including: plurality of data lines (Fig. 1; 102); plurality of gate lines (Fig. 1; 103); plurality of power lines; plurality of sub-pixels (Fig. 1; 101). Each sub-pixel including features of pixel circuitry. Data driver configured to output first data voltage corresponding to pulse width modulation (PWM) data and second data voltage corresponding to pulse amplitude modulation (PAM) data. Gate driver configured to output gate signal to plurality of gate lines. Display device, comprising: display panel, including at least one sub-pixel; controller. Controller configured to supply first and second data voltages to sub-pixel during one frame period, wherein luminance level adjusted based on first amplitude of first voltage data, emission period adjusted based on second amplitude of second data voltage.

Multiple examples are disclosed of SerDes transmitters and receivers. In one example, a transmitter comprises a mapping block to receive a clock signal and a two-bit data signal and to generate a plurality of pairs of digital values; a plurality of current steering blocks, each of the plurality of current steering blocks receiving one of the plurality of pairs of digital values to generate a pair of currents; a current summer and modulation block to receive the pair of currents from each of the plurality of current steering blocks to generate a differential output signal; wherein the differential output signal is a single frequency pulse amplitude modulated signal wherein the single frequency is a frequency of the clock signal.

The invention provides a wind turbine generator rotating shaft fault monitoring method and system based on pulse amplitude modulation. The method comprises the steps that pulse amplitude modulation signals of a rotating shaft are collected through a pulse amplitude modulation measuring device installed on a target shaft section of the rotating shaft of a measured wind turbine generator; performing amplitude demodulation on the pulse amplitude modulation signal to obtain an eccentric compound vibration component of the rotating shaft; carrying out discretization processing to obtain a composite vibration component sequence of a discrete time domain, then carrying out Fourier transform on the sequence of the discrete time domain to obtain phase differences, and extracting vibration amplitudes and amplitude characteristic parameters of each vibration component under different frequencies; and monitoring a misalignment abnormal state of the rotating shaft according to the vibration amplitudes, the amplitude characteristic parameters and the phase differences of the vibration components under different frequencies. According to the technical scheme, signals are collected through the pulse amplitude modulation measuring device, and high-precision monitoring and accurate fault type identification of the misalignment of the rotating shaft of the wind turbine generator are realized in combination with amplitude demodulation and frequency domain analysis.

A memory controller in an integrated circuit system performs bi-directional data transfer at a clock frequency between the memory controller and a memory module. The data transfer in a first direction is at a first pulse amplitude modulation (PAM) level and in a second direction at a second PAM level. When receiving an indication of an increased demand for data transfer in the first direction, the memory controller increases the first PAM level to a target PAM level for data transfer in the first direction while maintaining the clock frequency and the second PAM level in the second direction.

A display apparatus includes a pixel including a first sub-pixel including a first pulse width modulator outputting a first gate output signal for pulse width modulation in response to a first pulse width data and controlling a first driving current of a first light emitting element and a first pulse amplitude modulator applying the first driving current to the first light emitting element in response to a first pulse amplitude data, a second sub-pixel including a second pulse width modulator outputting a second gate output signal for pulse width modulation in response to a second pulse width data and controlling a second driving current of a second light emitting element and a second pulse amplitude modulator applying the second driving current to the second light emitting element in response to a second pulse amplitude data and an initializer initializing the first gate output signal and the second gate output signal.

Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and / or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

A photonic spin register includes: a shift register unit including a magnetic material layer having a shape extending in one direction; and a write unit configured to write spin information into a magnetic domain in the magnetic material layer by transferring information included in an optical signal that is a pulse amplitude-modulated and serial input signal, to a spin state of the magnetic domain in the magnetic material layer by means of a photocurrent corresponding to the optical signal or by irradiation with the optical signal. When a shift current flows through the shift register unit in the one direction, a domain wall is configured to move in the magnetic material layer, thereby allowing the spin information to move and be buffered in the magnetic material layer.

A pulse amplitude modulation transition density trigger in a test and measurement instrument is provided. A test and measurement instrument comprises: an input for receiving a pulse amplitude modulated n-level (PAMn) signal; an analog-to-digital converter (ADC) coupled to the input to digitize the PAMn signal; an acquisition memory coupled to the ADC and configured to store at least a portion of the digitized PAMn signal as a waveform; a trigger circuit coupled to the ADC and the acquisition memory and configured to generate a trigger signal to cause the test and measurement instrument to trigger acquisition of waveforms; a PAMn clock and data recovery (CDR) circuit configured to decode bits from the PAMn signal; and a conversion detection logic circuit coupled to the PAMn CDR circuit and the trigger circuit, and configured to detect a symbol conversion based on the decoded bits, and to cause the trigger circuit to generate a trigger signal in response to detecting a particular symbol conversion.

A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives from a processor a bit stream including a given symbol to be transmitted according to pulse-amplitude-modulation (PAM) with N signal levels on a first lane of multiple lanes. The lanes connect the transmitter module to a memory module in the integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk from other lanes on the first lane. The parameters are identified based on a pending transition in signal levels in each of the other lanes. The transmitter module superposes the parameters of the other lanes on the given symbol to adjust the given symbol on the first lane. A digital-to-analog converter (DAC) on the first lane generates an analog output to the memory module. The analog output represents the adjusted given symbol.