106 results about "Pulse-amplitude modulation" patented technology

Disclosed in the present invention is a non-autoregressive Transformer-based modeling method for a 4-level pulse amplitude modulation high-speed transmitter. The method involves establishing a deep learning model having an encoder-decoder architecture to predict the behavior of a 4-level pulse amplitude modulation transmitter. An encoder processes unordered non-sequential inputs, including an input signal parameter and link parameters, to generate a context vector and then transmit same to a decoder. The decoder uses both the context vector generated by the encoder and a transmitter output signal sequence to generate a categorical probability distribution for each point in the sequence one by one. The model is trained using a random masking strategy, and inference is performed by means of non-autoregressive decoding and filtering, so that the model can perform parallel prediction on an output sequence, and perform a filtering process to predict an output signal. Compared to traditional simulation methods, the present invention achieves a significant acceleration effect, particularly when processing multi-link systems.

An optical signal generation system for multi-level optical signal generation using binary keying comprises an array of light sources, a control circuit, and an optical coupling mechanism. The system may be operable to configure, using the control circuit, each of the light sources in the array of light sources in a HIGH or LOW state base on a received input signal to generate a plurality of optical output signals. The plurality of optical output signals may be communicated to the optical coupling mechanism and combined into a single optical signal thereby generating a multi-level output signal representative of the received input signal. The multi-level output signal may comprise a Pulse Amplitude Modulated (PAM) equivalent signal. The array of light sources may comprise vertical cavity surface emitting lasers (VCSELs), edge-emitting lasers, or light emitting diodes (LEDs).

Provided are a pixel and a display device, the pixel including: a first sub-pixel displaying a first color; and a second sub-pixel displaying a second color. Each of the first sub-pixel and the second sub-pixel includes: a light emitting element through which a driving current flows; and a pulse width modulator that controls the width of the drive current. The first sub-pixel and the second sub-pixel share a pulse amplitude modulator that controls the amplitude of the drive current.

A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer / deserializer (SerDes) receiver is provided. The receiver may include an analog-front-end (AFE) block to receive a transmit signal, an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal, a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4, a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal, and a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal.

A dual-mode transmitter for a low-power double-data rate (LPDDR) interface can be operated in one of a non-return to zero (NRZ) mode and a pulse amplitude modulation (PAM)-4 mode. The dual-mode transmitter includes: a pseudorandom binary sequence (PRBS) generator configured to generate a transmission signal to be transmitted to a dual-mode receiver; at least one serializer configured to serialize the transmission signal; a single-ended to differential (S2D) configured to convert the serialized transmission signal in a form of a single-ended signal into a differential signal; a ZQ calibration configured to generate a result code for matching an impedance value at an output terminal of the dual-mode transmitter with a terminating resistance value of the dual-mode receiver; and a pre-driver configured to combine the differential signal obtained by the converting and the result code.

The application discloses a mode division multiplexing all-optical regenerative device, which comprises a polarization controller, a few-mode amplifier, an optical coupler, a few-mode nonlinear optical fiber, an optical carrier extractor and an optical phase shifter. Mode division multiplexing signals of multi-level pulse amplitude modulation from different users can be simultaneously regenerated by the mode division multiplexing all-optical regenerative device, the regenerated mode division multiplexing signals are amplified and shaped, and the power transfer curve of each mode channel is not affected by the change of other mode levels.

Provided are a wired transmission time division duplex system and a node device thereof. The node device comprises a receiver configured to receive a data frame; a transmitter configured to send a processed data frame; a frame header detection circuit configured to identify a frame header and a preamble in a non-return-to-zero coding format from the data frame based on a specific code sequence, and obtain frame header information accordingly, and detect a level jump edge in the frame header and the preamble, and output a reference clock signal based on the detection result; and a clock and data recovery circuit configured to map a multi-level digital signal of a data segment after the frame header and the preamble into binary data bits using a corresponding pulse amplitude modulation format based on the frame header information, and recover a local receiving clock based on the reference clock signal. The slave node device effectively overcomes the synchronization difficulty and slow clock recovery in a multi-level pulse amplitude modulation system.

Multiple examples are disclosed of SerDes transmitters and receivers. In one example, a transmitter comprises a mapping block to receive a clock signal and a two-bit data signal and to generate a plurality of pairs of digital values; a plurality of current steering blocks, each of the plurality of current steering blocks receiving one of the plurality of pairs of digital values to generate a pair of currents; a current summer and modulation block to receive the pair of currents from each of the plurality of current steering blocks to generate a differential output signal; wherein the differential output signal is a single frequency pulse amplitude modulated signal wherein the single frequency is a frequency of the clock signal.

The invention provides a wind turbine generator rotating shaft fault monitoring method and system based on pulse amplitude modulation. The method comprises the steps that pulse amplitude modulation signals of a rotating shaft are collected through a pulse amplitude modulation measuring device installed on a target shaft section of the rotating shaft of a measured wind turbine generator; performing amplitude demodulation on the pulse amplitude modulation signal to obtain an eccentric compound vibration component of the rotating shaft; carrying out discretization processing to obtain a composite vibration component sequence of a discrete time domain, then carrying out Fourier transform on the sequence of the discrete time domain to obtain phase differences, and extracting vibration amplitudes and amplitude characteristic parameters of each vibration component under different frequencies; and monitoring a misalignment abnormal state of the rotating shaft according to the vibration amplitudes, the amplitude characteristic parameters and the phase differences of the vibration components under different frequencies. According to the technical scheme, signals are collected through the pulse amplitude modulation measuring device, and high-precision monitoring and accurate fault type identification of the misalignment of the rotating shaft of the wind turbine generator are realized in combination with amplitude demodulation and frequency domain analysis.

A memory controller in an integrated circuit system performs bi-directional data transfer at a clock frequency between the memory controller and a memory module. The data transfer in a first direction is at a first pulse amplitude modulation (PAM) level and in a second direction at a second PAM level. When receiving an indication of an increased demand for data transfer in the first direction, the memory controller increases the first PAM level to a target PAM level for data transfer in the first direction while maintaining the clock frequency and the second PAM level in the second direction.

A pulse amplitude modulation transition density trigger in a test and measurement instrument is provided. A test and measurement instrument comprises: an input for receiving a pulse amplitude modulated n-level (PAMn) signal; an analog-to-digital converter (ADC) coupled to the input to digitize the PAMn signal; an acquisition memory coupled to the ADC and configured to store at least a portion of the digitized PAMn signal as a waveform; a trigger circuit coupled to the ADC and the acquisition memory and configured to generate a trigger signal to cause the test and measurement instrument to trigger acquisition of waveforms; a PAMn clock and data recovery (CDR) circuit configured to decode bits from the PAMn signal; and a conversion detection logic circuit coupled to the PAMn CDR circuit and the trigger circuit, and configured to detect a symbol conversion based on the decoded bits, and to cause the trigger circuit to generate a trigger signal in response to detecting a particular symbol conversion.

A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives from a processor a bit stream including a given symbol to be transmitted according to pulse-amplitude-modulation (PAM) with N signal levels on a first lane of multiple lanes. The lanes connect the transmitter module to a memory module in the integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk from other lanes on the first lane. The parameters are identified based on a pending transition in signal levels in each of the other lanes. The transmitter module superposes the parameters of the other lanes on the given symbol to adjust the given symbol on the first lane. A digital-to-analog converter (DAC) on the first lane generates an analog output to the memory module. The analog output represents the adjusted given symbol.

The present disclosure provides a pixel driving circuit and a display device, and relates to the technical field of display, and comprises a pulse amplitude modulation circuit and a pulse width modulation circuit which are electrically connected, wherein the pulse amplitude modulation circuit is electrically connected with a light emitting element and is configured to provide a driving current to the light emitting element; the pulse amplitude modulation circuit is configured to control the amplitude of the driving current, and the pulse width modulation circuit is configured to control the pulse width of the driving current; the pulse amplitude modulation circuit comprises a light emitting branch connected with the light emitting element, the light emitting branch comprises a first driving transistor and at least one switching transistor, and at least one transistor in the light emitting branch is a double-gate double-channel transistor. The double-gate double-channel transistor is introduced in the light emitting branch, the output channel of the driving current is increased, and therefore the current transmission time is reduced, the power consumption of the pixel driving circuit is reduced, and the output capability of the pixel driving circuit for the driving current is improved.

Embodiments herein relate to a transmitter which can operate in a non-return-to-zero (NRZ) mode or a pulse amplitude modulation (PAM) mode with three or more levels. The transmitter includes a first driver which processes most significant bits and a second driver which processes least significant bits, in the PAM3 mode. In the NRZ mode, the second driver is turned off but resistances in the second driver are used to optimize impedance in the first driver. Switches can be turned on to couple in resistors in the first driver with resistors in the second driver, for pairs of driver slices. The switches are turned off in the PAM3 mode.

A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

The present disclosure provides a display device and a driving method thereof. The pixel driving circuit of the display device panel comprises a pulse amplitude modulation driving module and a pulse width modulation driving module. The pulse width modulation driving module includes a comparator, a plurality of transistors, and a capacitor. The comparator is configured to compare the voltage of the ramp signal and the voltage of the data signal and control the conduction state of the light-emitting device of the display panel. The driving method includes comparing a voltage of a ramp signal and a voltage of a data signal in a light-emitting phase to control a light emission time of a light-emitting device. The present disclosure can improve the low grayscale display effect and improve the display uniformity.

A system and method for distortion reduction. In some embodiments, a system for distortion reduction includes a transmitter comprising pulse amplitude modulation driver circuitry. The pulse amplitude modulation driver circuitry may include a main driver comprising a most significant bit (MSB) amplifier and a least significant bit (LSB) amplifier. The LSB amplifiers may include an upper arm and a lower arm, the strength of which is adjustable.

The present disclosure provides a pixel driving circuit and a display device, and relates to the technical field of display, and comprises a pulse amplitude modulation circuit and a pulse width modulation circuit which are electrically connected, wherein the pulse amplitude modulation circuit is electrically connected with a light emitting element and is configured to provide a driving current to the light emitting element; the pulse amplitude modulation circuit is configured to control the amplitude of the driving current, and the pulse width modulation circuit is configured to control the pulse width of the driving current; the pulse amplitude modulation circuit comprises a light emitting branch connected with the light emitting element, the light emitting branch comprises a first driving transistor and at least one switching transistor, and at least one transistor in the light emitting branch is a double-gate double-channel transistor. The double-gate double-channel transistor is introduced in the light emitting branch, the output channel of the driving current is increased, and therefore the current transmission time is reduced, the power consumption of the pixel driving circuit is reduced, and the output capability of the pixel driving circuit for the driving current is improved.

The present disclosure provides a pixel driving circuit and a display panel. An inversion control unit controls a potential of a second node to be a voltage corresponding to a first voltage signal or a second voltage signal based on a first scanning signal and a light-emitting control signal, so that a pulse width control unit improves the control speed of the signal transmission state between a first power supply terminal and the first node based on the potential of the second node, and a pulse amplitude modulation module improves the control speed of the light-emitting state of a light-emitting device based on a potential of the first node.

Pulse amplitude modulation (PAM) encoding for communication buses is disclosed. In particular, various two-wire communication buses can use three-level PAM (PAM-3) or five-level PAM (PAM-5) to encode bits to increase bit transmission without requiring an increase in clock frequency or the addition of additional pins. Avoiding an increase in clock frequency helps reduce the risk of electromagnetic interference (EMI), and avoiding the use of extra pins can avoid an increase in the cost of integrated circuits (ICs).

The embodiment of the invention discloses communication equipment and a signal processing method, and relates to the technical field of optical communication, the communication equipment comprises a signal processing device, the signal processing device comprises a processor and a signal modulator, and the processor is coupled with the signal modulator; the processor is used for selecting first modulation information corresponding to the temperature information from a preset mapping relation based on the temperature of the signal processing device and sending the first modulation information to the signal modulator, and the mapping relation is used for indicating modulation information corresponding to each temperature in the multiple temperatures; and the signal modulator is used for receiving the electric signal sequence from the digital signal device, performing pulse amplitude modulation on the electric signal sequence by using the first modulation information, and generating a modulated electric signal. According to the communication equipment and the signal processing method provided by the embodiment of the invention, the eye pattern distortion of the subsequently converted optical signal can be reduced.

A test and measurement instrument comprises an input for receiving a pulse-amplitude modulated n-level signal (PAMn), an analog-to-digital converter (ADC) coupled to the input to digitize the PAMn signal, a capture memory coupled to the ADC and configured to store at least a portion of the digitized PAMn signal as a waveform, a trigger circuit coupled to the ADC and the capture memory to generate a trigger signal to cause the test and measurement instrument to initiate waveform acquisition, a PAMn clock and data recovery (CDR) circuit configured to decode bits from the PAMn signal, and a transition detection logic circuit coupled to the PAMn CDR circuit and the trigger circuit to detect symbol transitions based on the decoded bits and to initiate the trigger circuit.The trigger signal is designed to generate a response to the detection of a specific symbol transition.

The embodiment of the invention discloses a data coding and decoding method, device and system. The invention discloses a device and a system. A coding method comprises the following steps: acquiring a first bit sequence containing k bits; the first bit sequence is coded to obtain a code word containing n bits, the code word comprises p = n-k check bits, and the result of multiplying the code word by a check matrix H is 0; wherein the check matrix H is a binary matrix with m + 1 rows and n columns. The coding method can be used for high-speed transmission scenes such as 800Gbps, 1.6 Tbps and the like. Meanwhile, in combination with the characteristics of the four-level pulse amplitude modulation (PAM4), the complexity of FEC coding and decoding can be reduced.

The invention discloses a method for balancing multipath interference and inter-symbol interference of an optical fiber link of an optical fiber communication system. Comprising the following steps: acquiring a pulse amplitude modulation signal from the optical transmitter, performing dual binary coding on the pulse amplitude modulation signal, performing filtering processing on the coded pulse amplitude modulation signal, and transmitting the filtered pulse amplitude modulation signal to an optical receiver; performing equalization training on the feed-forward equalizer by using the pulse amplitude modulation signal after the dual binary coding to obtain a trained feed-forward equalizer; obtaining the filtered pulse amplitude modulation signal from the optical receiver as a to-be-balanced receiving signal, and carrying out diode coding on the to-be-balanced receiving signal; and carrying out self-adaptive feed-forward equalization on the received signal coded by the diode by using the trained feed-forward equalizer, and decoding the equalized signal so as to recover a pulse amplitude modulation signal transmitted by the optical transmitter. According to the invention, multi-path interference and inter-symbol crosstalk balance of the optical fiber link can be realized.

Described apparatuses and methods are directed to equalization with pulse-amplitude modulation (PAM) signaling. As bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. Symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (DFE). DFE, however, can be expensive for chip area and power usage. Therefore, instead of applying DFE to all voltage level determination paths in a receiver, DFE can be applied to a subset of such determination paths. With PAM4 signaling, for example, a DFE circuit can be coupled between an output and an input of a middle slicer. In some cases, symbol detection reliability can be maintained even with fewer DFE circuits by compressing a middle eye of the PAM4 signal. The other two eyes thus have additional headroom for expansion. Encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.

A display panel. The display panel includes a plurality of pixel groups. Each pixel group includes a pulse width modulation control circuit and a plurality of sub-pixels. The pulse width modulation control circuit receives pulse width modulation data and a global light emission signal to provide a local light emission signal, wherein a pulse width of the local light emission signal is less than or equal to a pulse width of the global light emission signal. The plurality of sub-pixels individually have light emitting diodes, wherein the sub-pixels include a first sub-pixel that receives first pulse amplitude modulation data and the local light emission signal, wherein the first pulse amplitude modulation data determines a first drive current that flows through the light emitting diode of the first sub-pixel, and the local light emission signal determines a pass time of the first drive current that flows through the light emitting diode of the first sub-pixel.

The present disclosure relates to an image display apparatus and a video wall including the same. The image display apparatus according to an embodiment of the present disclosure includes: a panel with a plurality of light emitting diodes; and a driving controller configured to output a scan signal to the plurality of light emitting diodes during each of a plurality of subframe periods, wherein, in response to the gray level of a frame including a plurality of subframes being above a predetermined level, the driving controller outputs a data signal based on pulse width modulation to the light emitting diodes, and in response to the gray level of the frame being below the predetermined level, the driving controller outputs a data signal based on pulse amplitude modulation to the light emitting diodes while dividing the gray level of the frame and distributing the divided gray level across at least part of the subframes. Accordingly, it is possible to efficiently reduce flicker.

According to an aspect of the present disclosure, a display device includes a display panel in which a plurality of pixel groups is defined; one PAM circuit disposed in each of the plurality of pixel groups; a plurality of PWM circuits which is disposed in each of the plurality of pixel groups and is connected to one PAM circuit; a plurality of light emitting diodes which is disposed in each of the plurality of pixel groups and is connected to the plurality of PWM circuits. The plurality of PWM circuits is connected to an output terminal of one PAM circuit in parallel in each of the plurality of pixel groups. Accordingly, the plurality of PWM circuits shares one PAM circuit to reduce the number of overall transistors and simplify the structure of the display device.

Reduced complexity maximum likelihood sequence detectors (rMLSDs) for detecting multi-bit symbols, such as symbols found in pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM), and phase shift keying (PSK) signal constellations with more than two constellation points, are disclosed. One illustrative digital communication receiver includes an initial equalizer that derives an initial sequence of symbol decisions from a filtered received signal, each symbol decision in the initial sequence having a second possible symbol decision, and an rMLSD that derives a final sequence of symbol decisions by evaluating a state metric for only each symbol decision in the initial sequence and its second possible symbol decision.

A data communication system includes a link unit, a first communication unit, and a second communication unit. The first communication unit is connected to the link unit to transmit and receive pulse amplitude modulation (PAM) signals. The second communication unit is connected to the link unit to transmit and receive the PAM signals. The number of PAM signal levels is greater than or equal to the number of transmission lines, the sum of PAM values of each transmission line is “0”, and signal pairs with different signal levels of each transmission line are assigned to a vertex and a line segment of an inference graph diagram using graph coloring theory, and are defined as symbols according to a determined relationship. Each of the first communication unit and the second communication unit encodes and transmits transmission data to fit a corresponding symbol, and decodes and restores the received data.