543 results about "Clock generator" patented technology

An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

The invention relates to a phase-locked loop circuit, a clock generator, a chip and electronic equipment, and the phase-locked loop circuit mainly comprises a phase frequency detector which is used for generating a phase detection output signal according to the phase of a reference clock signal and the phase of a feedback clock signal; the proportional path module is used for generating a first control current according to the phase discrimination output signal; the integral path module is used for generating a second control current according to the phase discrimination output signal; the current control oscillation module is used for generating a clock output signal according to the first control current and the second control current; and the feedback frequency divider is used for obtaining a feedback clock signal through frequency division of the clock output signal. According to the phase-locked loop, the advantages of the analog charge pump phase-locked loop and the full-digital phase-locked loop are combined, the generation of a high-performance clock which is small in area, high in bandwidth, stable in loop and low in quantization noise is facilitated, the applicability of the phase-locked loop to the high bandwidth requirement is facilitated, the quantization noise is reduced, and the performance of the phase-locked loop is improved. And unconditional stability of the phase-locked loop is realized theoretically.

A receiving device, comprising: a clock generator circuit configured to generate a base clock signal; a counter configured to count cycles or edges of the base clock signal while a measurement pulse is received over a one-wire serial bus during a first transaction conducted over the one-wire serial bus, the measurement pulse having a pulse duration defined by a number of clock cycles of a transmitter clock signal; and a controller configured to adjust a count value of the counter when the counter is timing actuation of a trigger using a correction value that represents a difference between the cycles or edges of the base clock signal counted while the measurement pulse was being received and the number of clock cycles of the transmitter clock signal that defines the pulse duration.

The invention provides a multi-phase clock generator which outputs N injection current signals corresponding to different phases by processing an input clock signal, N is an integral multiple of 4, and a cross-coupled loop is arranged in a cross-coupled ring oscillator. The loop is respectively coupled with output nodes in N / 4 secondary ring oscillators based on a phase sequence, and the secondary ring oscillators realize high-working-frequency and high-stability oscillation frequency output and low-error phase alignment through a cross coupling mechanism, so that the secondary ring oscillators can output N oscillation clock signals with equally-spaced phases, and the phase alignment is realized. Since the injection current signal is input into each output node in the secondary ring oscillator based on the phase sequence, the frequency and the phase of the secondary ring oscillator are locked, the frequency is the same as the frequency of the input clock signal, and the phase noise is very low, so that the frequency and the phase of the secondary ring oscillator are locked. According to the invention, a high-speed multi-phase clock signal with low phase noise and high phase precision can be generated.

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

A disclosed charge pump includes first and second stages and, optionally, additional stage(s). The first stage receives a voltage input (Vin) at a first voltage (V1), CLK1 (GND, V1), and CLK1B (V1, GND), and outputs a first stage voltage output (Vout1) at a second voltage (V2) double V1. A second stage receives Vout1, CLK2 (V1, V2), and CLK2B (V2, V1, and outputs a second stage voltage output (Vout2) at a third voltage (V3) essentially triple V1, and so on. A clock driver supplies CLK1-CLK1B to the first stage and to a clock generator. The clock generator includes: a voltage level shifter, which receives CLK1 and CLK1B and outputs multiple level-shifted voltage output pulses; and a driving circuit, which receives specific ones of the output voltage pulses and outputs CLK2 and CLK2B to the second stage and, if needed, additional voltage level-shifted clock signal-inverted clock signal pairs to any additional stages.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

The invention relates to a method for realizing multi-channel ADC (Analog to Digital Converter) data synchronization processing based on an FPGA (Field Programmable Gate Array), which comprises the following steps that: the FPGA receives a clock frequency generated by an external clock generator and takes the clock frequency as a working clock of the FPGA; a plurality of groups of same-frequency clocks and same-phase clocks are generated in the FPGA and are respectively used as working clocks of the ADC chips; the FPGA receives sampling data of each ADC, an enable signal is set, and when the enable signal is effective, digital down-conversion, decimation filtering and FIR filtering are carried out on each sampling data; and after FIR filtering is completed, another enable signal ENend is generated, and data are further stored or transmitted to an upper computer. According to the method and the device for realizing the multi-channel ADC data synchronous processing based on the FPGA, the processor and the computer readable storage medium thereof, synchronous start and stop of the processing flow are controlled through the enable signals ENstart and ENend, synchronous processing of the multi-channel ADC data is ensured, accuracy and effectiveness are improved, and the method and the device have a wide application range.

The invention provides a frequency conversion sampling system and method, and relates to the technical field of electric power measurement, the system comprises a frequency measurement module, a clock generator module, an ADC module and a main control module, the frequency measurement module converts a measured AC signal into a target level signal; the main control module determines the current frequency of the detected AC signal based on the target level signal, and sends a frequency adjustment instruction to the clock generator module when the current frequency is different from the original frequency; the clock generator module provides a clock signal for the ADC module so as to drive the ADC module to sample according to a sampling frequency, and the sampling frequency is equal to a preset multiple of a current frequency; the ADC module performs voltage sampling and current sampling on the detected alternating current signal according to the sampling frequency to obtain a first digital signal and a second digital signal, and transmits the first digital signal and the second digital signal to the main control module; the main control module calculates a group of electrical parameters of the detected AC signal. By implementing the technical scheme provided by the invention, the measurement accuracy can be effectively improved.

Circuits and methods for multi-phase clock generators and phase interpolators are provided. The multi-phase clock generators include a delay line and multi-phase injection locked oscillator. At each stage of the multi-phase injection locked oscillator, injection currents are provided from a corresponding stage of the delay line. Outputs of the multi-phase injection locked oscillator and provided to mixers which produce inputs to an operational transconductance amplifier which provides feedback to the delay line and the multi-phase injection locked oscillator. The phase interpolator uses a technique of flipping certain input clock signals to reduce the number of components required while still being able to interpolate phase over 360 degrees and to reduce noise.

The invention provides a reference-clock-free clock data recovery device and a clock data recovery method thereof, and relates to the technical field of electronics. The reference-clock-free clock data recovery device comprises a linear phase discriminator used for carrying out phase discrimination processing on received four-level pulse amplitude modulation data and outputting a phase discrimination signal voltage; the frequency discriminator is used for carrying out frequency discrimination processing on the received phase discrimination voltage signal and outputting a frequency discrimination signal voltage; the first voltage-current converter is used for outputting pulse signal current; the loop filter is used for converting the pulse signal current into control voltage; the inductance-capacitance oscillator is used for converting the control voltage into an orthogonal clock signal; the self-biased multiphase clock generator is used for outputting a multiphase clock signal according to the orthogonal clock signal; and the starting circuit is used for discharging the control voltage to zero during power-on starting, so that the orthogonal clock signal is at the initial frequency, and traversal search of the control voltage is realized.

Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

Current balancing techniques. In an example, a circuit includes a synchronization terminal, an error amplifier, and a clock generator. The error amplifier is configured to generate a first control voltage signal based on a reference voltage and a power converter output voltage. The clock generator is configured to produce an outgoing clock signal having an outgoing clock frequency. The circuit further includes an encoder, a frequency detector, and a decoder. The encoder is coupled to the clock generator and synchronization terminal, and configured to encode the outgoing clock signal based on the first control voltage signal to provide, at synchronization terminal, an outgoing encoded clock signal. The frequency detector is coupled to synchronization terminal and configured to derive, from an incoming encoded clock signal, an incoming clock frequency. The decoder is coupled to synchronization terminal and configured to derive, from the incoming encoded clock signal, a second control voltage signal.

Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit die are synchronized using a synchronization circuit on one of the die. The synchronization circuit receives count phases and adjusts clock signals, and counts in some embodiments, to synchronize the processors. In one embodiment, the synchronization circuit comprises a phase detector that receives particular bits of the count signal as the count phases.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

The invention discloses a wireless audio data real-time transmission method based on hardware synchronization, and the method comprises the steps: hardware synchronous clock generation and management: a high-precision synchronous clock generator is integrated in a wireless audio module, and a high-precision synchronous clock signal is generated and used for controlling the sending and receiving time sequence of audio data; the synchronous clock generator adopts a clock chip with low power consumption and high stability. Through a high-precision synchronous clock and timestamp embedding mechanism, the real-time performance of audio data can be ensured, delay in the data transmission process is reduced, audio transmission can be synchronous and stable, a dynamic power consumption management mechanism intelligently adjusts power consumption according to audio flow and a network state, the energy consumption of battery power supply equipment is reduced, and the power consumption is reduced. The self-adaptive network transmission method improves the cruising ability of equipment, is particularly suitable for portable equipment, can detect the network condition in real time and adjust the transmission strategy according to the network change through the self-adaptive network transmission strategy, and effectively solves the problems of network delay, packet loss and the like.

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

Disclosed is an analog-to-digital converter (ADC) circuit for digitizing a pixel signal into a digital signal of positive integer (N) bits. The ADC includes a ramp generator, a clock, a comparator, and a counter. A system clock signal allows the ramp generator to generate a ramp signal and the clock generator to generate first to N-th clock signals. The comparator generates a comparison signal based on a comparison of the pixel signal, received from a pixel array, and the ramp signal. The counter includes an additional latch circuit and first to N-th latch circuits. The additional latch circuit generates an additional binary signal based on the system clock signal and the comparison signal, and the first to N-th latch circuits generate first to N-th latch signals based on the comparison signal and corresponding clock signal.

The invention provides a clock synchronization system and method for a DECT conversation system, a first clock of a conversation master station is synchronized by second clocks of one or more remote control units, a first clock source is arranged in the conversation master station, the first clock source is connected to a first clock generator, the first clock generator is connected with a first PHY chip, and the first PHY chip is connected with a second clock source. The first PHY chip is connected with the extended Ethernet interface; the remote control unit comprises a second PHY chip and a third PHY chip; the second PHY chip and the third PHY chip are respectively connected with the second clock generator; each remote control unit is further provided with a first interface and a second interface, the first interface is connected with the expanded Ethernet interface and the second PHY chip at the same time, the second interface is connected with the third PHY chip and the first interface of the other remote control unit at the same time, and the first interface and the second interface are sequentially linked, so that clock synchronization of the plurality of remote control units and the call master station is realized.

A charge transfer device having a charge transfer channel in a semiconductor substrate. The charge transfer channel is formed by overlap of the possible electrostatic effect of the gates with the conduction layer. A clock generator has a clock frequency of more than 100 MHz which applies changes in potential at the clock frequency to the gates, for transporting charge carriers at the clock frequency from adjacent regions of the overlap between adjacent gates and the conduction layer. The charge transfer channel in the region of one gate has a region of a constriction in which the cross-section in the flow direction decreases, and is arranged at least in the region of the gate upstream of the region of the protuberance or in the regions of the gate upstream of the protuberance and the adjoining gate of the protuberance.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

In a described example, a circuit includes a regulator circuit having a regulator output. A comparator circuit includes a voltage input, a clock input, and a signal output, in which the voltage input is coupled to the regulator output. A clock generator circuit has a second voltage input and the clock generator includes a programmable delay circuit, the programmable delay circuit having a signal input, a control input, and a clock output, in which the second voltage input is coupled to the regulator output, the signal input is coupled to the signal output, the clock output is coupled to the clock input. A controller includes a control output coupled to the control input.

A device (100) for packetizing of data from a set of sensors (10) comprises: a plurality of analog-to-digital converters, ADCs, (110a-n), each connected to a subset of sensors (10) and each comprising channels dedicated to respective sensors (10); a serializer (130) for generating a data packet (200) comprising data entries (210, 212, 220), each representing information from one channel of the ADCs (110a-n); a clock generator (140) for generating a clock signal; wherein the ADCs (110a-n) are configured to detect events and to output event information, wherein the clock generator (140) is configured to receive an enable signal for initiating generation of the clock signal in response to at least one event being detected in a time frame; wherein the clock generator (140) provides the clock signal to the serializer (130) for generating the data packet (200) comprising the event information output by the ADCs (110a-n) during the time frame.

The utility model relates to a clock source device and test equipment applied to multiple test machines, the clock source device comprises a clock distribution module and a calibration module, the clock distribution module comprises a clock generator and delay controllers, each delay controller is connected with the clock generator and the corresponding test machine, and the calibration module is connected with the clock generator. The calibration module is connected with each test machine and each delay controller; wherein the clock generator outputs a clock signal to each delay controller; the delay controller outputs a clock signal to a corresponding test machine, and adjusts the output clock signal according to the phase difference value output by the calibration module, so that the phase difference of the clock signal transmitted to the test machine is in a set error range; the calibration module receives a calibration clock of the test machine and outputs a phase difference value to the corresponding delay controller. The clock transmitted to the testing machine is adjusted by combining the phase difference value output by the calibration module, so that clock frequency synchronization and phase synchronization of different testing machines are realized, and the synchronization control accuracy is improved.

Aspects of the subject disclosure may include, for example, a multiphase clock generator having a plurality of digital phase interpolators each configured to create a generated clock signal according to an applied digital code, wherein a first digital code applied to a first digital phase interpolator and a second digital code applied to a second digital phase interpolator are chosen in a less precise range such that a first generated clock signal output by the first digital phase interpolator is as close to an ideal phase separation from a second generated clock signal output by the second digital phase interpolator, and wherein additional codes are applied to other digital phase interpolators in a more precise range to create generated clock signals having a deviation from an ideal separation from the first generated clock signal or the second generated clock signal that is less than a linear resolution of the applied digital code. Other embodiments are disclosed.

System-wide clock synchronization and latency reduction of audio signals in a wireless multi-channel audio system (WMAS). The apparatus includes: a base station and a wireless audio device. The base station includes: a master clock source; a framer operative to generate base station frames containing audio data and related audio clock timing derived from said master clock source; and a transmitter operative to transmit the frames over the WMAS. The wireless audio device includes: a receiver operative to receive frames from the base station over the WMAS; and a clock generator circuit operative to input a local clock signal generated by a frame synchronization circuit to generate therefrom multiple clocks derived from the timing signal to synchronize the wireless audio device to base station frames and to enable thereby communications according to a previously determined schedule with the base station.

A semiconductor device includes a multiphase clock generator generating clock signals by dividing a data clock signal, adjusting phases of the clock signals based on a control code set to generate a multiphase clock, a first data strobe module generating first and second serial signals from first and second data sequences using the multiphase clock, a phase error detector comparing a first length of a first rising period of the first serial signal and a second length of a second rising period of the second serial signal to generate a comparison result, a register storing the comparison result, and a control logic determining code values of the control code set by referring to the comparison result so that phase intervals between the clock signals are equalized with each other, and correcting a phase of the multiphase clock by storing the code values of the control code set in the register.

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.