192 results about "Clock generator" patented technology

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

In some embodiments, the phase adjustment circuit includes a clock generator that is configured to generate a sinusoidal clock signal, and may include a variable amplifier that is configured to receive the clock signal output from the clock generator as an input, output an amplitude-adjusted sinusoidal differential clock signal, and output an amplitude-adjusted in-phase signal. The phase adjustment circuit may include an adder that is configured to output a differential signal obtained by adding the in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier, a differential transmission line that includes two transmission lines configured to transmit the differential signal output from the adder, and a terminal circuit that is configured to terminate the differential transmission line where a signal is output from a terminal of any one of the two transmission lines.

This invention discloses a gate clock generator and a display device. The gate clock generator of the display device includes: a carry clock generator that sequentially generates N carry clock signals (N is an integer greater than or equal to 2) based on carry on and off clock signals; a scan clock generator that generates N scan clock signals based on scan on and off clock signals; and a sensing clock generator that generates N sensing clock signals based on sensing on and off clock signals. In a multi-clock mode, during the on-time of the Kth carry clock signal (K is an integer greater than or equal to 1 and less than N), the scan clock generator outputs a Kth scan clock signal having a number of pulses corresponding to the number of pulses of the scan on clock signal, and the sensing clock generator outputs a Kth sensing clock signal having a number of pulses corresponding to the number of pulses of the sensing on clock signal.

A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

A display device as described herein includes a microcontroller configured to operate in both an active mode and an idle mode, and includes a core configured to determine a touch position, a clock generator configured to generate a clock signal, and a first Pulse Width Modulation (PWM) generator configured to generate a PWM signal in the active mode using the clock signal, wherein the core operates at a reduced speed and power consumption in the idle mode compared to the active mode. The display device further includes a touch driver including a second PWM generator configured to generate a PWM signal based on a high pulse width, a low pulse width, a pulse count, and initial interval information of a PWM signal generated by the first PWM generator, wherein the touch driver determines whether a touch has occurred in the idle mode.

Embodiments of the present application provide a control system, method, device, electronic equipment and readable storage medium. The control system is applied to a server, and the control system comprises a clock generator and a detection module. In the clock generator, a plurality of clock signal output pins are connected to a plurality of corresponding control pins through lines to form a plurality of differential signal lines in the clock generator. The detection module is connected to the plurality of differential signal lines in the clock generator. The detection module is used for detecting whether the differential signal lines in the clock generator form a complete loop to obtain a detection result. According to the detection result, a result signal is returned to the clock generator. The clock generator is used for controlling whether the clock signal output pin corresponding to the differential signal line outputs the clock signal according to the received result signal. Through the control system of the embodiment, whether the clock signal is output can be automatically controlled, and the electromagnetic compatibility of the product can be improved while reducing the power consumption of the product.

An integrated circuit includes a comparator, a clock generator, and control circuitry. The comparator has a first input, a second input, and an output configured to provide an output clock. The clock generator is configured to generate a differential periodic signal formed from a first periodic signal and a second periodic signal. The clock generator provides the first periodic signal to the first input of the comparator and the second periodic signal to the second input of the comparator, and the clock generator is configured to vary an amplitude of the differential periodic signal based on a control input. The control circuitry is configured to measure hysteresis of the comparator by providing the control input to the clock generator to incrementally vary the amplitude of the differential periodic signal until detecting a predetermined number of state changes of the output clock.

According to the frequency adjusting system of the chip device and the chip device, a metal structure integrated on a back-end metal layer, a rewiring layer or a bonding layer of a chip is used as a temperature sensitive element, and the resistance value of the metal structure continuously changes along with the temperature of the chip in real time. And the resistance change is directly converted into voltage change applied to the reference voltage end of the clock generator, so that the clock generator can immediately respond and output corresponding clock frequency. And the change of the clock frequency further feeds back the influence on the chip temperature to form closed-loop control. According to the embodiment of the invention, through pure hardware circuit design, a direct, continuous and self-adaptive mapping relation between the temperature and the frequency is constructed, and dependence on a preset discrete temperature-frequency gear is not needed, so that adjustment delay or precision loss caused by insufficient fine gear division is avoided. According to the scheme, stepless, real-time and full-adaptive dynamic frequency regulation in a real sense is realized, the control logic is simplified, the system complexity is reduced, and the regulation response speed and the overall energy efficiency are remarkably improved.

Disclosed are a clock divider and a control method thereof, which enable retention work to be smoothly performed by ensuring that an output clock of the clock divider is in a low-level state in a retention signal conversion section. A clock divider according to an embodiment of the present invention comprises: a counter that counts clocks of an input clock and generates a counter output for dividing the input clock; an output clock generator that generates a generated clock edge according to the counter output, thereby generating an output clock divided from an input clock; and the state machine controls the counter according to a clock low level request of the power management unit, so that the output clock is in a low level state in a retention signal conversion interval.

A clock distribution network (10) including a clock generator (14) configured to generate at least a processor clock signal and at least a first peripheral clock signal, the clock generator including a processor clock output (31), a first peripheral clock output (32) and a first clock request input (42). A first peripheral unit (22) via a first clock request input (42) is operable to trigger the clock generator (14) to transmit the first peripheral clock signal via the first peripheral clock output (32).

A circuit includes a mixer having a first input, a second input, and an output. A clock generator has an output coupled to the second input of the mixer. An analog-to-digital converter (ADC) has an input coupled to the output of the mixer and has an output. A spur estimator has a first input, a second input, and an output. The first input of the spur estimator is coupled to the output of the ADC. A spur modification circuit has a first input, a control input and an output. The first input of the spur modification circuit is coupled to the second input of the spur estimator, and the control input is coupled to the output of the spur estimator. A transmitter has an input coupled to the output of the spur modification circuit and has an output coupled to the first input of the mixer.

An apparatus includes: a clock generator configured to generate a set signal fed to a set input of a latch; an error amplifier configured to generate a COMP signal; an offset generator configured to generate different offset voltages; and a comparator configured to generate a reset signal fed to a reset input of the latch, wherein the non-inverting input of the comparator is configured to receive a signal equal to the sum of a current sensing signal and a slope compensation signal, wherein the current sensing signal is equal to the current flowing through a power converter multiplied by an adjustable gain, and the inverting input of the comparator is configured to receive an error signal, wherein the error signal is equal to the COMP signal minus the offset voltage generated by the offset generator.

The invention belongs to the field of integrated circuit design, particularly relates to a fractional frequency divider circuit based on a digital time converter, and aims to solve the performance bottleneck caused by quantization errors in a fractional frequency division phase-locked loop. The circuit comprises three core modules, namely a differential integral modulator, a pulse swallowing multi-modulus frequency divider and a constant-slope digital time converter, wherein the differential integral modulator generates a multi-modulus frequency divider control word and a digital time converter control word according to integer and fractional frequency control words; the pulse swallowing multimode frequency divider receives an output signal of the voltage-controlled oscillator, and outputs a signal D1 and a time sequence control signal after frequency division processing; the constant slope digital-to-time converter time-converts D1 based on a control word and a timing signal, and outputs a delayed clock signal to counteract a quantization error. The femtosecond-level time delay circuit adopts an optimized circuit architecture design, has the characteristics of simple structure and low power consumption, realizes femtosecond-level time delay precision and high linearity, effectively inhibits phase noise and stray, is adaptive to various analog fractional frequency division phase-locked loop structures, remarkably improves the frequency spectrum purity and the system suitability of a clock generator, and has a wide application prospect. And the application requirements of the high-performance fractional frequency division phase-locked loop in the fields of wireless communication, radar and the like are met.

Certain aspects of the present disclosure are directed towards an interleaved sampling circuit. The interleaved sampling circuit generally includes: a clock generator having an input coupled to a main clock node and having a plurality of non-overlapping clock output nodes; and a plurality of sampling circuits, each of the plurality of sampling circuits having a first clock input coupled to a respective one of the non-overlapping clock output nodes and a second clock input coupled to the main clock node.

An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1→0) ST CLK # based on PCLK assertion (0→1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.

The present invention relates to a timepiece (100), in particular a wristwatch, comprising a first clock generator arrangement (1) for generating a first clock signal, a second clock generator arrangement (2) for generating a second clock signal, a useful signal generator (3), an electronic device (4), and a time display device (5). The useful signal generator (3) is configured to generate a useful signal based on the first clock signal. The electronic device (4) is configured to compare the frequency of the first clock signal with the frequency of the second clock signal and to modify the generation of the useful signal in response to this comparison. The time display device (5) is configured to display the time based on the useful signal. The first clock generator arrangement (1) is configured to continuously generate the first clock signal, and the second clock generator arrangement (2) is configured to generate the second clock signal in time segments including pauses.

An image sensor including: a pixel array including first to N-th pixel circuits to generate first to N-th pixel signals; an ADC connected to the pixel circuits; a system clock generator to generate a system clock signal; an internal clock generator to generate first to N-th clock signals and (N+1)-th to 2N-th clock signals based on the system clock signal; a ramp generator to generate first to N-th ramp signals based on the first to N-th clock signals; and a counter clock generator to generate first to N-th counter clock signals based on the (N+1)-th to 2N-th clock signals, the ADC includes: a comparator to generate first to N-th comparison signals based on comparison operations of the first to N-th pixel signals and the first to N-th ramp signals; and a counter to generate first to N-th digital signals based on the comparison signals and the counter clock signals.

This invention provides a video signal processing method, apparatus, system, and storage medium based on a video wall display. The video wall display includes at least two screens, each corresponding to the same clock generator. Each screen corresponds one-to-one with a video output interface of a decoding device. The method is applied to the decoding device and includes: sending a video signal to a target screen corresponding to the video output interface of the decoding device, so that the target screen determines the timing difference between the clock signal generated by the clock generator and the synchronization signal in the video signal; obtaining the timing difference from the target screen; and sending a new video signal to the target screen based on the timing difference. This invention can achieve image synchronization even with multiple decoding devices.

The invention discloses a double-edge multi-phase clock generator and a control method thereof, and belongs to the technical field of integrated circuit design. According to the method, the waveform freedom degree is improved through a three-stage time division architecture of'time period-round-period 'and in combination with a configuration mechanism of a plurality of programmable event points in each time period; configuration parameters are pre-stored in a register file module, and mode switching only needs to directly call pre-stored configuration, so that the real-time response capability is improved; the time control resolution is improved through double-edge counting, so that the sub-clock cycle control precision is achieved, and the method is suitable for high-precision application sensitive to power consumption and complex scene application.

Embodiments of this disclosure provide an apparatus and method for generating a circuit clock signal. The apparatus includes: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than the frequency of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on the selection signal.

The system includes a power stage for inverting an inputted power signal and for rectifying a received power signal. The system includes a trigger circuit for synchronizing wireless power transfer; a clock generator for generating a clock signal; a switching element electrically connected to the power stage, and selectively electrically connected to the trigger circuit and the clock generator, such that when the switching element electrically connects the clock generator to the power stage, a transceiver element is configured to transfer power by generating an electric field and / or a magnetic field, and when the switching element electrically connects the trigger circuit to the power stage, the transceiver element is configured to extract power from a generated electric field and / or a generated magnetic field.

The invention provides an adaptive switching method and device for an energy obtaining mode based on a radio frequency energy supply tag, relates to the technical field of circuit control, and is applied to an energy obtaining circuit. The energy obtaining circuit comprises a rectifier, an energy storage capacitor, a charge pump, a switched capacitor type step-down circuit, a low dropout linear regulator, a dummy load, a full charge judgment circuit, a clock generator, a timer and a switch control circuit. The method comprises the steps of obtaining direct-current voltage output by a rectifier; a dummy load is connected to the direct-current voltage, and a timer is started for timing; in the timing process, whether the direct current voltage reaches a preset threshold value or not is detected through a full-power judgment circuit, and a detection result is obtained; and based on the detection result and the timing ending signal, the control switch selects an energy storage mode or a direct connection mode to supply power to the radio frequency energy supply tag. In the mode, the energy storage mode and the direct connection mode are adaptively switched according to the magnitude of the radio frequency energy, high sensitivity and quick response are both considered, and the adaptability and the checking efficiency of the tag in a variable environment are remarkably improved.

A processing system includes a peripheral device configured to store security information and having a clock input to receive a gated clock; a watch clock generator configured to generate a watch clock having a reduced duty cycle relative to the system clock; and clock control circuitry configured to select the system clock as a gated clock during normal operation of the peripheral device and select the watch clock as a gated clock during a low power mode of the peripheral device. The watch clock generator may include a counter that counts system clock cycles and a clock pulse selector, such as a mode circuit, configured to select the cycles of the system clock to generate a watch clock. For multiple peripherals, the delay circuitry may skew a watch clock between two or more peripherals. A plurality of watch clocks having different delayed duty cycles may be generated, each for a corresponding group of a plurality of groups of peripherals.

This application discloses a low-power temperature-compensated RC oscillator, comprising a low-voltage linear buffer, an RC core circuit, a comparator, a Schmitt trigger, a non-overlapping clock generator, and a level shifter. The low-voltage linear buffer uses intrinsic transistors to reduce operating voltage and power consumption; the RC core circuit employs temperature compensation technology, including a series low-temperature drift resistor and a temperature-dependent current source, causing the equivalent resistance to increase with temperature; the comparator compares a triangular wave signal with a reference voltage and outputs a reference clock; the Schmitt trigger filters out clock glitches; the non-overlapping clock generator generates a two-phase clock with dead time to control charging and discharging; and the level shifter converts the low-voltage domain clock to the high-voltage domain. This oscillator eliminates the influence of comparator offset voltage through two-phase switching control and employs low-voltage and temperature compensation technology to achieve a high-precision, low-temperature drift reference frequency in a small area with low power consumption, making it suitable for compact sensing and measurement systems.

A pulse output device includes a digital pulse generator for outputting at least one output pulse triggered by a trigger signal. The digital pulse generator has a trigger input for the trigger signal and a clock input for a clock signal. The pulse output device further includes a clock generator for generating the clock signal, and a clock splitter. For synchronization of the clock signal with the trigger signal, the pulse output device is configured to stop the clock splitter, which is configured to reduce a clock rate of the clock signal, and / or to stop the clock generator before the clock signal is fed to the clock input of the digital pulse generator, and to restart the clock splitter and / or the clock generator synchronously with the trigger signal.

Embodiments herein describe a calibration circuit including a multi-phase clock generator configured to receive a clock signal and generate a multi-phase clock output, the multi-phase clock generator including a first injection-locked oscillator, a mixer, a current digital-to-analog converter (IDAC), and a voltage to current converter (VTOI), the IDAC and VTOI configured to fine tune offsets of the mixer and an input of the VTOI, and overcome phase errors from injection locking disturbance. The multi-phase clock generator further includes a pre-skew buffer configured to receive the multi-phase clock output from the multi-phase clock generator and generate multiple data signals and a phase interpolator (PI) configured to receive the multiple data signals from the pre-skew buffer and generate a shifted clock signal of the clock signal received by the multi-phase clock generator.

The utility model discloses PCM equipment, which belongs to the technical field of telecommunication, comprises an input interface, a signal amplifier, a sampling hold circuit, a signal conditioning circuit, an ADC (analog to digital converter) module, a clock generator, a power module, a digital processor, a memory, an Ethernet controller and a remote communication module, and solves the technical problems of sampling synchronization and high-precision sampling of the PCM equipment. According to the utility model, the tracking sampling holding circuit formed by the AD8250 amplifier and the AD503 is adopted, so that the accuracy and the stability of signals during high-frequency sampling can be ensured. The perfect alignment of time sequences among the modules in the system is ensured, and the problem of long-distance low-power-consumption data transmission is solved.

The described embodiments include a voltage regulator circuit with an amplifier having inputs coupled to a feedback voltage terminal and a reference voltage terminal. A comparator has a first comparator input coupled to the amplifier output, a second comparator input, and a comparator output. A current sensing circuit provides a current sensing output proportional to an output current. A waveform generator is coupled between the second comparator input and ground. A first latch input is coupled to the comparator output. A clock generator is coupled between a second latch input and ground. A terminal circuit has a first terminal input coupled to the current sensing output, a second terminal input coupled to a fixed voltage source, and a terminal output coupled to the first comparator input.The terminal circuit limits the first comparator input voltage to a terminal voltage that varies in response to the current sensing output.

This invention relates to a chopper amplifier, comprising a clock generator module, an input chopper module, an amplifier module, and an output chopper module. The clock generator module includes a zero-crossover aligned clock circuit, which outputs an intermediate clock based on the differential input signal and detects the zero-crossover point, aligning the edge of the intermediate clock to the zero-crossover point to generate an aligned chopper clock. The output chopper module is connected to a self-filling circuit, which, in conjunction with the chopper clock, samples the differential output voltage during the chopper steady-state phase and, during the chopper transition phase, forms a short circuit between the differential output nodes, causing the current polarity of the amplifier module to internally reverse, while simultaneously performing self-filling. By utilizing zero-crossover aligned chopper technology and / or self-filling technology, intermodulation distortion caused by chopping is suppressed or eliminated mechanistically without increasing power consumption or noise, significantly improving the linearity and usable input frequency range of the chopper amplifier.