421 results about "Clock generator" patented technology

The invention provides a multi-phase clock generator which outputs N injection current signals corresponding to different phases by processing an input clock signal, N is an integral multiple of 4, and a cross-coupled loop is arranged in a cross-coupled ring oscillator. The loop is respectively coupled with output nodes in N / 4 secondary ring oscillators based on a phase sequence, and the secondary ring oscillators realize high-working-frequency and high-stability oscillation frequency output and low-error phase alignment through a cross coupling mechanism, so that the secondary ring oscillators can output N oscillation clock signals with equally-spaced phases, and the phase alignment is realized. Since the injection current signal is input into each output node in the secondary ring oscillator based on the phase sequence, the frequency and the phase of the secondary ring oscillator are locked, the frequency is the same as the frequency of the input clock signal, and the phase noise is very low, so that the frequency and the phase of the secondary ring oscillator are locked. According to the invention, a high-speed multi-phase clock signal with low phase noise and high phase precision can be generated.

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

A disclosed charge pump includes first and second stages and, optionally, additional stage(s). The first stage receives a voltage input (Vin) at a first voltage (V1), CLK1 (GND, V1), and CLK1B (V1, GND), and outputs a first stage voltage output (Vout1) at a second voltage (V2) double V1. A second stage receives Vout1, CLK2 (V1, V2), and CLK2B (V2, V1, and outputs a second stage voltage output (Vout2) at a third voltage (V3) essentially triple V1, and so on. A clock driver supplies CLK1-CLK1B to the first stage and to a clock generator. The clock generator includes: a voltage level shifter, which receives CLK1 and CLK1B and outputs multiple level-shifted voltage output pulses; and a driving circuit, which receives specific ones of the output voltage pulses and outputs CLK2 and CLK2B to the second stage and, if needed, additional voltage level-shifted clock signal-inverted clock signal pairs to any additional stages.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

The invention relates to a method for realizing multi-channel ADC (Analog to Digital Converter) data synchronization processing based on an FPGA (Field Programmable Gate Array), which comprises the following steps that: the FPGA receives a clock frequency generated by an external clock generator and takes the clock frequency as a working clock of the FPGA; a plurality of groups of same-frequency clocks and same-phase clocks are generated in the FPGA and are respectively used as working clocks of the ADC chips; the FPGA receives sampling data of each ADC, an enable signal is set, and when the enable signal is effective, digital down-conversion, decimation filtering and FIR filtering are carried out on each sampling data; and after FIR filtering is completed, another enable signal ENend is generated, and data are further stored or transmitted to an upper computer. According to the method and the device for realizing the multi-channel ADC data synchronous processing based on the FPGA, the processor and the computer readable storage medium thereof, synchronous start and stop of the processing flow are controlled through the enable signals ENstart and ENend, synchronous processing of the multi-channel ADC data is ensured, accuracy and effectiveness are improved, and the method and the device have a wide application range.

The invention provides a frequency conversion sampling system and method, and relates to the technical field of electric power measurement, the system comprises a frequency measurement module, a clock generator module, an ADC module and a main control module, the frequency measurement module converts a measured AC signal into a target level signal; the main control module determines the current frequency of the detected AC signal based on the target level signal, and sends a frequency adjustment instruction to the clock generator module when the current frequency is different from the original frequency; the clock generator module provides a clock signal for the ADC module so as to drive the ADC module to sample according to a sampling frequency, and the sampling frequency is equal to a preset multiple of a current frequency; the ADC module performs voltage sampling and current sampling on the detected alternating current signal according to the sampling frequency to obtain a first digital signal and a second digital signal, and transmits the first digital signal and the second digital signal to the main control module; the main control module calculates a group of electrical parameters of the detected AC signal. By implementing the technical scheme provided by the invention, the measurement accuracy can be effectively improved.

Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit die are synchronized using a synchronization circuit on one of the die. The synchronization circuit receives count phases and adjusts clock signals, and counts in some embodiments, to synchronize the processors. In one embodiment, the synchronization circuit comprises a phase detector that receives particular bits of the count signal as the count phases.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

The invention discloses a wireless audio data real-time transmission method based on hardware synchronization, and the method comprises the steps: hardware synchronous clock generation and management: a high-precision synchronous clock generator is integrated in a wireless audio module, and a high-precision synchronous clock signal is generated and used for controlling the sending and receiving time sequence of audio data; the synchronous clock generator adopts a clock chip with low power consumption and high stability. Through a high-precision synchronous clock and timestamp embedding mechanism, the real-time performance of audio data can be ensured, delay in the data transmission process is reduced, audio transmission can be synchronous and stable, a dynamic power consumption management mechanism intelligently adjusts power consumption according to audio flow and a network state, the energy consumption of battery power supply equipment is reduced, and the power consumption is reduced. The self-adaptive network transmission method improves the cruising ability of equipment, is particularly suitable for portable equipment, can detect the network condition in real time and adjust the transmission strategy according to the network change through the self-adaptive network transmission strategy, and effectively solves the problems of network delay, packet loss and the like.

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

In a described example, a circuit includes a regulator circuit having a regulator output. A comparator circuit includes a voltage input, a clock input, and a signal output, in which the voltage input is coupled to the regulator output. A clock generator circuit has a second voltage input and the clock generator includes a programmable delay circuit, the programmable delay circuit having a signal input, a control input, and a clock output, in which the second voltage input is coupled to the regulator output, the signal input is coupled to the signal output, the clock output is coupled to the clock input. A controller includes a control output coupled to the control input.

A device (100) for packetizing of data from a set of sensors (10) comprises: a plurality of analog-to-digital converters, ADCs, (110a-n), each connected to a subset of sensors (10) and each comprising channels dedicated to respective sensors (10); a serializer (130) for generating a data packet (200) comprising data entries (210, 212, 220), each representing information from one channel of the ADCs (110a-n); a clock generator (140) for generating a clock signal; wherein the ADCs (110a-n) are configured to detect events and to output event information, wherein the clock generator (140) is configured to receive an enable signal for initiating generation of the clock signal in response to at least one event being detected in a time frame; wherein the clock generator (140) provides the clock signal to the serializer (130) for generating the data packet (200) comprising the event information output by the ADCs (110a-n) during the time frame.

The utility model relates to a clock source device and test equipment applied to multiple test machines, the clock source device comprises a clock distribution module and a calibration module, the clock distribution module comprises a clock generator and delay controllers, each delay controller is connected with the clock generator and the corresponding test machine, and the calibration module is connected with the clock generator. The calibration module is connected with each test machine and each delay controller; wherein the clock generator outputs a clock signal to each delay controller; the delay controller outputs a clock signal to a corresponding test machine, and adjusts the output clock signal according to the phase difference value output by the calibration module, so that the phase difference of the clock signal transmitted to the test machine is in a set error range; the calibration module receives a calibration clock of the test machine and outputs a phase difference value to the corresponding delay controller. The clock transmitted to the testing machine is adjusted by combining the phase difference value output by the calibration module, so that clock frequency synchronization and phase synchronization of different testing machines are realized, and the synchronization control accuracy is improved.

Aspects of the subject disclosure may include, for example, a multiphase clock generator having a plurality of digital phase interpolators each configured to create a generated clock signal according to an applied digital code, wherein a first digital code applied to a first digital phase interpolator and a second digital code applied to a second digital phase interpolator are chosen in a less precise range such that a first generated clock signal output by the first digital phase interpolator is as close to an ideal phase separation from a second generated clock signal output by the second digital phase interpolator, and wherein additional codes are applied to other digital phase interpolators in a more precise range to create generated clock signals having a deviation from an ideal separation from the first generated clock signal or the second generated clock signal that is less than a linear resolution of the applied digital code. Other embodiments are disclosed.

A semiconductor device includes a multiphase clock generator generating clock signals by dividing a data clock signal, adjusting phases of the clock signals based on a control code set to generate a multiphase clock, a first data strobe module generating first and second serial signals from first and second data sequences using the multiphase clock, a phase error detector comparing a first length of a first rising period of the first serial signal and a second length of a second rising period of the second serial signal to generate a comparison result, a register storing the comparison result, and a control logic determining code values of the control code set by referring to the comparison result so that phase intervals between the clock signals are equalized with each other, and correcting a phase of the multiphase clock by storing the code values of the control code set in the register.

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.

A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k−1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.

A pixel driving circuit for a display device includes a clock generator configured to generate clock signals with different time periods for different locations of bit values of the image data, an array of a plurality of pixels, each pixel including a light-emitting element, and an in-pixel memory configured to store image data comprising a set of bit values from a most significant bit (MSB) to a least significant bit (LSB), and a controller configured to read the set of bit values of the image data in an order, starting from the LSB bit to the MSB, to generate pulse width modulation (PWM) signals.

In some embodiments, the phase adjustment circuit includes a clock generator that is configured to generate a sinusoidal clock signal, and may include a variable amplifier that is configured to receive the clock signal output from the clock generator as an input, output an amplitude-adjusted sinusoidal differential clock signal, and output an amplitude-adjusted in-phase signal. The phase adjustment circuit may include an adder that is configured to output a differential signal obtained by adding the in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier, a differential transmission line that includes two transmission lines configured to transmit the differential signal output from the adder, and a terminal circuit that is configured to terminate the differential transmission line where a signal is output from a terminal of any one of the two transmission lines.

This invention discloses a gate clock generator and a display device. The gate clock generator of the display device includes: a carry clock generator that sequentially generates N carry clock signals (N is an integer greater than or equal to 2) based on carry on and off clock signals; a scan clock generator that generates N scan clock signals based on scan on and off clock signals; and a sensing clock generator that generates N sensing clock signals based on sensing on and off clock signals. In a multi-clock mode, during the on-time of the Kth carry clock signal (K is an integer greater than or equal to 1 and less than N), the scan clock generator outputs a Kth scan clock signal having a number of pulses corresponding to the number of pulses of the scan on clock signal, and the sensing clock generator outputs a Kth sensing clock signal having a number of pulses corresponding to the number of pulses of the sensing on clock signal.

A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

A method includes, during a time period A, in a computer storage element having first and second power inputs separated by an array of transistors, the computer storage element configured to store computer data bits, move an input of the array of transistors, a logic value "1" or "0" to a master latch; during a time period B, recovering at least a portion of the energy containing the input using the first clock; during a time period C, moving the input in the main latch to the isolation stage; recovering at least a portion of the energy containing the input from the isolation stage using a second clock during a time period D; during a time period E, recovering at least a portion of the energy containing the input from the slave latch using a third clock; and moving at least a portion of the input from the isolation stage to the slave latch during the time period F.

A display device as described herein includes a microcontroller configured to operate in both an active mode and an idle mode, and includes a core configured to determine a touch position, a clock generator configured to generate a clock signal, and a first Pulse Width Modulation (PWM) generator configured to generate a PWM signal in the active mode using the clock signal, wherein the core operates at a reduced speed and power consumption in the idle mode compared to the active mode. The display device further includes a touch driver including a second PWM generator configured to generate a PWM signal based on a high pulse width, a low pulse width, a pulse count, and initial interval information of a PWM signal generated by the first PWM generator, wherein the touch driver determines whether a touch has occurred in the idle mode.

Embodiments of the present application provide a control system, method, device, electronic equipment and readable storage medium. The control system is applied to a server, and the control system comprises a clock generator and a detection module. In the clock generator, a plurality of clock signal output pins are connected to a plurality of corresponding control pins through lines to form a plurality of differential signal lines in the clock generator. The detection module is connected to the plurality of differential signal lines in the clock generator. The detection module is used for detecting whether the differential signal lines in the clock generator form a complete loop to obtain a detection result. According to the detection result, a result signal is returned to the clock generator. The clock generator is used for controlling whether the clock signal output pin corresponding to the differential signal line outputs the clock signal according to the received result signal. Through the control system of the embodiment, whether the clock signal is output can be automatically controlled, and the electromagnetic compatibility of the product can be improved while reducing the power consumption of the product.

A low latency gearbox retimer architecture is provided. An apparatus includes a first clock generator configured to generate a first clock signal having a first frequency and a second clock signal having a second frequency; a control logic configured to generate a control signal based at least in part on the second clock signal; and two or more analog-to-digital converter (ADC) slices. Each respective ADC slice includes a multiplexer having a first number of inputs and a second number of outputs, where the multiplexer is configured to select a set of the second number of inputs to be output, where the selected set of the second number of inputs is based at least in part on the control signal. The apparatus includes one or more unit ADCs, wherein respective outputs of the one or more unit ADCs are coupled as inputs to the multiplexer.

The utility model relates to the field of medical instruments, and discloses a control system and a surgical robot system. The control system comprises a master reference module and at least one slave module, the main reference module comprises a main module clock generator used for generating a main module clock; the main controller is used for controlling the main reference module to broadcast a plurality of synchronous messages in a preset period under a main module clock; each slave module comprises a slave module clock generator used for generating a slave module clock; the slave controller is used for controlling the slave module to receive a plurality of synchronous messages in a preset period under the slave module clock; the master controller is also used for determining the receiving time of each slave module for receiving the plurality of synchronization messages, determining the clock drift amount of the slave module based on the receiving time, and sending the clock drift amount to the slave module for clock synchronization. And the problems of packet loss and the like caused by clock differences among different modules in the system can be avoided.

Processing unit circuitry of one or more computer devices that includes transistors configured to a first voltage threshold, and digital voltage sensor circuitry (160) of the computer devices that inc