307 results about "Clock generator" patented technology

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

In a described example, a circuit includes a regulator circuit having a regulator output. A comparator circuit includes a voltage input, a clock input, and a signal output, in which the voltage input is coupled to the regulator output. A clock generator circuit has a second voltage input and the clock generator includes a programmable delay circuit, the programmable delay circuit having a signal input, a control input, and a clock output, in which the second voltage input is coupled to the regulator output, the signal input is coupled to the signal output, the clock output is coupled to the clock input. A controller includes a control output coupled to the control input.

A semiconductor device includes a multiphase clock generator generating clock signals by dividing a data clock signal, adjusting phases of the clock signals based on a control code set to generate a multiphase clock, a first data strobe module generating first and second serial signals from first and second data sequences using the multiphase clock, a phase error detector comparing a first length of a first rising period of the first serial signal and a second length of a second rising period of the second serial signal to generate a comparison result, a register storing the comparison result, and a control logic determining code values of the control code set by referring to the comparison result so that phase intervals between the clock signals are equalized with each other, and correcting a phase of the multiphase clock by storing the code values of the control code set in the register.

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.

A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k−1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.

A pixel driving circuit for a display device includes a clock generator configured to generate clock signals with different time periods for different locations of bit values of the image data, an array of a plurality of pixels, each pixel including a light-emitting element, and an in-pixel memory configured to store image data comprising a set of bit values from a most significant bit (MSB) to a least significant bit (LSB), and a controller configured to read the set of bit values of the image data in an order, starting from the LSB bit to the MSB, to generate pulse width modulation (PWM) signals.

In some embodiments, the phase adjustment circuit includes a clock generator that is configured to generate a sinusoidal clock signal, and may include a variable amplifier that is configured to receive the clock signal output from the clock generator as an input, output an amplitude-adjusted sinusoidal differential clock signal, and output an amplitude-adjusted in-phase signal. The phase adjustment circuit may include an adder that is configured to output a differential signal obtained by adding the in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier, a differential transmission line that includes two transmission lines configured to transmit the differential signal output from the adder, and a terminal circuit that is configured to terminate the differential transmission line where a signal is output from a terminal of any one of the two transmission lines.

This invention discloses a gate clock generator and a display device. The gate clock generator of the display device includes: a carry clock generator that sequentially generates N carry clock signals (N is an integer greater than or equal to 2) based on carry on and off clock signals; a scan clock generator that generates N scan clock signals based on scan on and off clock signals; and a sensing clock generator that generates N sensing clock signals based on sensing on and off clock signals. In a multi-clock mode, during the on-time of the Kth carry clock signal (K is an integer greater than or equal to 1 and less than N), the scan clock generator outputs a Kth scan clock signal having a number of pulses corresponding to the number of pulses of the scan on clock signal, and the sensing clock generator outputs a Kth sensing clock signal having a number of pulses corresponding to the number of pulses of the sensing on clock signal.

A display device includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.

A display device as described herein includes a microcontroller configured to operate in both an active mode and an idle mode, and includes a core configured to determine a touch position, a clock generator configured to generate a clock signal, and a first Pulse Width Modulation (PWM) generator configured to generate a PWM signal in the active mode using the clock signal, wherein the core operates at a reduced speed and power consumption in the idle mode compared to the active mode. The display device further includes a touch driver including a second PWM generator configured to generate a PWM signal based on a high pulse width, a low pulse width, a pulse count, and initial interval information of a PWM signal generated by the first PWM generator, wherein the touch driver determines whether a touch has occurred in the idle mode.

Embodiments of the present application provide a control system, method, device, electronic equipment and readable storage medium. The control system is applied to a server, and the control system comprises a clock generator and a detection module. In the clock generator, a plurality of clock signal output pins are connected to a plurality of corresponding control pins through lines to form a plurality of differential signal lines in the clock generator. The detection module is connected to the plurality of differential signal lines in the clock generator. The detection module is used for detecting whether the differential signal lines in the clock generator form a complete loop to obtain a detection result. According to the detection result, a result signal is returned to the clock generator. The clock generator is used for controlling whether the clock signal output pin corresponding to the differential signal line outputs the clock signal according to the received result signal. Through the control system of the embodiment, whether the clock signal is output can be automatically controlled, and the electromagnetic compatibility of the product can be improved while reducing the power consumption of the product.

A low latency gearbox retimer architecture is provided. An apparatus includes a first clock generator configured to generate a first clock signal having a first frequency and a second clock signal having a second frequency; a control logic configured to generate a control signal based at least in part on the second clock signal; and two or more analog-to-digital converter (ADC) slices. Each respective ADC slice includes a multiplexer having a first number of inputs and a second number of outputs, where the multiplexer is configured to select a set of the second number of inputs to be output, where the selected set of the second number of inputs is based at least in part on the control signal. The apparatus includes one or more unit ADCs, wherein respective outputs of the one or more unit ADCs are coupled as inputs to the multiplexer.

An integrated circuit includes a comparator, a clock generator, and control circuitry. The comparator has a first input, a second input, and an output configured to provide an output clock. The clock generator is configured to generate a differential periodic signal formed from a first periodic signal and a second periodic signal. The clock generator provides the first periodic signal to the first input of the comparator and the second periodic signal to the second input of the comparator, and the clock generator is configured to vary an amplitude of the differential periodic signal based on a control input. The control circuitry is configured to measure hysteresis of the comparator by providing the control input to the clock generator to incrementally vary the amplitude of the differential periodic signal until detecting a predetermined number of state changes of the output clock.

According to the frequency adjusting system of the chip device and the chip device, a metal structure integrated on a back-end metal layer, a rewiring layer or a bonding layer of a chip is used as a temperature sensitive element, and the resistance value of the metal structure continuously changes along with the temperature of the chip in real time. And the resistance change is directly converted into voltage change applied to the reference voltage end of the clock generator, so that the clock generator can immediately respond and output corresponding clock frequency. And the change of the clock frequency further feeds back the influence on the chip temperature to form closed-loop control. According to the embodiment of the invention, through pure hardware circuit design, a direct, continuous and self-adaptive mapping relation between the temperature and the frequency is constructed, and dependence on a preset discrete temperature-frequency gear is not needed, so that adjustment delay or precision loss caused by insufficient fine gear division is avoided. According to the scheme, stepless, real-time and full-adaptive dynamic frequency regulation in a real sense is realized, the control logic is simplified, the system complexity is reduced, and the regulation response speed and the overall energy efficiency are remarkably improved.

A photoelectric conversion device is provided. The device includes a pixel array in which pixels are arranged, a drive controller configured to drive the pixel array, a horizontal transfer unit configured to sequentially output analog signals respectively output from columns of the pixel array, an AD converter configured to convert an analog signal output from the horizontal transfer unit into a digital signal, a first clock generator configured to generate a clock signal used to control an operation of the drive controller, and a second clock generator configured to generate a clock signal used to control the horizontal transfer unit and the AD converter. A clock tree in which a clock signal is distributed from the first clock generator and a clock tree in which a clock signal is distributed from the second clock generator form clock trees different from each other.

Disclosed are a clock divider and a control method thereof, which enable retention work to be smoothly performed by ensuring that an output clock of the clock divider is in a low-level state in a retention signal conversion section. A clock divider according to an embodiment of the present invention comprises: a counter that counts clocks of an input clock and generates a counter output for dividing the input clock; an output clock generator that generates a generated clock edge according to the counter output, thereby generating an output clock divided from an input clock; and the state machine controls the counter according to a clock low level request of the power management unit, so that the output clock is in a low level state in a retention signal conversion interval.

A clock distribution network (10) including a clock generator (14) configured to generate at least a processor clock signal and at least a first peripheral clock signal, the clock generator including a processor clock output (31), a first peripheral clock output (32) and a first clock request input (42). A first peripheral unit (22) via a first clock request input (42) is operable to trigger the clock generator (14) to transmit the first peripheral clock signal via the first peripheral clock output (32).

The present invention provides an electronic device, a clock calibration method, a storage medium, and a program product, which can be applied in the field of computer technology. The electronic device includes: a switch element electrically connected to a first controller, a processor, a clock generator, and a second controller; the second controller is configured to control the switch element to electrically connect the first controller to the clock generator when the electronic device is in an offline state; the first controller is configured to, when the first controller is electrically connected to the clock generator, perform a first calibration on the clock generator using a first reference time obtained from a time reference device to obtain a first calibrated clock generator; and, in response to an alarm signal sent by the first calibrated clock generator at a predetermined time, obtain a second reference time from the time reference device based on a first time difference between a first current system time of the first controller and the predetermined time, and perform a second calibration on the first calibrated clock generator using the second reference time.

The application provides a kind of server, spread spectrum setting method, program product, equipment and medium, can be applied to server technical field.The server includes: positioning component, for: acquisition multi-source initial positioning signal;Multi-source initial positioning signal is sent to baseboard management controller;Baseboard management controller, for: sending positioning instruction;Obtain multi-source initial positioning information;Multi-source initial positioning information is handled with time calibration, and multi-source time calibration positioning information is obtained;Multi-source time calibration positioning information is handled with space calibration, and multi-source target calibration positioning information is obtained;Each positioning information in multi-source target calibration positioning information is weighted fusion based on positioning weight, and target positioning information is obtained;In response to determining that target positioning information is included in preset geographic data set, generate spread spectrum control instruction;Clock generator, for receiving spread spectrum control instruction, in response to spread spectrum control instruction, start spread spectrum function.

A non-overlapping clock generator based on exclusive-NOR gates. The non-overlapping clock generator generates a non-overlapping in-phase output clock signal and an inverting output clock signal from an input clock signal. The non-overlapping clock generator includes first and second exclusive-NOR gates, first and second load transistors cross-coupled to each other, and first and second delay circuits coupled between the in-phase output clock signal and the control terminal of the first load transistor and between the inverting output clock signal and the control terminal of the second load transistor, respectively. Each exclusive-NOR gate includes at least one pass transistor logic to implement exclusive-NOR logic, the at least one pass transistor logic being coupled to the first control voltage. A non-overlapping period between the in-phase output clock signal and the inverting output clock signal is determined based on the first control voltage and / or the delay periods of the first and second delay circuits.

The application provides a normal-temperature dynamic burn-in device and method for a radio frequency digital mixed signal micro system, which comprises a burn-in control processor, a programmable clock generator electrically connected with the burn-in control processor, and a micro system burn-in test station; the radio frequency digital mixed signal micro system to be tested is connected on the micro system burn-in test station, the number of the micro system burn-in test stations is one or more than one, and each micro system burn-in test station can independently perform burn-in test and temperature control on one radio frequency digital mixed signal micro system to be tested. The application achieves the precise temperature control requirement of high consistency among the multiple chips in the micro system by reasonably designing the temperature control, state monitoring, chip temperature detection and control system and method of the micro system burn-in test station and the burn-in device, thereby realizing the micro system burn-in device without a temperature box; the burn-in method is easy to cascade and expand, and can be applied to the burn-in of micro systems in different batch scales, and is convenient for automatic monitoring and manual inspection.

A circuit includes a mixer having a first input, a second input, and an output. A clock generator has an output coupled to the second input of the mixer. An analog-to-digital converter (ADC) has an input coupled to the output of the mixer and has an output. A spur estimator has a first input, a second input, and an output. The first input of the spur estimator is coupled to the output of the ADC. A spur modification circuit has a first input, a control input and an output. The first input of the spur modification circuit is coupled to the second input of the spur estimator, and the control input is coupled to the output of the spur estimator. A transmitter has an input coupled to the output of the spur modification circuit and has an output coupled to the first input of the mixer.

A receiver includes a filter for receiving and filtering an input signal from a host; a signal processing part configured to separate data components and frequency components from the filtered input signal; a frequency detector configured to receive the separated frequency components of the input signal and detect period information; a first clock generator configured to generate a clock for a signal to be transmitted to the host based on the detected period information of the input signal; and a controller configured to control the frequency detector and the first clock generator to read back the signal to the host.

An apparatus includes: a clock generator configured to generate a set signal fed to a set input of a latch; an error amplifier configured to generate a COMP signal; an offset generator configured to generate different offset voltages; and a comparator configured to generate a reset signal fed to a reset input of the latch, wherein the non-inverting input of the comparator is configured to receive a signal equal to the sum of a current sensing signal and a slope compensation signal, wherein the current sensing signal is equal to the current flowing through a power converter multiplied by an adjustable gain, and the inverting input of the comparator is configured to receive an error signal, wherein the error signal is equal to the COMP signal minus the offset voltage generated by the offset generator.

The invention belongs to the field of integrated circuit design, particularly relates to a fractional frequency divider circuit based on a digital time converter, and aims to solve the performance bottleneck caused by quantization errors in a fractional frequency division phase-locked loop. The circuit comprises three core modules, namely a differential integral modulator, a pulse swallowing multi-modulus frequency divider and a constant-slope digital time converter, wherein the differential integral modulator generates a multi-modulus frequency divider control word and a digital time converter control word according to integer and fractional frequency control words; the pulse swallowing multimode frequency divider receives an output signal of the voltage-controlled oscillator, and outputs a signal D1 and a time sequence control signal after frequency division processing; the constant slope digital-to-time converter time-converts D1 based on a control word and a timing signal, and outputs a delayed clock signal to counteract a quantization error. The femtosecond-level time delay circuit adopts an optimized circuit architecture design, has the characteristics of simple structure and low power consumption, realizes femtosecond-level time delay precision and high linearity, effectively inhibits phase noise and stray, is adaptive to various analog fractional frequency division phase-locked loop structures, remarkably improves the frequency spectrum purity and the system suitability of a clock generator, and has a wide application prospect. And the application requirements of the high-performance fractional frequency division phase-locked loop in the fields of wireless communication, radar and the like are met.