292 results about "Clock phase" patented technology

The invention relates to the technical field of high-speed digital interfaces, and discloses a JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation, and the system comprises a main node which generates and dynamically distributes clock signals, and constructs a dynamic clock tree structure; the slave equipment is used for realizing cascade error elimination through a distributed compensation mechanism; the dynamic phase compensation engine adopts a hybrid phase detection framework and is combined with a digital-to-time converter (TDC) and an analog phase-locked loop (PLL); and the environment parameter compensation module is used for collecting temperature, voltage and operation time in real time, and calculating phase compensation quantity through a formula that delta phi = alpha * (T-T0) + beta * (V-V0) + gamma * delta t. On the aspect of synchronization precision, the phase error of a single device can be smaller than or equal to + / -200ps, the strict scene requirement is effectively met, the environment adaptability is high, the defects of traditional fixed compensation can be overcome, cascade error accumulation can be efficiently restrained through distributed compensation of slave devices, and on the aspect of real-time performance, an online calibration module can conduct real-time calibration without interrupting services.

The invention relates to the technical field of microcontrollers, and provides an MCU information protection method and device, electronic equipment and a readable storage medium, and the method comprises the steps: checking a storage access request according to an access control list; wherein the access control list comprises an authorized storage area and an authorized operation type corresponding to the authorized storage area; the storage access request is used for accessing a target storage area of the MCU; according to the debugging secret key, an interface debugging request is checked, and the interface debugging request is used for debugging a target debugging interface of the MCU; identifying a target code instruction of the MCU, and performing pre-execution verification and dynamic monitoring on the target code instruction; adjusting the clock frequency and the clock phase of the MCU according to the load change information and the power consumption change information of the MCU; and implementing encryption measures on the target data transmission channel of the MCU by using the encryption algorithm. According to the technical scheme provided by one or more embodiments of the invention, the data security and the anti-attack capability of the MCU can be improved.

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

The invention relates to a time synchronization parameter tracking method based on unknown Kalman filtering, which belongs to the technical field of time synchronization, and comprises the following steps: S1, modeling the output frequency of a clock crystal oscillator and the change rule of the temperature of the environment where the clock crystal oscillator is located into a quadratic function for a network communication scene with dynamic change of the environment temperature, introducing the temperature influence factor as an unknown quantity into a clock parameter tracking state equation; s2, establishing a clock observation equation by using a precise time synchronization protocol bidirectional information interaction process, and constructing a clock phase offset and clock frequency offset combined tracking state space model under the dynamic change of the environment temperature in combination with a clock state equation; and S3, by using unknown quantity Kalman filtering and taking minimum variance unbiased estimation as a criterion, jointly tracking a clock frequency offset value and a clock phase offset value for the established clock state space model.

The invention relates to a precise time synchronization parameter tracking method based on alternating minimization Kalman filtering, and belongs to the technical field of time synchronization. According to the method, timestamp noise is introduced into a clock synchronization parameter observation equation, and a state-space equation of clock synchronization parameter tracking is established in combination with a double-state clock model; a Kalman filtering method is used for tracking clock phase offset and frequency offset, and in the updating stage of Kalman filtering, an alternative minimization method is introduced for estimating the variance of timestamp noise and unknown observation noise in real time and correcting and updating Kalman gain. And furthermore, the influence of timestamp deviation and observation noise with unknown statistical characteristics on the clock synchronization parameter tracking precision is suppressed, and long-term effective tracking of the clock synchronization parameter is realized. According to the method, the problem that Kalman filtering is easy to diverge under unknown timestamp noise and observation noise is solved, joint tracking of clock phase offset and frequency offset can be realized, and the robustness and stability of clock synchronization are further improved.

Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

The invention discloses an Internet of Things flowmeter data compression sensing transmission optimization method and system, particularly relates to the field of low-power-consumption wireless communication networks, and is used for solving the problem of compressed sensing signal distortion caused by sampling time sequence misalignment in an LPWAN bandwidth limited environment. Constructing a local phase reference by extracting a pipeline vibration fundamental frequency component, and receiving a cloud synchronization reference timestamp alignment signal; fundamental frequency and third harmonic components are separated to calculate arrival time difference, and a phase-locked loop is triggered to dynamically adjust the phase of a sampling clock based on a pipeline material threshold value; after the stability of the zero crossing point time variance is verified, compressed sensing sampling is performed on the flow signal by adopting a phase synchronous clock, and an optimized compressed measurement value is generated and transmitted to the cloud through the LPWAN; through closed-loop cooperation of physical characteristics and a communication clock, complete capture of a signal sparse structure is guaranteed under a low-bandwidth condition, and cloud reconstruction precision is significantly improved.

This disclosure provides a charge pump circuit. The charge pump circuit according to this disclosure includes one or more cascaded boost units and output units having the same structure. Each boost unit has a dual-branch structure with top and bottom symmetry and connected to two sets of four-phase clock signals with opposite clock phases. By adjusting the phase relationship of the four-phase clocks, the rise time of the gate voltage of the transfer transistor can be delayed by advancing the falling edge of the driving clock of the secondary capacitor and delaying its rising edge. This ensures that the transfer transistor is in the off state at the moment of high-low phase switching, thereby avoiding the problem of reduced charge transfer efficiency caused by reverse charge flow between the input and output nodes of the boost unit.

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

The invention relates to a reference voltage optimization method, circuit and device, and the method comprises the steps: carrying out the sampling of data transmitted on at least one data line through changing the phase of a sampling clock, and obtaining a sampling clock phase interval under the condition that the sampling data on the at least one data line are all correct; obtaining an optimized sampling clock phase according to the sampling clock phase interval; sampling data transmitted on each data line in the at least one data line by optimizing a sampling clock phase and changing a sampling voltage to obtain an effective reference voltage interval of each data line; and obtaining an optimized reference voltage of each data line according to the effective reference voltage interval of each data line. According to the invention, the identification accuracy of the signal receiving end on the received signal can be improved, and the anti-interference capability of the signal receiving end on receiving the signal can be improved.

The invention discloses a power grid time frequency change trend prediction method and system based on intelligent electric meter data fusion, and the method comprises the steps: measuring the network transmission delay and time deviation between a master clock and a slave clock of a power grid, obtaining an initial time frequency deviation sequence, carrying out the error calibration, carrying out the data fusion after time domain alignment, and carrying out the prediction of the time frequency change trend. Generating a fusion time sequence; performing recursive estimation on the fusion time sequence, outputting an optimal time frequency deviation sequence, and performing synchronous estimation to obtain a clock phase error, a frequency error and frequency drift as state characteristic quantities; and training a preset machine learning prediction model by taking the optimal time frequency deviation sequence as a supervision signal and taking the state characteristic quantity of the corresponding moment as input, and obtaining a prediction result of the power grid time frequency change trend in the future period based on the trained time frequency change trend prediction model. According to the method, the power grid time synchronization precision and prediction capability are remarkably improved, and reliable technical guarantee is provided for stable operation of a power system.

An integrated circuit, a data transmission method across clock domains, an electronic device, and a storage medium. The integrated circuit includes a first clock domain and a second clock domain. The first clock domain includes a first pointer control module, and the second clock domain includes a second pointer control module. The first pointer control module includes a first synchronous pointer control module, and the first synchronous pointer control module is configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine a first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

The invention discloses a filter circuit, a clock data recovery method, a circuit and a receiver, and belongs to the technical field of signal processing. The filter circuit comprises: a voting module configured to vote according to at least two groups of input data to obtain a target voting result, and send the target voting result to a selection module, each group of input data comprising a clock phase and data, and the target voting result indicating a relative relationship between the clock phase and the data; the selection module is configured to determine a clock adjustment parameter according to the target voting result, obtain a target adjustment coefficient and send the clock adjustment parameter and the target adjustment coefficient to the processing module; the processing module is configured to obtain recovery parameters according to the clock adjustment parameters and the target adjustment coefficient, and the recovery parameters are used for recovering the clock and the data. The obtained recovery parameters are more accurate, noise is effectively suppressed, and the accuracy of recovering clocks and data based on the recovery parameters is improved.

The present invention relates to the technical field of data communication, and relates to a precise time synchronization clock parameter estimation method based on optimal invariant estimation. In the present invention, in a communication scene where unknown random time delay distribution information is present, on the basis of a precise time protocol, timestamp interaction is achieved by means of bidirectional data packet transfer between a master node and a slave node, and a clock relation model between the master node and the slave node is established; considering that a plurality of intermediate devices exist in the data packet interaction process, resulting that random time delay distribution information cannot be accurately obtained, a Gaussian mixture model is used to model a random time delay distribution, a competitive expectation maximization algorithm is used to learn mixture model parameters; and finally, on the basis of the parameters obtained by learning, an optimal invariant estimation method is used to estimate a clock frequency offset and a clock phase offset simultaneously, so as to realize time synchronization between the master node and the slave node. The present invention improves the accuracy of clock frequency offset estimation and clock phase offset estimation, is suitable for a communication scene where unknown random time delay distribution information is present, and enhances the robustness of the synchronization algorithm to a communication time delay.

The invention discloses a multi-channel multi-phase clock array based on an MEMS, and belongs to the field of radio frequency integration. Comprising a clock source circuit for generating reference signals of a multi-path multi-phase clock; the multi-phase clock generation circuit takes the reference signal output by the clock source circuit as an input signal, N paths of clocks are generated by using a delay phase-locked loop structure, and the phase difference of each path of clock is 2pi / N; according to the multi-phase clock calibration circuit, the multi-channel clocks of the multi-phase clock generation circuit are used as input signals of a controllable delay line array in the multi-phase clock calibration circuit, and after the multi-channel clocks output by the controllable delay line array are used for driving the multi-channel ADCs to sample the same sinusoidal signal, the same sinusoidal signal is output. A three-point IpDFT phase estimation algorithm is used for estimating the sampled sinusoidal signals to obtain the phase difference of multiple paths of clocks, and the delay of each path of the controllable delay line array is controlled according to the phase difference so as to calibrate the clock phase. Compared with a traditional multi-path and multi-phase clock structure, the multi-path and multi-phase clock structure has higher integration level, and the three-point IpDFT phase estimation algorithm is adopted, so that very high phase precision is achieved.

Systems and methods are disclosed for clock phase calibration between source logic and a coupled serial data link transmitter, enabling low-latency synchronization into the transmitter. In calibration mode, a phase relationship is monitored between a first clock, driving the source logic, and a second clock, tightly synchronized with a serial clock of the data link. The first clock is adjusted to a first phase at which the first and second clocks are aligned. The first clock phase is set for operation mode based on the first phase. Monitoring uses a D-type flip-flop as a phase detector. Adjustment is in steps of half the serial clock period. Variations are disclosed.

The present invention relates to the field of time synchronization, and relates to a precise clock synchronization parameter tracking method based on an augmented Kalman neural network. In the method, for a multi-hop network scenario where an ambient temperature changes and a link transmission delay is asymmetric, taking into account the impact of an accumulated asymmetric link transmission delay in a multi-hop network on clock synchronization accuracy, a multi-hop network clock observation equation containing an accumulated asymmetric link delay is derived, and on the basis of a quadratic polynomial model of a temperature and a clock frequency offset, a recursive state equation of the clock frequency offset and a temperature change is established; the evolution processes of an accumulated asymmetric delay and an unknown temperature coefficient are modeled as a first-order linear difference equation, and the accumulated asymmetric delay and the unknown temperature coefficient are augmented to a clock parameter tracking state space model; and an augmented Kalman neural network algorithm is used to realize joint tracking of a clock phase offset and a clock frequency offset of a slave node. This method employs a hybrid data-model-driven approach to perform joint tracking of the clock phase offset and frequency offset, thereby improving accuracy and robustness of clock parameter tracking.

Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.

The invention relates to the technical field of MEMS, and discloses an MEMS gyroscope closed-loop driving loop, a phase-locked loop circuit outputs a synchronous clock signal, and a clock generation circuit is used for performing gate logic operation, frequency division and layered delay addition on the synchronous clock signal to generate multiple groups of collaborative non-overlapping clock signals; a band-pass delta-sigma modulator, a CV conversion circuit and a digital signal processing module are controlled; meanwhile, through phase locking of a synchronous clock phase, a main sampling switch signal is synchronized with a falling edge of the synchronous clock phase, and the sampling phase is ensured to be 0 degree, so that a digital code stream signal of which the sampling phase is kept at 0 degree is output, and the sampling phase of the band-pass delta-sigma modulator is strictly synchronized with the mechanical vibration phase of the MEMS gyroscope; and phase deviation in the driving loop is eliminated. The digital signal processing module adjusts the amplitude and the phase of a feedback signal of the whole driving loop, so that the stability and the adjustability of the driving loop are improved under the condition that the MEMS gyroscope is driven under a proper condition.

The invention discloses a differential bus transmission verification system based on a digital ink-jet printer and a printer, and relates to the technical field of printing equipment data transmission, the system comprises a first main control module, a second main control module, 14 pairs of differential signal lines, a downlink channel and an uplink channel, a dynamic verification module adjusts the bit width of a verification code according to the type of a data packet, and the downlink adopts an enhanced CRC algorithm. An odd-even, accumulation and combination algorithm is used for uplink, the algorithm can be switched and retransmission is carried out when continuous error data packets are encountered; a time sequence control module is used for measuring transmission delay, adjusting a clock phase and guaranteeing transmission accuracy; a self-defined bus protocol is divided into three layers; a data packet structure and printing instruction analysis are stipulated; the system has an exception handling mechanism, speed reduction, redundant channel cutting, error recording and diagnosis report generation are performed when verification fails and exceeds a threshold value, a differential signal line is of a twisted-pair structure, signal stability is ensured, and the system is used for connecting a printer with a printing head drive and a motion platform and transmitting a control instruction to ensure reliable and stable data transmission.

The invention relates to a clock phase detection circuit and method, a delay phase-locked loop, a chip and electronic equipment, and the circuit comprises a frequency division module which is used for carrying out the frequency division processing of a reference clock signal selected from a plurality of input clock signals with the same frequency and different phases, and generating a frequency division clock signal; the clock driving module is used for grouping a plurality of input clock signals with the same frequency and different phases to generate at least two groups of input clock signals; the detection module is used for generating a detection signal according to a time interval between the reference clock signal and the feedback clock signal based on the frequency division clock signal and the at least two groups of input clock signals; wherein the feedback clock signal is an input clock signal of the previous phase of the reference clock signal. According to the invention, on the premise of not introducing an additional clock source, the detection of the clock phase can be quickly realized by using a plurality of input clock signals with the same frequency and different phases.

The invention relates to the technical field of phased array radars, in particular to a multi-channel synchronous digital TR assembly, which comprises a phase-locked loop module for receiving a first reference clock signal and performing phase locking on the first reference clock signal to output a second reference clock signal; the clock synchronization module carries out clock distribution based on the second reference clock signal so as to send a plurality of target clock signals with the same phase to corresponding target devices at the same time, and the target devices comprise a data processing FPGA, an analog-to-digital converter and a digital-to-analog converter in the digital TR assembly; the interface control FPGA is used for controlling the phase-locked loop module so as to enable the phase-locked loop module to carry out phase locking and output, and controlling the clock synchronization module so as to enable the clock synchronization module to carry out clock distribution; according to the digital TR assembly, the consistency of clock phases of all channels can be well ensured, so that clock synchronization among all target devices is ensured, and synchronous transmission of multi-channel signals is facilitated.

The present invention discloses a waveform synchronization method and device. After the system is turned on, a dot frequency signal with the same frequency and synchronization with a low-frequency reference clock is first generated. After passing through a signal link, it is fed back in the form of a clock to perform digital phase identification with the low-speed reference clock. By adjusting the signal link delay, the feedback clock and the reference clock phase are aligned, thereby achieving the certainty of the signal link delay. By adopting this idea similar to a phase-locked loop, the problems of uncertain delay and asynchrony between channels between the DAC and FPGA interface can be solved without using an ADC to collect feedback waveforms and perform complex correction calculations, significantly reducing the hardware complexity and cost of the system, and the digital phase identification speed and calibration speed are fast. In addition, the accuracy of the delay calibration mainly depends on the setup and hold time of the D flip-flop, which can achieve very high accuracy. The present invention also discloses a synchronous waveform generating device.

The invention relates to the technical field of laser inter-satellite link communication ranging, and provides an optimization method and device for improving the ranging precision of a laser inter-satellite communication ranging link, and the method comprises the steps: obtaining the sampling data of a photoelectric detection signal of the laser inter-satellite communication ranging link in real time; performing interpolation recovery on the sampling data according to the current loop interpolation parameter; performing clock phase error phase discrimination on the interpolation recovery data, wherein phase discrimination gain coefficient correction needs to be performed through real-time amplitude monitoring on the interpolation recovery data; filtering a clock phase error phase discrimination result; updating a loop interpolation parameter and a super-resolution code element phase accurate distance measurement result by using a filtered clock phase error phase discrimination result; and extracting a super-resolution code element phase accurate distance measurement result. According to the method, the phase discrimination gain coefficient is corrected in real time by monitoring the amplitude change in real time, so that the distance measurement precision does not change along with the amplitude of the received optical signal, and the distance measurement precision under the working condition of dynamic amplitude change of the laser inter-satellite link is improved.

The invention provides a jitter tolerance measuring device and a jitter tolerance measuring method, which can automatically calculate the confidence level of an output signal of a measured object when the jitter tolerance is obtained, and can quickly and easily confirm the confidence level of the jitter tolerance after a jitter tolerance test. A jitter tolerance measurement device is provided with: an error code measurement unit that measures, within a predetermined measurement time, an error measurement value of an output signal of a DUT that receives a code pattern signal synchronized with a jitter clock phase-modulated by a jitter modulation signal; a jitter tolerance measuring unit that changes the jitter amplitude and jitter frequency of the jitter modulation signal and estimates, for each jitter frequency, the maximum jitter amplitude at which the error measurement value measured by the error code measuring unit is equal to or less than a prescribed allowable value as the jitter tolerance of the DUT; a confidence level calculation unit that calculates a confidence level relating to an allowable value of the error rate of the output signal of the DUT; and a display unit that displays a result display screen showing the shake tolerance and the confidence level.

The invention relates to the technical field of communication networks, in particular to a DCI (Downlink Control Information) box electric layer system, a networking method and equipment, and the system comprises the following steps: a clock synchronization control module, an error code correction optimization module, a signal multiplexing management module, a flow scheduling execution module and a real-time energy consumption management module. According to the invention, through real-time extraction and analysis of the short-time frequency offset change rate, dynamic adjustment of clock phase compensation is realized, the precision and adaptability of clock synchronization are improved, intelligent adaptive optimization of error code correction parameters is realized through real-time analysis of error code fluctuation characteristics, redundant overhead is reduced, and dynamic statistics of bandwidth occupancy rate is combined, so that the accuracy and the adaptability of clock synchronization are improved. The method optimizes the channel resource allocation efficiency, avoids the resource waste, optimizes the transmission path priority by adopting the time delay change gradient analysis, effectively avoids the channel congestion, and reduces the equipment energy consumption through the dynamic monitoring of the link load and the optimization of the energy efficiency control.

The present invention discloses a method for reference clock phase synchronization and fine adjustment and a pulse generator. The method includes: Step 3, the host computer or the accelerator control system issues parameter configuration; Step 4, determine the reference clock selection mode; Step 5, when an external reference clock is selected, the pulse generator receives an external reference clock signal with a frequency of 10 MHz to 500 MHz; Step 6, according to the pulse parameter values set in Step 3, calculate the theoretically pulse repetition frequency count value, pulse width count value, and pulse delay count value. The present invention calculates the theoretically pulse repetition frequency count value, pulse width count value, and pulse delay count value through the parameter configuration issued by the host computer or the accelerator control system, enabling the pulse generator to generate stable and adjustable pulse signals with ns-level precision and to maintain phase synchronization with the input reference clock under different working conditions to meet different particle acceleration and control requirements.

The invention discloses a signal data receiving terminal for data recovery without a reference clock and a receiving method of the signal data receiving terminal, and relates to the technical field of clock data recovery. And the inner side of the fixing frame is fixedly connected with a terminal body which is used for receiving external data and is embedded into the clock body to recover the precision of the clock body. According to the signal data receiving terminal for data recovery without the reference clock and the receiving method of the signal data receiving terminal, external data are received through the terminal body, the terminal body exchanges timestamps, counteracts transmission delay and calculates clock skew through two-way communication, and the local clock frequency is adjusted through feedback control of the received signals, so that the data recovery efficiency is improved. When the terminal body starts to receive external data, the deformation metal sheet can pull the receiving antenna to move towards the outer side, the receiving antenna extends out of the interior of the terminal body to better receive the external data, and subsequent data recovery of a non-reference clock is facilitated.

The invention relates to the technical field of voice communication, and discloses a clock-buffer bidirectional linkage adjustment method and device for a voice gateway, and the method comprises the steps: obtaining a clock frequency error, and carrying out the compensation of a jitter buffer initial depth according to the clock frequency error, and obtaining a jitter buffer target depth; the jitter cache initial depth is a dynamic initial depth at the current moment determined based on a prediction model; based on the original depth of the jitter cache and the target depth of the jitter cache, determining a depth change rate corresponding to the jitter cache; and determining a dynamic gain of a clock phase-locked loop based on the depth change rate, and updating a clock signal according to the dynamic gain, thereby effectively improving the accuracy and reliability of voice playing by the voice gateway through clock-buffer bidirectional linkage adjustment.

The invention discloses an aperture error and non-linear cooperative calibration circuit and method for a pipeline ADC, and relates to the technical field of mixed signal integrated circuits, the circuit comprises a pipeline ADC basic circuit and a calibration circuit integrated with the pipeline ADC basic circuit, and the calibration circuit comprises an aperture error calibration module and a non-linear error calibration module. And the aperture error calibration module dynamically adjusts the sampling clock phase of the first-stage Sub-ADC by counting a post-stage output code value histogram and combining an SAR logic feedback mechanism so as to compensate the sampling moment deviation between the first-stage Sub-ADC and the MDAC. The nonlinear error calibration module extracts errors by injecting pseudo-random jitter and utilizing double-threshold window crossing statistics, and after EWMA smooth filtering is carried out, a polynomial compensation coefficient is updated in a self-adaptive mode through an LMS algorithm, and harmonic distortion is restrained. According to the method, the linearity under high-speed and high-bandwidth application is remarkably improved, and the method has good robustness for PVT fluctuation.