214 results about "Clock phase" patented technology

The invention discloses an Internet of Things flowmeter data compression sensing transmission optimization method and system, particularly relates to the field of low-power-consumption wireless communication networks, and is used for solving the problem of compressed sensing signal distortion caused by sampling time sequence misalignment in an LPWAN bandwidth limited environment. Constructing a local phase reference by extracting a pipeline vibration fundamental frequency component, and receiving a cloud synchronization reference timestamp alignment signal; fundamental frequency and third harmonic components are separated to calculate arrival time difference, and a phase-locked loop is triggered to dynamically adjust the phase of a sampling clock based on a pipeline material threshold value; after the stability of the zero crossing point time variance is verified, compressed sensing sampling is performed on the flow signal by adopting a phase synchronous clock, and an optimized compressed measurement value is generated and transmitted to the cloud through the LPWAN; through closed-loop cooperation of physical characteristics and a communication clock, complete capture of a signal sparse structure is guaranteed under a low-bandwidth condition, and cloud reconstruction precision is significantly improved.

This disclosure provides a charge pump circuit. The charge pump circuit according to this disclosure includes one or more cascaded boost units and output units having the same structure. Each boost unit has a dual-branch structure with top and bottom symmetry and connected to two sets of four-phase clock signals with opposite clock phases. By adjusting the phase relationship of the four-phase clocks, the rise time of the gate voltage of the transfer transistor can be delayed by advancing the falling edge of the driving clock of the secondary capacitor and delaying its rising edge. This ensures that the transfer transistor is in the off state at the moment of high-low phase switching, thereby avoiding the problem of reduced charge transfer efficiency caused by reverse charge flow between the input and output nodes of the boost unit.

The invention discloses a power grid time frequency change trend prediction method and system based on intelligent electric meter data fusion, and the method comprises the steps: measuring the network transmission delay and time deviation between a master clock and a slave clock of a power grid, obtaining an initial time frequency deviation sequence, carrying out the error calibration, carrying out the data fusion after time domain alignment, and carrying out the prediction of the time frequency change trend. Generating a fusion time sequence; performing recursive estimation on the fusion time sequence, outputting an optimal time frequency deviation sequence, and performing synchronous estimation to obtain a clock phase error, a frequency error and frequency drift as state characteristic quantities; and training a preset machine learning prediction model by taking the optimal time frequency deviation sequence as a supervision signal and taking the state characteristic quantity of the corresponding moment as input, and obtaining a prediction result of the power grid time frequency change trend in the future period based on the trained time frequency change trend prediction model. According to the method, the power grid time synchronization precision and prediction capability are remarkably improved, and reliable technical guarantee is provided for stable operation of a power system.

The invention discloses a multi-channel multi-phase clock array based on an MEMS, and belongs to the field of radio frequency integration. Comprising a clock source circuit for generating reference signals of a multi-path multi-phase clock; the multi-phase clock generation circuit takes the reference signal output by the clock source circuit as an input signal, N paths of clocks are generated by using a delay phase-locked loop structure, and the phase difference of each path of clock is 2pi / N; according to the multi-phase clock calibration circuit, the multi-channel clocks of the multi-phase clock generation circuit are used as input signals of a controllable delay line array in the multi-phase clock calibration circuit, and after the multi-channel clocks output by the controllable delay line array are used for driving the multi-channel ADCs to sample the same sinusoidal signal, the same sinusoidal signal is output. A three-point IpDFT phase estimation algorithm is used for estimating the sampled sinusoidal signals to obtain the phase difference of multiple paths of clocks, and the delay of each path of the controllable delay line array is controlled according to the phase difference so as to calibrate the clock phase. Compared with a traditional multi-path and multi-phase clock structure, the multi-path and multi-phase clock structure has higher integration level, and the three-point IpDFT phase estimation algorithm is adopted, so that very high phase precision is achieved.

Systems and methods are disclosed for clock phase calibration between source logic and a coupled serial data link transmitter, enabling low-latency synchronization into the transmitter. In calibration mode, a phase relationship is monitored between a first clock, driving the source logic, and a second clock, tightly synchronized with a serial clock of the data link. The first clock is adjusted to a first phase at which the first and second clocks are aligned. The first clock phase is set for operation mode based on the first phase. Monitoring uses a D-type flip-flop as a phase detector. Adjustment is in steps of half the serial clock period. Variations are disclosed.

The present invention relates to the field of time synchronization, and relates to a precise clock synchronization parameter tracking method based on an augmented Kalman neural network. In the method, for a multi-hop network scenario where an ambient temperature changes and a link transmission delay is asymmetric, taking into account the impact of an accumulated asymmetric link transmission delay in a multi-hop network on clock synchronization accuracy, a multi-hop network clock observation equation containing an accumulated asymmetric link delay is derived, and on the basis of a quadratic polynomial model of a temperature and a clock frequency offset, a recursive state equation of the clock frequency offset and a temperature change is established; the evolution processes of an accumulated asymmetric delay and an unknown temperature coefficient are modeled as a first-order linear difference equation, and the accumulated asymmetric delay and the unknown temperature coefficient are augmented to a clock parameter tracking state space model; and an augmented Kalman neural network algorithm is used to realize joint tracking of a clock phase offset and a clock frequency offset of a slave node. This method employs a hybrid data-model-driven approach to perform joint tracking of the clock phase offset and frequency offset, thereby improving accuracy and robustness of clock parameter tracking.

Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.

The invention relates to the technical field of phased array radars, in particular to a multi-channel synchronous digital TR assembly, which comprises a phase-locked loop module for receiving a first reference clock signal and performing phase locking on the first reference clock signal to output a second reference clock signal; the clock synchronization module carries out clock distribution based on the second reference clock signal so as to send a plurality of target clock signals with the same phase to corresponding target devices at the same time, and the target devices comprise a data processing FPGA, an analog-to-digital converter and a digital-to-analog converter in the digital TR assembly; the interface control FPGA is used for controlling the phase-locked loop module so as to enable the phase-locked loop module to carry out phase locking and output, and controlling the clock synchronization module so as to enable the clock synchronization module to carry out clock distribution; according to the digital TR assembly, the consistency of clock phases of all channels can be well ensured, so that clock synchronization among all target devices is ensured, and synchronous transmission of multi-channel signals is facilitated.

The invention relates to the technical field of laser inter-satellite link communication ranging, and provides an optimization method and device for improving the ranging precision of a laser inter-satellite communication ranging link, and the method comprises the steps: obtaining the sampling data of a photoelectric detection signal of the laser inter-satellite communication ranging link in real time; performing interpolation recovery on the sampling data according to the current loop interpolation parameter; performing clock phase error phase discrimination on the interpolation recovery data, wherein phase discrimination gain coefficient correction needs to be performed through real-time amplitude monitoring on the interpolation recovery data; filtering a clock phase error phase discrimination result; updating a loop interpolation parameter and a super-resolution code element phase accurate distance measurement result by using a filtered clock phase error phase discrimination result; and extracting a super-resolution code element phase accurate distance measurement result. According to the method, the phase discrimination gain coefficient is corrected in real time by monitoring the amplitude change in real time, so that the distance measurement precision does not change along with the amplitude of the received optical signal, and the distance measurement precision under the working condition of dynamic amplitude change of the laser inter-satellite link is improved.

The invention provides a jitter tolerance measuring device and a jitter tolerance measuring method, which can automatically calculate the confidence level of an output signal of a measured object when the jitter tolerance is obtained, and can quickly and easily confirm the confidence level of the jitter tolerance after a jitter tolerance test. A jitter tolerance measurement device is provided with: an error code measurement unit that measures, within a predetermined measurement time, an error measurement value of an output signal of a DUT that receives a code pattern signal synchronized with a jitter clock phase-modulated by a jitter modulation signal; a jitter tolerance measuring unit that changes the jitter amplitude and jitter frequency of the jitter modulation signal and estimates, for each jitter frequency, the maximum jitter amplitude at which the error measurement value measured by the error code measuring unit is equal to or less than a prescribed allowable value as the jitter tolerance of the DUT; a confidence level calculation unit that calculates a confidence level relating to an allowable value of the error rate of the output signal of the DUT; and a display unit that displays a result display screen showing the shake tolerance and the confidence level.

The invention discloses a signal data receiving terminal for data recovery without a reference clock and a receiving method of the signal data receiving terminal, and relates to the technical field of clock data recovery. And the inner side of the fixing frame is fixedly connected with a terminal body which is used for receiving external data and is embedded into the clock body to recover the precision of the clock body. According to the signal data receiving terminal for data recovery without the reference clock and the receiving method of the signal data receiving terminal, external data are received through the terminal body, the terminal body exchanges timestamps, counteracts transmission delay and calculates clock skew through two-way communication, and the local clock frequency is adjusted through feedback control of the received signals, so that the data recovery efficiency is improved. When the terminal body starts to receive external data, the deformation metal sheet can pull the receiving antenna to move towards the outer side, the receiving antenna extends out of the interior of the terminal body to better receive the external data, and subsequent data recovery of a non-reference clock is facilitated.

The invention relates to the technical field of voice communication, and discloses a clock-buffer bidirectional linkage adjustment method and device for a voice gateway, and the method comprises the steps: obtaining a clock frequency error, and carrying out the compensation of a jitter buffer initial depth according to the clock frequency error, and obtaining a jitter buffer target depth; the jitter cache initial depth is a dynamic initial depth at the current moment determined based on a prediction model; based on the original depth of the jitter cache and the target depth of the jitter cache, determining a depth change rate corresponding to the jitter cache; and determining a dynamic gain of a clock phase-locked loop based on the depth change rate, and updating a clock signal according to the dynamic gain, thereby effectively improving the accuracy and reliability of voice playing by the voice gateway through clock-buffer bidirectional linkage adjustment.

The invention discloses an aperture error and non-linear cooperative calibration circuit and method for a pipeline ADC, and relates to the technical field of mixed signal integrated circuits, the circuit comprises a pipeline ADC basic circuit and a calibration circuit integrated with the pipeline ADC basic circuit, and the calibration circuit comprises an aperture error calibration module and a non-linear error calibration module. And the aperture error calibration module dynamically adjusts the sampling clock phase of the first-stage Sub-ADC by counting a post-stage output code value histogram and combining an SAR logic feedback mechanism so as to compensate the sampling moment deviation between the first-stage Sub-ADC and the MDAC. The nonlinear error calibration module extracts errors by injecting pseudo-random jitter and utilizing double-threshold window crossing statistics, and after EWMA smooth filtering is carried out, a polynomial compensation coefficient is updated in a self-adaptive mode through an LMS algorithm, and harmonic distortion is restrained. According to the method, the linearity under high-speed and high-bandwidth application is remarkably improved, and the method has good robustness for PVT fluctuation.

This invention provides a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. A sensor array is deployed along the critical signal path to simultaneously acquire high-frequency crosstalk spectrum and timing eye diagram parameters, generating a crosstalk intensity matrix (CIM) and a timing margin heatmap (TMM) to achieve multi-dimensional quantitative characterization of signal integrity. Based on the CIM, the main interference source is located, and the impedance of the affected line is dynamically adjusted and a reverse compensation current is injected to cancel high-frequency crosstalk at its source. The margin attenuation is predicted using a pre-trained model, and the clock phase of the affected line is fine-tuned to compensate for timing deviations. The optimized efficiency index per unit energy consumption after compensation is calculated, triggering a dynamic update or re-compensation mechanism for the strategy library. This invention achieves dynamic synergy between crosstalk suppression and timing optimization based on a closed-loop architecture composed of monitoring data, neural network prediction, dual-loop compensation, energy efficiency verification, and strategy learning.

The invention relates to an exception handling circuit and exception handling method for clock data recovery. According to the method and the device, the data sender can be supported to implement data scrambling with direct current balance as a target on the target data to be transmitted, so that the data receiver can receive scrambled data with a direct current balance characteristic through a physical channel. On the basis, periodic samples of sampled data obtained by sampling the scrambled data by a data receiver can be obtained, and when it is judged that a sampling clock phase of the scrambled data is locked at a false eye position in an eye pattern of the scrambled data according to periodic direct-current unbalance deviation of a plurality of continuous periodic samples, the scrambled data is locked at the false eye position in the eye pattern of the scrambled data. According to the method, the phase of the sampling clock can be separated from the false eye position by implementing unlocking phase adjustment on the phase of the sampling clock, so that the dynamic calibration of the phase of the sampling clock can be recovered in time, and the failure risk of clock data recovery can be reduced.

The application relates to a low-power four-phase distributed digital low-voltage difference linear voltage stabilizer, belonging to the technical field of electronic circuits, comprising a four-phase clock circuit and four digital LDO subunits connected to the same load network; the four-phase clock circuit is used for converting an input clock signal into clock signals with the same frequency and different phases through a clock phase adjustment channel composed of four frequency dividers and three inverters, and outputting the clock signals to the connected four digital LDO subunits for time sharing and phase control; the digital LDO subunit is used for comparing the size of an output voltage of the subunit with two reference voltages through an internal voltage judgment circuit composed of double comparators and a fast trigger loop composed of a controller, and stably controlling the output voltage between the two reference voltages according to the voltage comparison. The application effectively optimizes the transient response speed and power consumption of the digital LDO.

To compensate for the nonlinearity of a phase interpolation (PI) circuit, the interpolation clocks of two PI circuits receiving different interpolation codes may be summed. However, even if the nonlinearity of the interpolated clocks has opposite polarities, they may have different magnitudes, causing some nonlinearity. A weighted summing PI that sums the interpolated clocks of two PI circuits includes a weighted summing circuit that uses weight signals to generate a weighted summing interpolated clock having an interpolated phase between the phases of the interpolated clocks based on the weight signals. Consequently, the phase of the weighted summing interpolated clock may be more influenced by the phase of one of the interpolated clocks from the two PI circuits than by the phase of the other. To reduce nonlinearity in the weighted summing PI, a weight correction circuit may be included to select a balanced weight signal.

The invention relates to a satellite clock frequency difference and phase difference determination method, system and device, a medium and a product, and the method comprises the steps: carrying out the bidirectional comparison clock difference measurement of adjacent satellites when a time-frequency reference reported by an operation control center is received, and obtaining the initial frequency difference and initial phase difference of a satellite clock; performing volume Kalman filtering prediction on the initial phase difference according to the current time frequency information and a clock phase difference value at a previous moment of the current moment to obtain a phase difference prediction value; according to a preset period, taking a frequency difference average value measured by the neighbor satellites of the adjacent satellites as a target frequency difference of a satellite clock, and taking a phase difference average value measured by the adjacent satellites as an updated initial phase difference; and processing the phase difference predicted value, the target frequency difference and the updated initial phase difference by adopting a volume Kalman filtering strategy to obtain the target phase difference of the satellite clock, so that an accurate adjustment basis is provided for calibration of the satellite clock, and the clock synchronization precision is improved.

A method, apparatus, and system are disclosed for a host to process and transmit one or more streams having a data signal and bit clock signal over a serial channel to a receiver by detecting a count and timing location for one or more clock edge transitions in the bit clock signal with respect to a pre-negotiated duration spanning over one or multiple aggregated frames which are transmitted over the serial channel, and then coding the count and timing location with one or more corresponding data values from the data signal into a multi-bit clock phase data codeword which is inserted into one of the aggregated frame that is transmitted over the serial channel to the receiver.

The invention discloses an Ethernet clock phase synchronization method and a related device, and the method comprises the steps: obtaining a sending timestamp and a receiving timestamp through a time synchronization protocol, and calculating the time offset between a master clock and a slave clock according to the sending timestamp and the receiving timestamp; a delay configuration signal including the transmit and receive path delay control value is then generated. Control values are respectively input to programmable delay arrays on a sending path and a receiving path, and the number of unit delay units through which clock signals pass is dynamically controlled, so that the phases of a sending clock and a receiving sampling clock are accurately adjusted. According to the method, a circuit structure with unit delay time is utilized, refined dynamic compensation of the clock phase is achieved, and Ethernet clock synchronization precision and system data transmission reliability are effectively improved.

The application relates to the technical field of chip signals, and discloses a clock phase adjusting method, an Ethernet data transmission method and related equipment. The clock phase adjusting method comprises the following steps: obtaining the link state and the working transmission rate of a counterpart chip (a PHY chip or a MAC chip), then setting an initial value of a counter and a count rollover condition, and when the value of the counter reaches the count rollover condition, generating a first clock signal and a second clock signal with a phase deviation, which are used for the output of a data signal and a clock signal of the PHY chip or the MAC chip. The application enables the RGMII interface to adapt to various MAC chip and PHY chip interconnection scenes, improves the compatibility of the network card chip, and solves the problem of RGMII interface data sampling errors.

The application provides an HDLC receiver with adaptive adjustment of synchronous clock phase function and an operation method, belongs to the technical field of data communication, and solves the problem that a traditional HDLC receiver cannot adaptively adjust clock phase to adapt to different working environments and signal changes, wherein the HDLC receiver comprises a synchronous clock input module, a serial data input module, a clock phase shifter module, a phase difference calculator module, a serial-parallel converter module, a zero removal controller module, a '7E' detector module, a received data coding module, an address judgment module, a CRC check module, a function setting register module, a received buffer area module and a state register module; the modules in the HDLC receiver designed by the application are independent of each other, but are connected with each other through clock and data signals, so that the flexibility and expansibility of the system are ensured, and in different application scenarios, the parameters of different modules can be adjusted according to needs to adapt to different communication environments.

A system and method for performing digital calibration of non-linearity in a circuit is presented. The circuit includes a phase detector, a statistics gathering device, and a feedback device. The phase detector provides information regarding a relationship between a clock from the programmable clock phase circuit and a reference signal. The statistics gathering device is coupled to the phase detector. The statistics gathering device receives an output of the phase detector to measure linearity of the programmable clock phase circuit. The feedback device is coupled to the statistics gathering device. The feedback device controls a delay and adjusts a phase of the clock based on measured values received from the statistics gathering device.

The invention discloses a phase convergence method, circuit and chip for XGSPON uplink burst data transmission, and the method comprises the steps: obtaining first sampling data generated by a lead code of double oversampling burst data, recording even-number-bit data as a first even-number-bit sequence, and recording odd-number-bit data as a first odd-number-bit sequence; lagging the sampling clock phase of the burst data by a first preset angle; acquiring second sampling data generated by oversampling the preamble by two times of a sampling clock phase lagging behind the first preset angle, recording the even-number bit data as a second even-number bit sequence, and recording the odd-number bit data as a second odd-number bit sequence; performing preset logic processing on the first even bit sequence, the first odd bit sequence, the second even bit sequence and the second odd bit sequence, and determining a hopping edge position of the lead code according to a preset logic processing result; and adjusting the sampling clock phase of the burst data according to the jump edge position of the lead code. According to the invention, the time window of phase convergence is shortened, and the effective bandwidth of XGSPON uplink communication is improved.

The application relates to the technical field of laser intersatellite link communication ranging, and provides an optimization method and device for improving the ranging precision of a laser intersatellite communication ranging link, which comprises the following steps: acquiring sampling data of a photoelectric detection signal of the laser intersatellite communication ranging link in real time; performing interpolation recovery on the sampling data according to current loop interpolation parameters; performing clock phase error phase discrimination on the interpolation recovery data, wherein the phase discrimination gain coefficient needs to be corrected through real-time amplitude monitoring of the interpolation recovery data; filtering the clock phase error phase discrimination result; updating the loop interpolation parameters and the super-resolution code phase accurate ranging result by using the filtered clock phase error phase discrimination result; and extracting the super-resolution code phase accurate ranging result. The application can correct the phase discrimination gain coefficient in real time through real-time monitoring of the amplitude change, so that the ranging precision does not change with the amplitude change of the received light signal, and the ranging precision under the dynamic amplitude change working condition of the laser intersatellite link is improved.

Clock phase tuning method including supplying a current (lout) to a capacitor (CL) when first and second clock signals (CK1, CK2) are at a first logic state to generate an voltage (Vout) across the capacitor during a first interval; supplying or drawing a current (lout) to or from the capacitor based on an enable signal when the first and second clock signals are at first and second logic states to generate the voltage across the capacitor during a second interval; drawing a current from the capacitor when the first and second clock signals are at the second logic state to generate the voltage during a third interval; drawing or supplying current from or to the capacitor based on the enable signal when the first and second clock signals are at second and first second logic states to generate the voltage across the capacitor during a fourth interval; and generating a clock signal (Ckout) based on the voltage.

The invention provides a low-jitter pulse signal generation circuit, which relates to the technical field of synchronous control signals and comprises an FPGA (Field Programmable Gate Array) chip U1 and a low-jitter clock phase-locked loop chip U2, the low-jitter clock phase-locked loop chip U2 is connected with the FPGA chip U1, and the low-jitter clock phase-locked loop chip U2 is connected with the crystal oscillator U5 or the external reference clock input interface U6; the low-jitter clock phase-locked loop chip U2 is connected to the FPGA chip U1; the clock fan-out chip U3 is connected to the low-jitter clock phase-locked loop chip U2; the high-speed driving chip U4 is connected to the clock fan-out chip U3, the high-speed driving chip U4 is connected to the FPGA chip U1, and the high-speed driving chip U4 is connected to the digital pulse signal output interface U7. The circuit has the advantages of extremely low output signal jitter, excellent time sequence margin and reliability, high flexibility and expandability, capability of supporting internal and external clock reference and wide application scene.

The invention discloses a method, equipment and a system. A method for a host to process one or more streams having a data signal and a bit clock signal and transmit the one or more streams to a receiver over a serial channel. Detecting a count and timing position of one or more clock edge transitions in the bit clock signal relative to a pre-negotiation duration across one or more aggregated frames transmitted over the serial channel, the count and timing positions are then encoded with one or more corresponding data values from the data signal into a multi-bit clock phase data codeword inserted into one of the aggregated frames transmitted over the serial channel to the receiver.

Cells in a superconducting electronics (SCE) netlist may be levelized. The SCE may use multiple clock phases, and each level in the levelized SCE netlist may be associated with a clock phase. Buffers may be inserted in the SCE netlist so that output ports of the SCE netlist are associated with the same clock phase. A floorplan may be created for the SCE netlist. A placed SCE netlist may be generated based on the floorplan, where cells in each row of the placed SCE netlist may be clocked using the same clock phase.

The application relates to a re-timer, comprising an analog signal front-end processing module, a clock data recovery module, a clock trigger driving module, and further comprising: a phase control decision device, which is used for fixed-point sampling and decision of the processed analog signal based on an optimal sampling clock phase to obtain a digital signal, and scoring the reliability of each bit of the digital signal; a forward error correction decoding module, which is used for error correction and repair of the digital signal according to the score of the reliability of each bit of the digital signal to obtain a repaired digital signal; and the repaired digital signal is sent into the clock trigger driving module to be converted into an analog differential signal. The application integrates the forward error correction function in the re-timer, corrects the error code of the received code stream, avoids the uniform transmission of the error code to the receiving end, can efficiently process the error code, reduces the link delay, prolongs the transmission distance, and further improves the stability and reliability of the system.