334 results about "Clock phase" patented technology

The invention relates to the technical field of high-speed digital interfaces, and discloses a JESD204B multi-device deterministic delay synchronization system and method based on dynamic clock phase compensation, and the system comprises a main node which generates and dynamically distributes clock signals, and constructs a dynamic clock tree structure; the slave equipment is used for realizing cascade error elimination through a distributed compensation mechanism; the dynamic phase compensation engine adopts a hybrid phase detection framework and is combined with a digital-to-time converter (TDC) and an analog phase-locked loop (PLL); and the environment parameter compensation module is used for collecting temperature, voltage and operation time in real time, and calculating phase compensation quantity through a formula that delta phi = alpha * (T-T0) + beta * (V-V0) + gamma * delta t. On the aspect of synchronization precision, the phase error of a single device can be smaller than or equal to + / -200ps, the strict scene requirement is effectively met, the environment adaptability is high, the defects of traditional fixed compensation can be overcome, cascade error accumulation can be efficiently restrained through distributed compensation of slave devices, and on the aspect of real-time performance, an online calibration module can conduct real-time calibration without interrupting services.

The invention relates to a time synchronization maintaining method assisted by temperature sensing, and belongs to the technical field of time synchronization. The method comprises the following steps: for a network communication scene in which synchronous information interaction cannot be carried out between equipment due to a main clock fault or communication link interruption, considering the characteristic that the output frequency of an equipment clock crystal oscillator presents nonlinear dynamic time varying due to environment temperature change; constructing a time sequence prediction model based on the TimeNet neural network and suitable for the non-external connection; training the model by using clock parameter data and temperature information which are historically recorded; using the trained model to take the environment temperature information as the input of the model, and predicting the clock frequency offset of the slave node; and the clock phase offset of the slave node is calculated by using the predicted clock frequency offset and a frequency offset autoregressive state transition equation, and the slave node corrects a local clock and realizes clock self-holding with the master node by using the clock frequency offset and a clock phase offset value.

The invention relates to the technical field of microcontrollers, and provides an MCU information protection method and device, electronic equipment and a readable storage medium, and the method comprises the steps: checking a storage access request according to an access control list; wherein the access control list comprises an authorized storage area and an authorized operation type corresponding to the authorized storage area; the storage access request is used for accessing a target storage area of the MCU; according to the debugging secret key, an interface debugging request is checked, and the interface debugging request is used for debugging a target debugging interface of the MCU; identifying a target code instruction of the MCU, and performing pre-execution verification and dynamic monitoring on the target code instruction; adjusting the clock frequency and the clock phase of the MCU according to the load change information and the power consumption change information of the MCU; and implementing encryption measures on the target data transmission channel of the MCU by using the encryption algorithm. According to the technical scheme provided by one or more embodiments of the invention, the data security and the anti-attack capability of the MCU can be improved.

The invention provides a novel clock control method and system based on FPGA, and relates to the technical field of signal processing. The system provided by the invention comprises: a VCXO voltage-controlled crystal oscillator, a digital-to-analog converter, a PLL phase-locked loop module, a DDMTD measurement module and an adaptive clock control module. The phase-locked loop is implemented, a phase detection algorithm and a clock control algorithm are executed based on a single FPGA chip, and the hardware design complexity is low. The invention uses a digital dual-mixing time difference method (DDMTD) to measure and obtain a clock phase detection result, and cooperates with a dynamic PID clock control algorithm to quickly adjust the local clock frequency, so as to realize the fast tracking and locking of the frequency and phase between the local clock and the clock source. The dynamic PID clock control algorithm of the invention dynamically adjusts the parameter P of the PID algorithm in real time according to the state, the clock frequency deviation and the clock phase difference, so that the algorithm has the advantages of stronger locking ability, shorter convergence time and faster response.

The invention discloses an integrated circuit, a cross-clock domain data transmission method, electronic equipment and a storage medium. The integrated circuit comprises a first clock domain and a second clock domain, the first clock domain comprises a first pointer control module, the second clock domain comprises a second pointer control module, the first pointer control module comprises a first synchronous pointer control module, and the second pointer control module comprises a second synchronous pointer control module. The first synchronous pointer control module is configured to respond to the fact that the frequency of the first clock signal is larger than the frequency of the second clock signal, and determine the phase relation between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal and the first clock phase of the first clock domain, determining a first pointer control signal based on the phase relation; and in response to the fact that the frequency of the first clock signal is smaller than that of the second clock signal, determining that the first pointer control signal is a first value, so that the first read pointer and the first write pointer increase the first value in each clock period of the first clock signal.

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

The invention relates to a time synchronization parameter tracking method based on unknown Kalman filtering, which belongs to the technical field of time synchronization, and comprises the following steps: S1, modeling the output frequency of a clock crystal oscillator and the change rule of the temperature of the environment where the clock crystal oscillator is located into a quadratic function for a network communication scene with dynamic change of the environment temperature, introducing the temperature influence factor as an unknown quantity into a clock parameter tracking state equation; s2, establishing a clock observation equation by using a precise time synchronization protocol bidirectional information interaction process, and constructing a clock phase offset and clock frequency offset combined tracking state space model under the dynamic change of the environment temperature in combination with a clock state equation; and S3, by using unknown quantity Kalman filtering and taking minimum variance unbiased estimation as a criterion, jointly tracking a clock frequency offset value and a clock phase offset value for the established clock state space model.

The embodiment of the invention provides a clock phase demodulation method and a molecular clock, and the method comprises the steps: determining a demodulation phase initial value of an Nth harmonic based on an Nth harmonic signal outputted by the clock; wherein the N is a positive integer and is an odd number; determining a first phase change value of the Mth harmonic signal along with time based on the Mth harmonic signal output by the clock; determining a second phase change value, changing along with time, of the L-th harmonic signal based on the L-th harmonic signal output by the clock; wherein M and L are positive integers and are even numbers; calculating a target demodulation phase based on the demodulation phase initial value, the first phase change value and the second phase change value; wherein the target demodulation phase is a demodulation phase used under the condition that frequency locking is carried out by adopting Nth harmonic waves. Through the method, the calculation amount of phase demodulation of the clock can be reduced.

Hub node of a passive optical network, wherein the hub node includes a DSP (Digital Signal Processing) chain configured to: Receiving a signal burst from a leaf node in the passive optical network, wherein the signal burst comprises a frame including a payload and a frame header, the frame header comprising a clock and gain control section, a frame detection section and an equalizer section; Retrieving a clock phase of the leaf node from the clock-and-gain control section of the frame header; Estimation of the signal strength of a signal burst from the leaf node in the passive optical network; Compensation for differences in the signal power of the signal burst from the leaf node; Detecting a frame alignment sequence that indicates the arrival of the signal burst; Determination of MIMO (Multiple Input, Multiple Output) polarization filter coefficients from the frame alignment sequence; Aligning the phase between the X-polarization and Y-polarization of the signal burst using the MIMO polarization filter coefficients; and Determine the frequency offset estimate (FOE) of a local oscillator signal.

The invention relates to a precise time synchronization parameter tracking method based on alternating minimization Kalman filtering, and belongs to the technical field of time synchronization. According to the method, timestamp noise is introduced into a clock synchronization parameter observation equation, and a state-space equation of clock synchronization parameter tracking is established in combination with a double-state clock model; a Kalman filtering method is used for tracking clock phase offset and frequency offset, and in the updating stage of Kalman filtering, an alternative minimization method is introduced for estimating the variance of timestamp noise and unknown observation noise in real time and correcting and updating Kalman gain. And furthermore, the influence of timestamp deviation and observation noise with unknown statistical characteristics on the clock synchronization parameter tracking precision is suppressed, and long-term effective tracking of the clock synchronization parameter is realized. According to the method, the problem that Kalman filtering is easy to diverge under unknown timestamp noise and observation noise is solved, joint tracking of clock phase offset and frequency offset can be realized, and the robustness and stability of clock synchronization are further improved.

Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

The invention discloses an Internet of Things flowmeter data compression sensing transmission optimization method and system, particularly relates to the field of low-power-consumption wireless communication networks, and is used for solving the problem of compressed sensing signal distortion caused by sampling time sequence misalignment in an LPWAN bandwidth limited environment. Constructing a local phase reference by extracting a pipeline vibration fundamental frequency component, and receiving a cloud synchronization reference timestamp alignment signal; fundamental frequency and third harmonic components are separated to calculate arrival time difference, and a phase-locked loop is triggered to dynamically adjust the phase of a sampling clock based on a pipeline material threshold value; after the stability of the zero crossing point time variance is verified, compressed sensing sampling is performed on the flow signal by adopting a phase synchronous clock, and an optimized compressed measurement value is generated and transmitted to the cloud through the LPWAN; through closed-loop cooperation of physical characteristics and a communication clock, complete capture of a signal sparse structure is guaranteed under a low-bandwidth condition, and cloud reconstruction precision is significantly improved.

This disclosure provides a charge pump circuit. The charge pump circuit according to this disclosure includes one or more cascaded boost units and output units having the same structure. Each boost unit has a dual-branch structure with top and bottom symmetry and connected to two sets of four-phase clock signals with opposite clock phases. By adjusting the phase relationship of the four-phase clocks, the rise time of the gate voltage of the transfer transistor can be delayed by advancing the falling edge of the driving clock of the secondary capacitor and delaying its rising edge. This ensures that the transfer transistor is in the off state at the moment of high-low phase switching, thereby avoiding the problem of reduced charge transfer efficiency caused by reverse charge flow between the input and output nodes of the boost unit.

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

The invention relates to a reference voltage optimization method, circuit and device, and the method comprises the steps: carrying out the sampling of data transmitted on at least one data line through changing the phase of a sampling clock, and obtaining a sampling clock phase interval under the condition that the sampling data on the at least one data line are all correct; obtaining an optimized sampling clock phase according to the sampling clock phase interval; sampling data transmitted on each data line in the at least one data line by optimizing a sampling clock phase and changing a sampling voltage to obtain an effective reference voltage interval of each data line; and obtaining an optimized reference voltage of each data line according to the effective reference voltage interval of each data line. According to the invention, the identification accuracy of the signal receiving end on the received signal can be improved, and the anti-interference capability of the signal receiving end on receiving the signal can be improved.

In described examples, a frequency modulated continuous wave (FMCW) radar includes a reference clock, a phase locked loop (PLL), a pulse generator, a counter, a chirp ramp control circuit, and a synchronization state machine. The reference clock generates a reference clock signal. The PLL generates a feedback clock signal in response to the reference clock signal, and an output signal in response to the feedback clock signal. The pulse generator outputs a chirp start pulse in response to the reference clock signal. The counter increments a count in response to the feedback clock signal. The synchronization state machine provides a chirp ramp signal to a chirp ramp control circuit in response to the reference clock signal, the feedback clock signal, the chirp start pulse, and the count. The chirp ramp control circuit causes the PLL to ramp a frequency of the output signal in response to the chirp ramp signal.

The invention relates to a cross-chip clock synchronization system, chips and electronic equipment. The clock synchronization system comprises a first clock adjustment link, a second clock adjustment link and a clock phase difference detection module, the first clock adjustment link is configured to adjust the phase delay of an input clock signal and generate a first clock signal based on the adjusted input clock signal; the first clock adjusting link is arranged in the two chips in a crossing manner, and the first clock adjusting link comprises a first cross-chip transmission circuit; the second clock adjustment link is configured to adjust the phase delay of the input clock signal and generate a second clock signal based on the adjusted input clock signal; the second clock adjusting link comprises a delay copy circuit, and the transmission delay of the first cross-chip transmission circuit is consistent with the transmission delay of the delay copy circuit; the clock phase difference detection circuit is configured to detect a phase difference between the first clock signal and the second clock signal. According to the invention, clock skew across chips can be reduced.

The invention discloses a power grid time frequency change trend prediction method and system based on intelligent electric meter data fusion, and the method comprises the steps: measuring the network transmission delay and time deviation between a master clock and a slave clock of a power grid, obtaining an initial time frequency deviation sequence, carrying out the error calibration, carrying out the data fusion after time domain alignment, and carrying out the prediction of the time frequency change trend. Generating a fusion time sequence; performing recursive estimation on the fusion time sequence, outputting an optimal time frequency deviation sequence, and performing synchronous estimation to obtain a clock phase error, a frequency error and frequency drift as state characteristic quantities; and training a preset machine learning prediction model by taking the optimal time frequency deviation sequence as a supervision signal and taking the state characteristic quantity of the corresponding moment as input, and obtaining a prediction result of the power grid time frequency change trend in the future period based on the trained time frequency change trend prediction model. According to the method, the power grid time synchronization precision and prediction capability are remarkably improved, and reliable technical guarantee is provided for stable operation of a power system.

An integrated circuit, a data transmission method across clock domains, an electronic device, and a storage medium. The integrated circuit includes a first clock domain and a second clock domain. The first clock domain includes a first pointer control module, and the second clock domain includes a second pointer control module. The first pointer control module includes a first synchronous pointer control module, and the first synchronous pointer control module is configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine a first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal as a first value, so that the first read pointer and the first write pointer increase by the first value in each clock period of the first clock signal.

The invention discloses a filter circuit, a clock data recovery method, a circuit and a receiver, and belongs to the technical field of signal processing. The filter circuit comprises: a voting module configured to vote according to at least two groups of input data to obtain a target voting result, and send the target voting result to a selection module, each group of input data comprising a clock phase and data, and the target voting result indicating a relative relationship between the clock phase and the data; the selection module is configured to determine a clock adjustment parameter according to the target voting result, obtain a target adjustment coefficient and send the clock adjustment parameter and the target adjustment coefficient to the processing module; the processing module is configured to obtain recovery parameters according to the clock adjustment parameters and the target adjustment coefficient, and the recovery parameters are used for recovering the clock and the data. The obtained recovery parameters are more accurate, noise is effectively suppressed, and the accuracy of recovering clocks and data based on the recovery parameters is improved.

The present invention relates to the technical field of data communication, and relates to a precise time synchronization clock parameter estimation method based on optimal invariant estimation. In the present invention, in a communication scene where unknown random time delay distribution information is present, on the basis of a precise time protocol, timestamp interaction is achieved by means of bidirectional data packet transfer between a master node and a slave node, and a clock relation model between the master node and the slave node is established; considering that a plurality of intermediate devices exist in the data packet interaction process, resulting that random time delay distribution information cannot be accurately obtained, a Gaussian mixture model is used to model a random time delay distribution, a competitive expectation maximization algorithm is used to learn mixture model parameters; and finally, on the basis of the parameters obtained by learning, an optimal invariant estimation method is used to estimate a clock frequency offset and a clock phase offset simultaneously, so as to realize time synchronization between the master node and the slave node. The present invention improves the accuracy of clock frequency offset estimation and clock phase offset estimation, is suitable for a communication scene where unknown random time delay distribution information is present, and enhances the robustness of the synchronization algorithm to a communication time delay.

The invention discloses a multi-channel multi-phase clock array based on an MEMS, and belongs to the field of radio frequency integration. Comprising a clock source circuit for generating reference signals of a multi-path multi-phase clock; the multi-phase clock generation circuit takes the reference signal output by the clock source circuit as an input signal, N paths of clocks are generated by using a delay phase-locked loop structure, and the phase difference of each path of clock is 2pi / N; according to the multi-phase clock calibration circuit, the multi-channel clocks of the multi-phase clock generation circuit are used as input signals of a controllable delay line array in the multi-phase clock calibration circuit, and after the multi-channel clocks output by the controllable delay line array are used for driving the multi-channel ADCs to sample the same sinusoidal signal, the same sinusoidal signal is output. A three-point IpDFT phase estimation algorithm is used for estimating the sampled sinusoidal signals to obtain the phase difference of multiple paths of clocks, and the delay of each path of the controllable delay line array is controlled according to the phase difference so as to calibrate the clock phase. Compared with a traditional multi-path and multi-phase clock structure, the multi-path and multi-phase clock structure has higher integration level, and the three-point IpDFT phase estimation algorithm is adopted, so that very high phase precision is achieved.

The invention provides an all-digital dual-mixing phase discrimination filtering system and a metastable state median filtering method, and relates to the technical field of signal processing. The system provided by the invention is completely realized by an FPGA (Field Programmable Gate Array), and frequency mixing processing is carried out on a tested clock signal by adopting a multi-stage frequency mixing link, so that the influence of a metastable state on a DDMTD (Digital Division Multiplexing Time Division Multiplexing) frequency mixing result is reduced; in addition, a DDMTD burr filtering module arranged in the multi-path filtering module is used for simultaneously carrying out metastable state filtering on multi-path DDMTD frequency mixing results of the same clock signal, and the edge of each path of DDMTD frequency mixing result is accurately recovered; in addition, DDMTD clock phase difference measurement is carried out on each path of DDMTD frequency mixing result edge after filtering recovery through a clock phase difference measurement module; and finally, the mean value filtering module is used for finishing mean value processing on the multi-channel DDMTD clock phase difference measurement result, so that the measurement precision of the digital double-mixing phase discrimination filtering system is further improved.

Systems and methods are disclosed for clock phase calibration between source logic and a coupled serial data link transmitter, enabling low-latency synchronization into the transmitter. In calibration mode, a phase relationship is monitored between a first clock, driving the source logic, and a second clock, tightly synchronized with a serial clock of the data link. The first clock is adjusted to a first phase at which the first and second clocks are aligned. The first clock phase is set for operation mode based on the first phase. Monitoring uses a D-type flip-flop as a phase detector. Adjustment is in steps of half the serial clock period. Variations are disclosed.

The present invention relates to the field of time synchronization, and relates to a precise clock synchronization parameter tracking method based on an augmented Kalman neural network. In the method, for a multi-hop network scenario where an ambient temperature changes and a link transmission delay is asymmetric, taking into account the impact of an accumulated asymmetric link transmission delay in a multi-hop network on clock synchronization accuracy, a multi-hop network clock observation equation containing an accumulated asymmetric link delay is derived, and on the basis of a quadratic polynomial model of a temperature and a clock frequency offset, a recursive state equation of the clock frequency offset and a temperature change is established; the evolution processes of an accumulated asymmetric delay and an unknown temperature coefficient are modeled as a first-order linear difference equation, and the accumulated asymmetric delay and the unknown temperature coefficient are augmented to a clock parameter tracking state space model; and an augmented Kalman neural network algorithm is used to realize joint tracking of a clock phase offset and a clock frequency offset of a slave node. This method employs a hybrid data-model-driven approach to perform joint tracking of the clock phase offset and frequency offset, thereby improving accuracy and robustness of clock parameter tracking.

Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.

The invention relates to the technical field of MEMS, and discloses an MEMS gyroscope closed-loop driving loop, a phase-locked loop circuit outputs a synchronous clock signal, and a clock generation circuit is used for performing gate logic operation, frequency division and layered delay addition on the synchronous clock signal to generate multiple groups of collaborative non-overlapping clock signals; a band-pass delta-sigma modulator, a CV conversion circuit and a digital signal processing module are controlled; meanwhile, through phase locking of a synchronous clock phase, a main sampling switch signal is synchronized with a falling edge of the synchronous clock phase, and the sampling phase is ensured to be 0 degree, so that a digital code stream signal of which the sampling phase is kept at 0 degree is output, and the sampling phase of the band-pass delta-sigma modulator is strictly synchronized with the mechanical vibration phase of the MEMS gyroscope; and phase deviation in the driving loop is eliminated. The digital signal processing module adjusts the amplitude and the phase of a feedback signal of the whole driving loop, so that the stability and the adjustability of the driving loop are improved under the condition that the MEMS gyroscope is driven under a proper condition.

The invention discloses a differential bus transmission verification system based on a digital ink-jet printer and a printer, and relates to the technical field of printing equipment data transmission, the system comprises a first main control module, a second main control module, 14 pairs of differential signal lines, a downlink channel and an uplink channel, a dynamic verification module adjusts the bit width of a verification code according to the type of a data packet, and the downlink adopts an enhanced CRC algorithm. An odd-even, accumulation and combination algorithm is used for uplink, the algorithm can be switched and retransmission is carried out when continuous error data packets are encountered; a time sequence control module is used for measuring transmission delay, adjusting a clock phase and guaranteeing transmission accuracy; a self-defined bus protocol is divided into three layers; a data packet structure and printing instruction analysis are stipulated; the system has an exception handling mechanism, speed reduction, redundant channel cutting, error recording and diagnosis report generation are performed when verification fails and exceeds a threshold value, a differential signal line is of a twisted-pair structure, signal stability is ensured, and the system is used for connecting a printer with a printing head drive and a motion platform and transmitting a control instruction to ensure reliable and stable data transmission.

The invention relates to a clock phase detection circuit and method, a delay phase-locked loop, a chip and electronic equipment, and the circuit comprises a frequency division module which is used for carrying out the frequency division processing of a reference clock signal selected from a plurality of input clock signals with the same frequency and different phases, and generating a frequency division clock signal; the clock driving module is used for grouping a plurality of input clock signals with the same frequency and different phases to generate at least two groups of input clock signals; the detection module is used for generating a detection signal according to a time interval between the reference clock signal and the feedback clock signal based on the frequency division clock signal and the at least two groups of input clock signals; wherein the feedback clock signal is an input clock signal of the previous phase of the reference clock signal. According to the invention, on the premise of not introducing an additional clock source, the detection of the clock phase can be quickly realized by using a plurality of input clock signals with the same frequency and different phases.

The invention discloses an equipment debugging method and device, equipment, an equipment system and a medium, and relates to the technical field of communication, and the method comprises the steps: obtaining network card information of target equipment after the target equipment is powered on, and recognizing a target network card supporting a shared network port from all network cards of the target equipment based on the network card information; if the target network card is identified for the first time, controlling a preset control device in the target equipment to be switched to a target interface channel so as to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of a sideband interface of the network controller; and accessing the data transceiving signal appearing in the target interface channel to a preset control device so that the preset control device performs spectral analysis on the data transceiving signal, and debugging a clock phase offset meeting a preset function requirement based on a spectral analysis result. According to the scheme, the clock phase offset meeting the preset requirement is debugged, and accurate time sequence matching of the clock signal and the data signal is achieved.