41 results about "Clock phase" patented technology

This invention provides a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. A sensor array is deployed along the critical signal path to simultaneously acquire high-frequency crosstalk spectrum and timing eye diagram parameters, generating a crosstalk intensity matrix (CIM) and a timing margin heatmap (TMM) to achieve multi-dimensional quantitative characterization of signal integrity. Based on the CIM, the main interference source is located, and the impedance of the affected line is dynamically adjusted and a reverse compensation current is injected to cancel high-frequency crosstalk at its source. The margin attenuation is predicted using a pre-trained model, and the clock phase of the affected line is fine-tuned to compensate for timing deviations. The optimized efficiency index per unit energy consumption after compensation is calculated, triggering a dynamic update or re-compensation mechanism for the strategy library. This invention achieves dynamic synergy between crosstalk suppression and timing optimization based on a closed-loop architecture composed of monitoring data, neural network prediction, dual-loop compensation, energy efficiency verification, and strategy learning.

To compensate for the nonlinearity of a phase interpolation (PI) circuit, the interpolation clocks of two PI circuits receiving different interpolation codes may be summed. However, even if the nonlinearity of the interpolated clocks has opposite polarities, they may have different magnitudes, causing some nonlinearity. A weighted summing PI that sums the interpolated clocks of two PI circuits includes a weighted summing circuit that uses weight signals to generate a weighted summing interpolated clock having an interpolated phase between the phases of the interpolated clocks based on the weight signals. Consequently, the phase of the weighted summing interpolated clock may be more influenced by the phase of one of the interpolated clocks from the two PI circuits than by the phase of the other. To reduce nonlinearity in the weighted summing PI, a weight correction circuit may be included to select a balanced weight signal.

This invention discloses a control method and system for a distributed motion controller, relating to the field of motor control technology. The method includes: acquiring operational data from the motion controllers of each production line via real-time Ethernet and processing the acquired data; performing fuzzy inference based on the underlying single-axis servo fuzzy controller of the motion controller to obtain position feedforward compensation time and distributed clock phase adjustment; performing fuzzy inference based on the upper-level production line collaborative fuzzy scheduler of the main controller to obtain speed multipliers and global command timestamp offsets; generating motor control commands conforming to the real-time Ethernet protocol; and using a distributed clock synchronization mechanism to synchronously adjust the operating parameters of the servo motors of each production line. By real-time monitoring and scheduling of the motion controllers of multiple production lines, multiple production lines can cooperate with each other, achieving intelligent dynamic adjustment of the production line system, thereby improving the processing efficiency of the production line system.

This application relates to the field of data verification technology, specifically to a data verification method and apparatus for a chip programming system. The method includes: for a multi-channel parallel chip programming system, statistically analyzing the clock cycles of each channel within each time window; determining the clock phase offset of each channel; evaluating the deviation between each channel and a second reference channel in the current clock cycle and the deviation of the clock phase offset, obtaining the timing deviation of each channel; and dynamically determining the verification delay time of each channel using the timing deviation and clock cycle, generating the verification trigger time for each channel for data verification. This balances verification accuracy and overall efficiency.

The application discloses a clock phase difference control-based electro-optic element driving adjusting device, method and equipment. The device comprises a clock phase modulation circuit for generating at least one first clock signal and at least one second clock signal; at least one first clock level conversion driving circuit and at least one second clock level conversion driving circuit, which are respectively used for amplifying and converting the first clock signal into a first driving level and amplifying and converting the second clock signal into a second driving level to form an alternating voltage across the electro-optic element; and the clock phase modulation circuit can adjust the phase difference between the first clock signal and the second clock signal to adjust the brightness of the electro-optic element. The device has the advantages of high efficiency and flexibility in adjusting the electro-optic element and is also helpful to realize the miniaturization of the device.

The application relates to the field of digital signal processing, in particular to a digital signal processing system and method based on a dynamic clock anti-jitter algorithm, which comprises the following steps: collecting historical jitter data of a clock signal in real time through a clock data collection module; generating jitter statistical characteristic parameters by using a Gaussian mixture model dynamic modeling module; realizing sub-nanosecond level real-time phase compensation by means of an extended Kalman filter correction module; dynamically adjusting an I2S master clock phase in cooperation with a software programmable clock generation module; and realizing a prediction-compensation feedback mechanism to complete jitter suppression through a closed-loop control unit. The application achieves the technical effects of significantly reducing clock jitter, improving digital signal processing precision and stability, and especially showing excellent anti-jitter performance in a high-frequency signal processing scene.

The present application relates to an integrated circuit, a cross-clock domain data transmission method, an electronic device, and a storage medium. The integrated circuit comprises a first clock domain and a second clock domain; the first clock domain comprises a first pointer control module; the second clock domain comprises a second pointer control module; the first pointer control module comprises a first synchronization pointer control module; the first synchronization pointer control module is configured to: in response to the frequency of the first clock signal being greater than that of the second clock signal, on the basis of a second clock phase and a second clock period of the second clock domain, the first clock signal and a first clock phase of the first clock domain, determine a phase relationship between the first clock signal and the second clock signal, and determine a first pointer control signal on the basis of the phase relationship; and in response to the frequency of the first clock signal being smaller than that of the second clock signal, determine that the first pointer control signal is a first value, so that a first read pointer and a first write pointer increase by the first value in each clock period of the first clock signal.

The application relates to the technical field of bus communication, and particularly discloses a servo driver bus communication system for multi-motor synchronization, which comprises a reference module, a clock module, a phase conversion module and an adjustment module. The reference module comprises a bus master station for sending a test clock signal with a time stamp, and a slave station for feeding back a signal; the master station calculates the time consumption and screens the slave station with the shortest time consumption as a reference slave station. The clock module acquires the clock difference value of the reference slave station, calculates and issues the calibration compensation amount of each slave station, and adjusts the local clock of the corresponding slave station according to the compensation amount. The phase conversion module collects the motor rotor pulse number of the slave station, converts the pulse number at the reference time into the actual phase based on the encoder resolution, and uploads the actual phase. The adjustment module calculates the deviation by taking the reference phase as the reference, marks the target slave station if the deviation exceeds a threshold value, calculates the correction amount, and issues the adjustment instruction to complete the phase calibration. Through the reference screening, clock calibration, phase conversion and closed-loop adjustment, the multi-motor synchronization error problem is solved, the collaborative precision and stability are improved, and technical support is provided for industrial automation.

The application provides a kind of integrated circuit chip signal transmission correction system and method, related to the technical field of application-specific integrated circuit chip, by determining the clock phase difference between adjacent transmission channels;The monitoring circuit of each receiving end records the pulse string interference intensity from the active transmission channel, and then constructs the pulse string interference matrix of application-specific integrated circuit chip;When it is identified that more than a preset number of transmission channels in adjacent transmission channels occur reverse jump at the same time, pulse edge suppression is carried out on the transmission channel that occurs reverse jump, and the jitter suppression amount of the pulse edge of the reverse jump transmission channel is obtained;Insert reference pulse in the idle clock cycle of signal transmission stage, and detect the waveform distortion degree of reference pulse;According to the jitter suppression amount and the waveform distortion degree, the timing parameters of the pulse edge of the reverse jump transmission channel are timing calibrated.The application can realize the suppression of multi-channel pulse crosstalk in the application-specific integrated circuit chip, so as to improve the integrity of chip signal transmission.

An apparatus, including: a first synchronizer configured to synchronize a frequency divider reset signal with a reference clock signal to generate a reference clock domain reset signal; a set of delay buffers configured to generate a set of delayed staggered reference clock domain reset signals based on the reference clock domain reset signal; a set of second synchronizers configured to synchronize the set of delayed staggered reference clock domain reset signals with a phase lock loop (PLL) clock signal to generate a set of PLL clock domain reset signals; a phase detector configured to generate a signal related to a phase difference between respective clocking edges of the reference clock signal and the PLL clock signal; a phase corrector configured to generate a select signal based on the phase difference signal; and a multiplexer configured to output one of the PLL clock domain reset signals based on the select signal.

The present application relates to a kind of tunnel advanced geological prediction method and system based on three-level synchronization of wireless data transmission, and in the present application, acquisition host computer and acquisition node instrument establish wireless data transmission network;Acquisition host computer broadcasts synchronous clock command, and acquisition node instrument carries out clock frequency synchronization accordingly;Acquisition host computer and acquisition node instrument carry out bidirectional time difference measurement, and acquisition node instrument carries out local clock phase synchronization according to the result of bidirectional time difference measurement;After seismic source triggers, acquisition node instrument collects seismic wave data and returns, and acquisition terminal generates residual offset correction amount according to cross-correlation result and feeds back to acquisition node instrument to modify its local clock again;Repeat cross-correlation correction process, until the time synchronization error of all acquisition node instruments converges to within preset range.The present application realizes high-precision time synchronization in the environment without GPS through the three-level progressive mechanism of frequency synchronization, phase synchronization and mutual close-loop recalibration based on physical signal.

A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1 / n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1 / n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1 / n of the clock period of the switch-off duration.

The application provides a synchronization circuit based on clock phase adjustment, comprising: a clock dividing circuit, which is used for generating a divided clock signal from an input system clock; a phase detection circuit, which is connected with the clock dividing circuit and is used for obtaining a phase offset value according to an input synchronization reference signal and the divided clock signal; a phase adjustment circuit, which is connected with the clock dividing circuit and the phase detection circuit and is used for adjusting the phase of the input divided clock signal according to the phase offset value to obtain a phase-adjusted divided clock signal; and a synchronizer circuit, which is connected with the phase adjustment circuit and is used for obtaining a local synchronization reference signal according to the phase-adjusted divided clock signal and the synchronization reference signal. The application can quickly adjust the clock phase in real time according to the phase relationship between the reference signal and the divided clock, does not lose the sampling edge of the clock, and can be applied to integrated circuits with high sampling accuracy requirements.

This invention belongs to the field of analog integrated circuit technology, specifically relating to an 8-bit ADC circuit with step-by-step multi-bit quantization; it includes: a SIG-DAC capacitor array receiving differential input signals VIP and VIN, connected to a first enable signal module and 5 comparators, used for successive approximation of the main signal; a REF-DAC capacitor array receiving differential input signals VREFP and VREFN, connected to a second enable signal module and 5 comparators, used to generate a threshold voltage; an asynchronous clock module connected to the second enable signal module, a latch array, and 5 comparators; the latch array consists of 17 latch circuits, and is also connected to the first enable signal module, 5 comparators, and 2 decoder modules connected in series; this invention increases the overall performance of the ADC without adding an extra clock phase, increases the ADC's tolerance to comparison errors, requires fewer total clock cycles, and simplifies the asynchronous clock module.

An electronic device includes a phase detection circuit configured to detect a difference between the phases of a reference clock and a feedback clock and a phase-locked signal generation circuit configured to generate a phase-locked signal based on the results of the detection of the difference between the phases of the reference clock and the feedback clock. The phase-locked signal generation circuit is configured to generate the phase-locked signal when the difference between the phases of the reference clock and the feedback clock is equal to or smaller than a first phase difference after the start of an initial operation and configured to stop the generation of the phase-locked signal when the difference between the phases of the reference clock and the feedback clock is equal to or greater than a second phase difference, which is greater than the first phase difference, after outputting the phase-locked signal.

This invention relates to a method and system for achieving phase consistency of local frequency-divided clocks between modules in a large-scale chip. The method includes: local system clocks clk1 and clk2 of modules A and B are clocks of the same origin and frequency, and the local frequency-divided clocks of the two modules have data exchange; within module A, local system clock clk1 is divided to obtain a local frequency-divided clock clk1_div; a clock synchronization pulse indication signal Bus_en, synchronized with the clock period of the local frequency-divided clock clk1_div, is generated and output to module B; the trailing edge of each indication pulse of the clock synchronization pulse indication signal Bus_en is aligned with the leading edge of the frequency-divided clock clk1_div; module B detects the clock synchronization pulse indication signal Bus_en with its local system clock clk2, generates a local frequency division enable Div_en to trigger local system clock clk2 to perform frequency division, and outputs a local frequency-divided clock clk2_div with phase consistent with the local frequency-divided clock clk1_div. This invention solves the timing problem of data exchange between frequency-divided clocks of various Harden IP modules in a large-scale chip.

This invention discloses a high-efficiency multi-mode clock data recovery circuit, comprising: a multi-mode sampling module for sampling differential signals from an equalizer output to generate data signals and edge signals; a deserialization module for reducing the speed of the data signals and edge signals output by the multi-mode sampling module before outputting them to subsequent digital circuits, compensating for the speed difference between analog circuits operating at higher frequencies and digital circuits operating at lower frequencies; a multi-mode phase detection control module for generating a control word for adjusting the output clock phase of a phase interpolation module; a phase interpolation module for adjusting the phase of the PLL output clock to generate the sampling clock for the multi-mode sampling module; a parallel data output module for outputting the final parallel output data of the physical layer; and a CDR mode control module for controlling and selecting the operating mode of the clock data recovery circuit. This invention can dynamically adapt to different rate modes, improve the energy efficiency ratio in low-noise scenarios, and effectively reduce the system's requirements for the PLL.

The present invention relates to the technical field of time synchronization, and relates to a temperature sensing-assisted time synchronization holdover method. The method comprises: for a network communication scenario in which synchronization information cannot be exchanged between devices due to a master clock failure or a communication link interruption, taking into account the nonlinear and dynamically time-varying characteristics of the clock crystal oscillator output frequency of the devices caused by ambient temperature variations, constructing a TimeNet neural network-based time series prediction model applicable to the case of no external connection, and using historical clock parameter data and temperature information to train the model; using the trained model and taking the ambient temperature information as an input of the model to predict a clock frequency offset of a slave node; and on the basis of the predicted clock frequency offset, using a frequency offset autoregressive state transition equation to calculate a clock phase offset of the slave node, and on the basis of the clock frequency offset and the clock phase offset, the slave node correcting a local clock to achieve clock holdover with a master node.

This invention relates to the field of avionics bus testing and modular instrument technology, specifically to an automated functional testing system for avionics buses based on a modular instrument architecture. The system includes a communication acquisition node, a backplane transmission channel with a first-in-first-out buffer, a low-level bus probe, a status acquisition module, a congestion quantization module, a strategy generation module, and an adaptive scheduling module. The status acquisition module acquires memory access channel occupancy, trigger synchronization clock phase jitter parameters, and system interrupt response differences. The congestion quantization module uses weighted summation to obtain the system's micro-congestion entropy index. The strategy generation module generates full-load concurrent injection, local frequency reduction, or backbone communication deterministic protection strategies based on a first risk threshold and a second limit threshold. The adaptive scheduling module uses feedback sampling to adjust control quantities, correcting the time difference between excitation transmission and response reception, and improving timing reliability in high-concurrency closed-loop testing.

The application provides a training system, a chip and a storage medium of a parallel bus link, the system comprising: a data detection module, configured to detect the validity of data signals corresponding to different phase stages in a plurality of preset phase stages of a clock phase, and obtain binary detection results of the data signals corresponding to the different phase stages; a maximum cluster detection module, configured to obtain a plurality of groups of binary sequences based on an initial binary sequence; obtain a target phase adjustment value based on a binary sequence corresponding to a maximum value in a plurality of values corresponding to the plurality of groups of binary sequences; and a clock module, further configured to adjust the clock phase based on the target phase adjustment value, and detect the validity of data signals corresponding to the adjusted clock phase through the data detection module, and when the data signals corresponding to the adjusted clock phase are detected to be valid, training of the parallel bus link is ended. Thus, fine adjustment of the clock phase is realized through the system.

This invention relates to the field of laser communication technology and discloses a high-precision ranging method and system based on spaceborne laser communication. The method includes: when two terminals send communication signals, aligning the falling edge of the last bit of the frame synchronization header of the data frame with the leading edge of the local satellite clock's integer second pulse as a ranging identifier; modulating the baseband signal containing the ranging identifier into an optical signal and transmitting it into free space; receiving the downlink optical signal from the cooperating terminal and demodulating it into a baseband signal; performing multi-level time delay calibration to obtain the time delay parameters of the system's transceiver channel, and using a code synchronization loop in the communication link to recover the symbol clock phase; and calculating the distance and clock difference between the two terminals based on the arrival time of the ranging identifier and the time delay parameters using a bidirectional one-way ranging model. The above method integrates laser communication and ranging, ensuring high ranging accuracy while saving hardware resources, and is suitable for inter-satellite and satellite-to-ground high-precision laser ranging and high-speed data transmission integration scenarios.

This invention discloses a clock data recovery method, system, and apparatus. After the sampling module samples each data point in the data to be sampled based on the clock signal generated by the clock generation module, the phase of the clock signal generated by the clock generation module is adjusted by determining the offset direction of the actual sampling position of each data point in the data to be sampled relative to a preset sampling position. This adjustment continues until the sampling position when the sampling module samples each data point in the data to be sampled based on the clock signal with the adjusted clock phase is the preset sampling position. In this application, adjusting the phase of the clock signal by determining the offset direction of the actual sampling position of the sampled data relative to the preset sampling position ensures that the sampling module samples the data at the preset sampling position of each data point in the data to be sampled, improving the accuracy of data sampling and thus guaranteeing the accuracy of data transmission.

The application relates to the technical field of high-speed interface transmission, and discloses a clock phase adjustment circuit, method and system. The circuit comprises a phase monitoring module configured to detect a phase difference between a source clock signal and a side clock signal and output a phase monitoring signal; a voting module configured to receive the phase monitoring signals output by the plurality of phase monitoring modules and output an adjustment instruction when more than half of the phase monitoring signals are in a consistent state; and a phase adjustment module configured to generate a phase control code according to the adjustment instruction to control phase adjustment of the source clock signal. The application effectively solves the problem of clock phase deviation caused by differences in delay changes of different clock paths in a high-speed interface when voltage or temperature changes, can detect and automatically compensate for the relative phase deviation caused by different clock paths in real time when voltage or temperature dynamically changes, and thus ensures long-term stable alignment of clock signals in the high-speed interface.

This disclosure provides a clock synchronization method for ultrasonic radar chips and an ultrasonic radar chip, relating to the field of ultrasonic radar technology. The clock synchronization method for ultrasonic radar chips, applied to each ultrasonic radar chip in a multi-ultrasonic radar array system, includes: receiving a synchronization pulse signal; a host computer sending a synchronization pulse signal to all ultrasonic radar chips in the multi-ultrasonic radar array system every first time interval; identifying a valid synchronization command corresponding to the synchronization pulse signal; the valid synchronization command including a synchronization start time; and, based on the valid synchronization command, performing a reset operation on the frequency divider circuit associated with the clock source within the ultrasonic radar chip at the synchronization start time. This enables the ultrasonic radar chips in the multi-chip array to achieve clock phase synchronization, significantly improving the synchronization and consistency of multi-channel signal sampling, thereby improving the angle measurement accuracy and system reliability based on time difference or phase.

The application relates to the field of audio compensation technology and provides an audio device, a method, equipment and a medium based on DAC module optimized delay difference. The audio device comprises a clock generation circuit which generates a reference clock signal; a clock distribution circuit which buffers the reference clock signal to obtain a first working clock to a DAC module and performs frequency division to obtain a second working clock to a digital audio processing circuit; the digital audio processing circuit processes a digital audio signal according to the second working clock, outputs an audio data stream and a synchronous reference clock signal; the DAC module detects a phase difference between the first working clock and the reference clock signal, generates a phase error signal and filters the phase error signal to obtain a phase adjustment value, adjusts the phase of the first working clock to generate a sampling clock according to the phase adjustment value, makes a sampling time point located in a data stable interval and compensates for a sampling deviation caused by the propagation delay of the first and second working clocks. The application eliminates clock delay mismatch and improves audio linearity and fidelity.

This invention discloses a zero-delay buffer device and method with a programmable capacitor array, belonging to the field of communication technology. The zero-delay buffer device with a programmable capacitor array of this invention includes a programmable capacitor module and a phase-locked loop (PLL) module. The programmable capacitor module includes a primary switch, a coarse adjustment capacitor, a secondary switch, and a fine adjustment capacitor. The PLL module includes a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, a first frequency divider, and a second frequency divider. The zero-delay buffer device with a programmable capacitor array of this invention can compensate for signal interference caused by different application environments and load conditions through programmable capacitors without changing the hardware, and the output clock signal phase is consistent with the input clock phase, exhibiting zero delay.

The application discloses a kind of multi-screen display synchronous display optimization methods.This method includes: obtaining the extended display identification data of each display and timing parameter;Based on the actual time stamp of the vertical synchronization signal of each display clock monitor, construct timing drift characteristic model;Select timing reference source or generate virtual reference clock;Delay compensation instruction is inserted in GPU rendering command stream, and the scanning start offset address of the frame buffer of secondary display is adjusted dynamically, and the physical clock phase difference between each display is compensated.In addition, for the mixed refresh rate scene, a proactive double buffering queue is established, and a complete frame is selectively output based on the tear risk index.The application can achieve microsecond-level accurate synchronization of multi-screen display at the software level without external Genlock hardware, effectively eliminating the tearing phenomenon caused by heterogeneous screen clock drift and the periodic stutter caused by mixed refresh rate.