133 results about "Clock phase" patented technology

This disclosure provides a charge pump circuit. The charge pump circuit according to this disclosure includes one or more cascaded boost units and output units having the same structure. Each boost unit has a dual-branch structure with top and bottom symmetry and connected to two sets of four-phase clock signals with opposite clock phases. By adjusting the phase relationship of the four-phase clocks, the rise time of the gate voltage of the transfer transistor can be delayed by advancing the falling edge of the driving clock of the secondary capacitor and delaying its rising edge. This ensures that the transfer transistor is in the off state at the moment of high-low phase switching, thereby avoiding the problem of reduced charge transfer efficiency caused by reverse charge flow between the input and output nodes of the boost unit.

The invention discloses a power grid time frequency change trend prediction method and system based on intelligent electric meter data fusion, and the method comprises the steps: measuring the network transmission delay and time deviation between a master clock and a slave clock of a power grid, obtaining an initial time frequency deviation sequence, carrying out the error calibration, carrying out the data fusion after time domain alignment, and carrying out the prediction of the time frequency change trend. Generating a fusion time sequence; performing recursive estimation on the fusion time sequence, outputting an optimal time frequency deviation sequence, and performing synchronous estimation to obtain a clock phase error, a frequency error and frequency drift as state characteristic quantities; and training a preset machine learning prediction model by taking the optimal time frequency deviation sequence as a supervision signal and taking the state characteristic quantity of the corresponding moment as input, and obtaining a prediction result of the power grid time frequency change trend in the future period based on the trained time frequency change trend prediction model. According to the method, the power grid time synchronization precision and prediction capability are remarkably improved, and reliable technical guarantee is provided for stable operation of a power system.

The present invention relates to the field of time synchronization, and relates to a precise clock synchronization parameter tracking method based on an augmented Kalman neural network. In the method, for a multi-hop network scenario where an ambient temperature changes and a link transmission delay is asymmetric, taking into account the impact of an accumulated asymmetric link transmission delay in a multi-hop network on clock synchronization accuracy, a multi-hop network clock observation equation containing an accumulated asymmetric link delay is derived, and on the basis of a quadratic polynomial model of a temperature and a clock frequency offset, a recursive state equation of the clock frequency offset and a temperature change is established; the evolution processes of an accumulated asymmetric delay and an unknown temperature coefficient are modeled as a first-order linear difference equation, and the accumulated asymmetric delay and the unknown temperature coefficient are augmented to a clock parameter tracking state space model; and an augmented Kalman neural network algorithm is used to realize joint tracking of a clock phase offset and a clock frequency offset of a slave node. This method employs a hybrid data-model-driven approach to perform joint tracking of the clock phase offset and frequency offset, thereby improving accuracy and robustness of clock parameter tracking.

The invention provides a jitter tolerance measuring device and a jitter tolerance measuring method, which can automatically calculate the confidence level of an output signal of a measured object when the jitter tolerance is obtained, and can quickly and easily confirm the confidence level of the jitter tolerance after a jitter tolerance test. A jitter tolerance measurement device is provided with: an error code measurement unit that measures, within a predetermined measurement time, an error measurement value of an output signal of a DUT that receives a code pattern signal synchronized with a jitter clock phase-modulated by a jitter modulation signal; a jitter tolerance measuring unit that changes the jitter amplitude and jitter frequency of the jitter modulation signal and estimates, for each jitter frequency, the maximum jitter amplitude at which the error measurement value measured by the error code measuring unit is equal to or less than a prescribed allowable value as the jitter tolerance of the DUT; a confidence level calculation unit that calculates a confidence level relating to an allowable value of the error rate of the output signal of the DUT; and a display unit that displays a result display screen showing the shake tolerance and the confidence level.

This invention provides a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. A sensor array is deployed along the critical signal path to simultaneously acquire high-frequency crosstalk spectrum and timing eye diagram parameters, generating a crosstalk intensity matrix (CIM) and a timing margin heatmap (TMM) to achieve multi-dimensional quantitative characterization of signal integrity. Based on the CIM, the main interference source is located, and the impedance of the affected line is dynamically adjusted and a reverse compensation current is injected to cancel high-frequency crosstalk at its source. The margin attenuation is predicted using a pre-trained model, and the clock phase of the affected line is fine-tuned to compensate for timing deviations. The optimized efficiency index per unit energy consumption after compensation is calculated, triggering a dynamic update or re-compensation mechanism for the strategy library. This invention achieves dynamic synergy between crosstalk suppression and timing optimization based on a closed-loop architecture composed of monitoring data, neural network prediction, dual-loop compensation, energy efficiency verification, and strategy learning.

The application relates to a low-power four-phase distributed digital low-voltage difference linear voltage stabilizer, belonging to the technical field of electronic circuits, comprising a four-phase clock circuit and four digital LDO subunits connected to the same load network; the four-phase clock circuit is used for converting an input clock signal into clock signals with the same frequency and different phases through a clock phase adjustment channel composed of four frequency dividers and three inverters, and outputting the clock signals to the connected four digital LDO subunits for time sharing and phase control; the digital LDO subunit is used for comparing the size of an output voltage of the subunit with two reference voltages through an internal voltage judgment circuit composed of double comparators and a fast trigger loop composed of a controller, and stably controlling the output voltage between the two reference voltages according to the voltage comparison. The application effectively optimizes the transient response speed and power consumption of the digital LDO.

To compensate for the nonlinearity of a phase interpolation (PI) circuit, the interpolation clocks of two PI circuits receiving different interpolation codes may be summed. However, even if the nonlinearity of the interpolated clocks has opposite polarities, they may have different magnitudes, causing some nonlinearity. A weighted summing PI that sums the interpolated clocks of two PI circuits includes a weighted summing circuit that uses weight signals to generate a weighted summing interpolated clock having an interpolated phase between the phases of the interpolated clocks based on the weight signals. Consequently, the phase of the weighted summing interpolated clock may be more influenced by the phase of one of the interpolated clocks from the two PI circuits than by the phase of the other. To reduce nonlinearity in the weighted summing PI, a weight correction circuit may be included to select a balanced weight signal.

A system and method for performing digital calibration of non-linearity in a circuit is presented. The circuit includes a phase detector, a statistics gathering device, and a feedback device. The phase detector provides information regarding a relationship between a clock from the programmable clock phase circuit and a reference signal. The statistics gathering device is coupled to the phase detector. The statistics gathering device receives an output of the phase detector to measure linearity of the programmable clock phase circuit. The feedback device is coupled to the statistics gathering device. The feedback device controls a delay and adjusts a phase of the clock based on measured values received from the statistics gathering device.

The invention discloses a phase convergence method, circuit and chip for XGSPON uplink burst data transmission, and the method comprises the steps: obtaining first sampling data generated by a lead code of double oversampling burst data, recording even-number-bit data as a first even-number-bit sequence, and recording odd-number-bit data as a first odd-number-bit sequence; lagging the sampling clock phase of the burst data by a first preset angle; acquiring second sampling data generated by oversampling the preamble by two times of a sampling clock phase lagging behind the first preset angle, recording the even-number bit data as a second even-number bit sequence, and recording the odd-number bit data as a second odd-number bit sequence; performing preset logic processing on the first even bit sequence, the first odd bit sequence, the second even bit sequence and the second odd bit sequence, and determining a hopping edge position of the lead code according to a preset logic processing result; and adjusting the sampling clock phase of the burst data according to the jump edge position of the lead code. According to the invention, the time window of phase convergence is shortened, and the effective bandwidth of XGSPON uplink communication is improved.

The application relates to the technical field of laser intersatellite link communication ranging, and provides an optimization method and device for improving the ranging precision of a laser intersatellite communication ranging link, which comprises the following steps: acquiring sampling data of a photoelectric detection signal of the laser intersatellite communication ranging link in real time; performing interpolation recovery on the sampling data according to current loop interpolation parameters; performing clock phase error phase discrimination on the interpolation recovery data, wherein the phase discrimination gain coefficient needs to be corrected through real-time amplitude monitoring of the interpolation recovery data; filtering the clock phase error phase discrimination result; updating the loop interpolation parameters and the super-resolution code phase accurate ranging result by using the filtered clock phase error phase discrimination result; and extracting the super-resolution code phase accurate ranging result. The application can correct the phase discrimination gain coefficient in real time through real-time monitoring of the amplitude change, so that the ranging precision does not change with the amplitude change of the received light signal, and the ranging precision under the dynamic amplitude change working condition of the laser intersatellite link is improved.

Clock phase tuning method including supplying a current (lout) to a capacitor (CL) when first and second clock signals (CK1, CK2) are at a first logic state to generate an voltage (Vout) across the capacitor during a first interval; supplying or drawing a current (lout) to or from the capacitor based on an enable signal when the first and second clock signals are at first and second logic states to generate the voltage across the capacitor during a second interval; drawing a current from the capacitor when the first and second clock signals are at the second logic state to generate the voltage during a third interval; drawing or supplying current from or to the capacitor based on the enable signal when the first and second clock signals are at second and first second logic states to generate the voltage across the capacitor during a fourth interval; and generating a clock signal (Ckout) based on the voltage.

The invention provides a low-jitter pulse signal generation circuit, which relates to the technical field of synchronous control signals and comprises an FPGA (Field Programmable Gate Array) chip U1 and a low-jitter clock phase-locked loop chip U2, the low-jitter clock phase-locked loop chip U2 is connected with the FPGA chip U1, and the low-jitter clock phase-locked loop chip U2 is connected with the crystal oscillator U5 or the external reference clock input interface U6; the low-jitter clock phase-locked loop chip U2 is connected to the FPGA chip U1; the clock fan-out chip U3 is connected to the low-jitter clock phase-locked loop chip U2; the high-speed driving chip U4 is connected to the clock fan-out chip U3, the high-speed driving chip U4 is connected to the FPGA chip U1, and the high-speed driving chip U4 is connected to the digital pulse signal output interface U7. The circuit has the advantages of extremely low output signal jitter, excellent time sequence margin and reliability, high flexibility and expandability, capability of supporting internal and external clock reference and wide application scene.

The invention relates to the technical field of electronic system time sequence control, in particular to a multi-system clock synchronization method based on a low-frequency calibration clock, which is characterized in that a main system adopts a high-stability clock source and simultaneously generates a high-frequency data clock and the low-frequency calibration clock of which the frequency is less than one thousandth of that of the data clock through a clock management unit; the characteristics of strong anti-interference and high transmission quality of the low-frequency clock are utilized, and the low-frequency clock is sent to each slave system through the optimized clock distribution network. Each slave system extracts a low-frequency calibration clock through a clock recovery circuit, a high-precision time interval measurement unit is adopted to measure the time difference between a local clock and the calibration clock, and the measurement precision and stability are improved through digital signal processing. And each slave system inputs the time difference as a control quantity into a digital regulation system, dynamically regulates the phase of a local clock, and judges a synchronous locking state through a locking state detection mechanism, thereby realizing high-precision, long-term and stable clock synchronization among multiple systems.

The invention discloses a dynamic behavior authentication security system and method for industrial Internet of Things equipment, and relates to the technical field of authentication security. During operation of the system, equipment dynamic parameters including electromagnetic radiation spectrum, power supply ripple, micro-current jitter, micro-vibration entropy, thermal transient recovery, clock phase noise and network delay jitter are acquired; the method comprises the steps of forming an original multi-channel signal flow, performing preprocessing, constructing a multi-working-condition reference fingerprint database, calculating deviation of each parameter based on a distribution distance, aggregating the deviation into physical layer deviation and network layer deviation through an unweighted norm mode, generating a behavior consistency index BCI based on the deviation of the physical parameter and the network parameter, performing first evaluation and grading judgment, and performing second evaluation and grading judgment. According to the method, perturbation challenges are injected into gray area equipment, multi-dimensional responses under perturbation are collected, an active challenge coherence consistency index ACCI is calculated, and equipment authority adjustment, network segment isolation, degraded operation or safety linkage measures are executed based on double evaluation results of the BCI and the ACCI.

The application relates to a data and clock phase difference correction method, which comprises the following steps: a receiver performs secondary synchronization on an IO signal based on a CLK signal to obtain an IO synchronization signal; a starting bit falling edge pulse signal is obtained according to the IO synchronization signal, and then a starting bit enable signal is set; the delay duration of the receiver and the IO signal is obtained; when a check bit error of a character frame received by the receiver occurs, a compensation time is determined, the data line is taken over at the compensation time according to the delay duration, the data line is driven to a low level, and the character frame is retransmitted by a transmitter. The receiver of the application can better receive the starting bit on the data line, has smaller timing requirements for the other party of communication, and can communicate with more products. The application avoids possible misjudgment and bidirectional driving of the transmitter, enables the communication between the two parties to be stably carried out, improves the performance of the interface, and enhances the compatibility. The application also relates to a receiver, a chip and a device.

The application discloses a method for automatically identifying and matching a 5G front transmission network interface, and belongs to the technical field of computers.The method comprises the following steps: a QSFP interface detection step and an SFP interface detection step.The method adopts a receiving side clock phase-locked loop adaptive configuration technology, a clock recovery circuit automatic adjustment and sampling technology and an encoding error code detection technology, and realizes the functions of fast automatic scanning and matching of port rate, line encoding and frame protocol by judging whether the following conditions are normal: PLL locking, frequency deviation range, short-time frequency stability, encoding without exception and frame synchronization, so that the testing and troubleshooting time of the 5G front transmission interface is greatly shortened.

This invention discloses a control method and system for a distributed motion controller, relating to the field of motor control technology. The method includes: acquiring operational data from the motion controllers of each production line via real-time Ethernet and processing the acquired data; performing fuzzy inference based on the underlying single-axis servo fuzzy controller of the motion controller to obtain position feedforward compensation time and distributed clock phase adjustment; performing fuzzy inference based on the upper-level production line collaborative fuzzy scheduler of the main controller to obtain speed multipliers and global command timestamp offsets; generating motor control commands conforming to the real-time Ethernet protocol; and using a distributed clock synchronization mechanism to synchronously adjust the operating parameters of the servo motors of each production line. By real-time monitoring and scheduling of the motion controllers of multiple production lines, multiple production lines can cooperate with each other, achieving intelligent dynamic adjustment of the production line system, thereby improving the processing efficiency of the production line system.

The embodiment of the invention provides a time synchronization method and synchronization device for a multimode redundancy computer system level, and the method comprises the steps: each module has a handshake pulse receiving moment and a handshake pulse generating moment at the same time in a preset synchronization time period, which indicates that the two modules are used as a target module when the handshake synchronization is successful; acquiring a handshake pulse receiving moment and a handshake pulse generating moment of the target module from a handshake synchronization sub-module of the target module through a clock phase locking synchronous control state machine of the target module; a clock phase difference of each target module is determined through a timer comparison output logic unit of each target module according to a handshake pulse receiving moment and a handshake pulse generating moment of the target module; and adopting a synchronization pulse to adjust a square wave signal for timing the local clock of the target module according to the phase difference, so that the phase of the clock of the target module is synchronized. And the time synchronization of the flight control computer with multimode system level redundancy is realized.

The invention discloses a delay search method and system for a delay phase-locked loop, a computer and a medium, and the method comprises the following steps: enabling a signal to activate a finite-state machine, and jumping to a search state; based on the preset configuration of the finite-state machine, linear step length search is carried out in the guard band range to locate a target phase, if the target phase is not found in the guard band range, linear step length search is carried out again after the guard band range is expanded, and when the real-time phase is equal to the target phase, a symbol state is entered; in the symbol state, the slope of real-time phase change is calculated, and symbol matching is verified; and if the symbols are matched, entering a phase-locked state, fixing a real-time delay change value in the phase-locked state, and pulling up a phase-locked loop activation signal. According to the invention, the digital code which is output by the phase discriminator and represents the phase relationship between the reference clock and the input clock can be received, the delay is searched in a linear search mode, the control signal is sent to the delay line, and the clock delay is changed until the clock meeting the requirement is generated.

This application relates to the field of data verification technology, specifically to a data verification method and apparatus for a chip programming system. The method includes: for a multi-channel parallel chip programming system, statistically analyzing the clock cycles of each channel within each time window; determining the clock phase offset of each channel; evaluating the deviation between each channel and a second reference channel in the current clock cycle and the deviation of the clock phase offset, obtaining the timing deviation of each channel; and dynamically determining the verification delay time of each channel using the timing deviation and clock cycle, generating the verification trigger time for each channel for data verification. This balances verification accuracy and overall efficiency.

The invention discloses a high-synchronism display double-screen driving system, which relates to the technical field of display double-screen driving, and comprises a main control unit module, a double-path display controller module, a synchronous control logic module, a frame buffer system module, a signal transmission link module and a power supply and time sequence management module, the main control unit is used for generating a time sequence reference, managing frame cache data and distributing a synchronization signal; the two-way display controller module is used for being connected with the main control unit module. According to the high-synchronism display double-screen driving system, through clock homologous phase locking, phase dynamic calibration, transmission delay compensation and other core technologies, the double-screen synchronization error is controlled to be within the clock phase difference, and compared with a traditional double-screen driving system that the synchronization error is usually larger than or equal to 30 degrees, the synchronization precision is improved by one order of magnitude; and the problems of cross-screen tearing, flickering and frame dislocation can be effectively eliminated.

The invention provides a VA-based indoor environment composition method under a narrowband signal condition. In a single-base-station and single-antenna scene, high-precision environment map construction is realized through the RRoF of multipath signals. In order to solve the problems that the time delay resolution of a narrow-band signal is limited and absolute ToF measurement is easily influenced by clock phase deviation, an RToF is adopted as a supervision signal to suppress system errors. By designing DNN, end-to-end learning is carried out on nonlinear mapping from a user position to VA, so that manual modeling of a complex reflection model is avoided. In addition, an iterative optimization algorithm based on ToF geometric consistency check is introduced, the network is retrained by screening high-confidence samples, VA positions are self-supervised and corrected, and the result is ensured to be stable and convergent. The method gets rid of dependence on a multi-antenna array and special hardware, reduces the cost and deployment difficulty, and provides reliable composition technical support for indoor scenes such as underground parking lots and shopping malls.

The application discloses a clock phase difference control-based electro-optic element driving adjusting device, method and equipment. The device comprises a clock phase modulation circuit for generating at least one first clock signal and at least one second clock signal; at least one first clock level conversion driving circuit and at least one second clock level conversion driving circuit, which are respectively used for amplifying and converting the first clock signal into a first driving level and amplifying and converting the second clock signal into a second driving level to form an alternating voltage across the electro-optic element; and the clock phase modulation circuit can adjust the phase difference between the first clock signal and the second clock signal to adjust the brightness of the electro-optic element. The device has the advantages of high efficiency and flexibility in adjusting the electro-optic element and is also helpful to realize the miniaturization of the device.

A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1 / n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1 / n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1 / n of the clock period of the switch-off duration.

The application relates to the field of digital signal processing, in particular to a digital signal processing system and method based on a dynamic clock anti-jitter algorithm, which comprises the following steps: collecting historical jitter data of a clock signal in real time through a clock data collection module; generating jitter statistical characteristic parameters by using a Gaussian mixture model dynamic modeling module; realizing sub-nanosecond level real-time phase compensation by means of an extended Kalman filter correction module; dynamically adjusting an I2S master clock phase in cooperation with a software programmable clock generation module; and realizing a prediction-compensation feedback mechanism to complete jitter suppression through a closed-loop control unit. The application achieves the technical effects of significantly reducing clock jitter, improving digital signal processing precision and stability, and especially showing excellent anti-jitter performance in a high-frequency signal processing scene.

The present application relates to an integrated circuit, a cross-clock domain data transmission method, an electronic device, and a storage medium. The integrated circuit comprises a first clock domain and a second clock domain; the first clock domain comprises a first pointer control module; the second clock domain comprises a second pointer control module; the first pointer control module comprises a first synchronization pointer control module; the first synchronization pointer control module is configured to: in response to the frequency of the first clock signal being greater than that of the second clock signal, on the basis of a second clock phase and a second clock period of the second clock domain, the first clock signal and a first clock phase of the first clock domain, determine a phase relationship between the first clock signal and the second clock signal, and determine a first pointer control signal on the basis of the phase relationship; and in response to the frequency of the first clock signal being smaller than that of the second clock signal, determine that the first pointer control signal is a first value, so that a first read pointer and a first write pointer increase by the first value in each clock period of the first clock signal.

An integrated circuit includes a plurality of ADC channels. During a calibration process of the ADC channels, the integrated circuit utilizes derivative filters to calculate a phase difference between the ADC channels. During a calibration process, the integrated circuit utilizes clock phase alignment circuits to align the phases of the ADC channels based on the outputs of the derivative filters.

An electronic device includes a phase detection circuit configured to detect a difference between the phases of a reference clock and a feedback clock and a phase-locked signal generation circuit configured to generate a phase-locked signal based on the results of the detection of the difference between the phases of the reference clock and the feedback clock. The phase-locked signal generation circuit is configured to generate the phase-locked signal when the difference between the phases of the reference clock and the feedback clock is equal to or smaller than a first phase difference after the start of an initial operation and configured to stop the generation of the phase-locked signal when the difference between the phases of the reference clock and the feedback clock is equal to or greater than a second phase difference, which is greater than the first phase difference, after outputting the phase-locked signal.

The application relates to the technical field of bus communication, and particularly discloses a servo driver bus communication system for multi-motor synchronization, which comprises a reference module, a clock module, a phase conversion module and an adjustment module. The reference module comprises a bus master station for sending a test clock signal with a time stamp, and a slave station for feeding back a signal; the master station calculates the time consumption and screens the slave station with the shortest time consumption as a reference slave station. The clock module acquires the clock difference value of the reference slave station, calculates and issues the calibration compensation amount of each slave station, and adjusts the local clock of the corresponding slave station according to the compensation amount. The phase conversion module collects the motor rotor pulse number of the slave station, converts the pulse number at the reference time into the actual phase based on the encoder resolution, and uploads the actual phase. The adjustment module calculates the deviation by taking the reference phase as the reference, marks the target slave station if the deviation exceeds a threshold value, calculates the correction amount, and issues the adjustment instruction to complete the phase calibration. Through the reference screening, clock calibration, phase conversion and closed-loop adjustment, the multi-motor synchronization error problem is solved, the collaborative precision and stability are improved, and technical support is provided for industrial automation.

A communication circuit is disclosed. The communication circuit includes a calibration system configured to receive clock signals having first and second clock phases and first and second duty cycles, respectively, wherein the calibration system is further configured to receive input data and to adjust the input data based in part on the input data and in part on the first and second duty cycles to generate adjusted data. The communication circuit further includes a mixer configured to receive the clock signals and to receive the adjusted data, wherein the mixer is configured to generate output data based on the clock signals and the adjusted data, and wherein due to the adjustment of the input data to generate the adjusted data, mismatches in the output data due to the first and second duty cycles being different are reduced.