Low-power dissipation RS latch unit and low-power dissipation master-slave D flip-flop

Abstract

The invention discloses a low-power dissipation RS latch unit and a low-power dissipation master-slave D flip-flop, which is characterized in that the low-power dissipation RS latch unit comprises an input driving and synchronizing circuit, a pull-down circuit, a function control circuit, a first phase inverter and a second phase inverter, wherein the first phase inverter and the second phase inverter are mutually overlapped and coupled. The low power dissipation master-slave D flip-flop is composed of an input phase inverter, a clock phase inverter, a first low-power dissipation RS latch unit and a second low-power dissipation RS latch unit, wherein the first low power dissipation RS latch unit and the second low power dissipation RS latch unit have the same inner structure and are cascaded. The low power dissipation master-slave D flip-flop has the advantages that the low-power dissipation RS latch units use three kinds of leaked power consumption lowering technology, i.e. P-type logic technology, function control technology and double-threshold technology, so that the low-power dissipation RS latch units have better leaked power consumption inhibiting performance. The low-power dissipation master-slave D flip-flop has simple and totally symmetrical circuit structure. Compared with the traditional single-threshold transmission gate D trigger circuit, the invention can save 80% of leaked power consumption and 40% of total power consumption in the 90 nm process, so that the invention is suitable to serve as a digital circuit unit to the design of low-power consumption integrated circuits in the deep sub-micron CMOS process.

Description

technical field [0001] The invention relates to a D flip-flop, in particular to a low-power RS ​​latch unit and a low-power master-slave D flip-flop. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the scale and complexity of existing integrated circuits are increasing day by day, and the problem of power consumption of integrated circuits is becoming more and more prominent. Power consumption has become a factor in addition to speed and area in integrated circuit design Another important constraint of . The low-power design technology of integrated circuits has become an important research hotspot in the field of integrated circuit design. The power consumption of CMOS digital integrated circuits is mainly composed of dynamic power consumption, short-circuit power consumption and leakage current power consumption. In the CMOS technology above 0.13μm, the dynamic power consumption accounts for the vast majority of th...

AI Technical Summary

Problems solved by technology

1. The additional circuit introduced consumes energy while reducing the leakage power consumption; 2. It affects the performance of the circuit while reducing the leakage power consumption

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