3649results about "Electric pulse generator" patented technology

An output drive circuit includes: a totem-pole output including: a high-side transistor (HST) with drain and source, an output stage power supply voltage applied to the drain, the source connected to the first node (N1); and a low-side transistor with source and drain, a ground voltage applied to the source, the drain connected to N1; and a bootstrap part including a capacitor supplying charge to a gate of HST when on, the charge being charged when HST is off, and one terminal of the bootstrap part connected to N1, the output drive circuit further including: a first transistor (T1) that conducts when HST is to be on, T1 connected between a drive circuit power supply voltage and the gate of HST; and a second transistor conducting when HST is to be turned on, the second transistor connected between the other terminal of the capacitor and HST gate.

The invention relates to an output control method and system for a pulse power supply, and the method comprises the following steps: collecting the output voltage waveform of the pulse power supply, and obtaining an output voltage sampling sequence; carrying out wavelet transform decomposition on the voltage waveform characteristic coefficient, and extracting the voltage waveform characteristic coefficient; self-adaptive threshold segmentation is carried out based on the feature coefficient, and pulse edge feature points are identified; generating a waveform compensation parameter sequence through dynamic compensation calculation; modulating a PWM (Pulse Width Modulation) control signal by using the sequence to obtain an optimized PWM waveform sequence; finally, the parameters of the drive circuit are adjusted based on the optimized PWM sequence, stable control over the output voltage waveform is achieved, and the technical problems that a traditional pulse power supply mostly adopts a PWM control strategy with fixed parameters, output fluctuation caused by load abrupt change, temperature drift and device aging factors is difficult to cope with, and waveform distortion is caused are solved.

Disclosed are a method and an apparatus of digital feedback based adaptive delay time control for a high efficiency active rectifier. According to the present invention, provided is an apparatus for digital feedback based adaptive delay time control, which adaptively compensates a driving delay of a switch by controlling a time of a delay circuit through a digital feedback-based compensation technique, and operate the switch at an appropriate timing in spite of changes in operation environments such as an input voltage and a load to increase the efficiency of an AC-DC rectifier.

A receiver circuit is configured to generate a reception symbol from a multi-level signal. The receiver circuit is configured to generate three compensation signal pairs from an input signal pair to perform a loop unrolled decision feedback equalization operation. A first summing circuit is configured to equalize the input signal pair with a first offset to generate a first compensation signal pair, and a second summing circuit is configured to equalize the input signal pair with a second offset to generate a second compensation signal pair. An averaging circuit is configured to average the first compensation signal pair and the second compensation signal pair to generate a third compensation signal pair.

A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

An array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem. A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

The invention relates to a quarter-rate architecture SerDes clock path and a serialization circuit. The quarter-rate architecture SerDes clock path comprises a PLL (Phase Locked Loop) used for generating a differential clock signal consisting of two signals with opposite phases; the four-phase clock signal generation module is used for generating four four-phase clock signals with the phase difference of 90 degrees in sequence according to the differential clock signal; the retiming module is used for performing delay processing on the input four-way parallel data according to the four-phase clock signal, so that the delay interval among the input four-way parallel data is 1UI; the 1UI PULSE generation module is used for synthesizing clock signals of two adjacent phases in four-phase clock signals of which the phase difference is 90 degrees in sequence into clock signals with 1UI pulse width; and 4, the 1MUX module is used for synthesizing the four paths of delayed parallel data into one path of serial data according to the clock signal of the 1UI pulse width synthesized by the 1UI PULSE generation module.

Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage domain and the first voltage domain. The methods and systems generate an output of the thin-oxide device interface using first and second thin-oxide devices, the output of the thin-oxide device interface having a range corresponding to the second voltage domain.

A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.

In an example, a level shifter includes a low side having first and second inputs. The level shifter also includes a high side, where the high side has a latch having first and second terminals. The high side also includes a current comparator including first and second current mirrors. The high side includes isolation circuitry including first and second transistors, in which the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror.

An object is to provide a technique that suppresses heat generation in a first semiconductor switching element and a second semiconductor switching element. A semiconductor device includes a gate drive circuit that drives each of the first semiconductor switching element and the second semiconductor switching element based on an input signal. When a first gate voltage applied to the first gate to turn On the first semiconductor switching element is lower than a first threshold, the gate drive circuit turns Off the first semiconductor switching element after turns Off the second semiconductor switching element regardless of the input signal.

The invention provides a dynamic latch, comprising an input terminal for inputting a first data; an output terminal for outputting a second data; a clock signal terminal for supplying a clock signal; a data transmission unit for transmitting the first data under control of the clock signal; and a data output unit for converting the first data into the second data. The data transmission unit and the data output unit are sequentially connected in series between the input terminal and the output terminal, and a node is provided between the data transmission unit and the data output unit. The dynamic latch further comprises a data retention unit electrically connected to the node. The retention time of data can be effectively extended, thereby improving data security and accuracy.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

The embodiment of the invention provides an excitation signal generation method and system and a digital eddy current sensor, and the method comprises the steps: outputting a square wave signal through a pulse width modulation assembly of a microcontroller unit, and enabling the frequency and resolution of the square wave signal to be adaptive to eddy current probes with different inductance values; inputting the square wave signal into a low-pass filter for filtering, and setting the cut-off frequency of the low-pass filter, the suppression times of higher harmonics and the attenuation slope so as to output a sine wave signal with a target total harmonic distortion range; the amplitude of the sine wave signal is collected in real time, and the pulse width modulation duty ratio and the passband gain of a low-pass filter are dynamically adjusted in combination with a digital control algorithm, so that the sine wave signal is subjected to self-adaptive adjustment and correction and is output; and taking the sine wave signal as an excitation source of an eddy current probe, and driving the eddy current probe to carry out nondestructive testing. According to the invention, the excitation signal which gives consideration to high-frequency signal generation, deep harmonic suppression and digital adaptive adjustment can be generated.

An amplification circuit is configured to differentially amplify an input signal and a reference voltage to generate an output signal when a clock signal has a first logic level. The amplification circuit is configured to precharge the output signal when the clock signal has a second logic level. The amplification circuit is configured to adjust a current driving force that precharges the output signal based on the reference voltage.

A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

A method for validating operation of a driver integrated circuit includes providing a signal using an output node. The signal is provided using multiple set points in response to a change in state of an input signal. Each set point corresponds to a different phase of a multi-phase transition of the signal. The method includes providing a timer value at an end of a phase of the multi-phase transition and determining whether the signal is in a target signal range of the phase based on the timer value at the end of the phase, a predetermined value defining the target signal range of the phase, and a predetermined time limit for the phase. A current through the output node may be provided using the multiple set points, and a voltage on the output node may have the multi-phase transition.

The disclosure relates to an electronic circuit to verify the integrity of a switch. The circuit comprises a voltage comparator and decoupling switch. The decoupling switch configured receive the driving signal having a first logic value to enable the monitoring of the comparison voltage and is configured to receive the monitoring enable signal having a first logic value to command the opening of the decoupling switch. The electronic circuit is configured to generate the output monitoring signal having a first logic value in an event that the switch is an open circuit and having a second logic value in an event that the switch is a short circuit.

A level shifter includes: a low voltage domain configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal; and a high voltage domain comprising a latch and a current mirror circuit configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first current pulse is active and reset when the second current pulse is active. The current mirror circuit includes a first mirroring path for the first current pulse and a second mirroring path for the second current pulse. The level shifter has a common mode slew current that is added to the non-overlapping first and second current pulses. The first mirroring path and the second mirroring path are cross-coupled such that the common mode slew current is reduced or cancelled before the non-overlapping first and second current pulses are input to the latch.

According to an embodiment, a clock signal is input to clock terminals of first and second FFs. A first signal from a Q terminal of the first FF is input to a D terminal of the second FF. A first inverter performs inversion calculation on a second signal from a Q terminal of the second FF. A signal from the first inverter is input to a D terminal of the first FF. A second inverter performs inversion calculation on the first signal. (L−1) adders each calculate a different bit of a Gray code by an addition operation based on a carry signal. A circuit block generates a carry signal for a first adder based on a logical product of the first / second signals. The circuit block generates carry signals of second to (L−1)th adders based on the second signal and a signal from the second inverter.

Circuits and methods for providing a “bootstrap” power supply for level-shifter / driver (LS / D) circuits in a FET-based power converter. In a first embodiment, linear regulators and a bootstrap capacitor provide a bootstrap power supply for level-shifter / driver circuits in each tier of a multi-level FET-based power converter. In a second embodiment, floating charge circuits and bootstrap capacitors provide an improved bootstrap power supply for level-shifter and driver circuits in each tier of a multi-level FET-based power converter. More particularly, a floating charge circuit configured to be coupled to an associated bootstrap capacitor includes a first sub-circuit configured to pre-charge the associated bootstrap capacitor when coupled and a second sub-circuit configured to transfer charge between the bootstrap capacitor and a bootstrap capacitor coupled to an adjacent floating charge circuit.

A voltage level shifter is provided. The voltage level shifter includes a main level shifter, a first bias level shifter and a second bias level shifter. The main level shifter includes a first N-type transistor and a second N-type transistor cross-coupled to each other, a third N-type transistor and a fourth N-type transistor controlled by a first bias voltage, a fifth N-type transistor and a sixth N-type transistor respectively controlled by a second bias voltage and a third bias voltage, and a first P-type transistor and a second P-type transistor configured to respectively receive an input signal and an inverted input signal which have opposite voltage values. The first bias level shifter generates the first bias voltage according to an enable signal. The second bias level shifter generates the second bias voltage and the third bias voltage according to the first bias voltage and the input signal.

Certain aspects are directed towards an interpolator and / or a clock generator. An example interpolator generally includes: a first capacitive element; a first current source; a first switch coupled between the first capacitive element and the first current source; a second current source; a second switch coupled between the first capacitive element and the second current source; and a first comparison circuit having an input coupled to the first capacitive element.

A reconfigurable driver in an I / O circuit has a first transistor provided in a first pullup structure, a second transistor provided in a second pullup structure, and a control circuit that generates a control signal provided to a gate of the second transistor. A gate of the first transistor receives a data signal. The control signal is an inverted, delayed version of the data signal in a first mode. The control signal turns off the second transistor in a second mode. The control circuit generates the control signal using a version of the data signal when operated in a third mode. The second pullup structure may be used to provide one-shot equalization to an output of the reconfigurable driver when the second pullup structure is operated in the first mode. The second transistor may be a thin-oxide PMOS transistor. The first transistor may be a thin-oxide NMOS transistor.

Systems and devices for signal arbitration are described. A first asynchronous circuit can receive and sanitize a first non-persistent signal representing a first request to generate a first persistent signal. A second asynchronous circuit can receive and sanitize a second non-persistent signal representing a second request to generate a second persistent signal. A mutual exclusive circuit can arbitrate between the first persistent signal and the second persistent signal and output a grant signal to issue a grant. A control circuit can control an operation mode of the first and second asynchronous circuits based on a control signal, a first grant signal indicating a grant status of the first request, a second grant signal indicating a grant status of the second request, the first persistent signal and the second persistent signal.

A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.

An apparatus includes a transmitter, a voltage regulator, an isolator, and a test controller. The transmitter has an input, an output, and a first supply voltage terminal. The input couples to the apparatus' input terminal. The voltage regulator's input couples to a second supply voltage terminal. The voltage regulator's output couples to the first supply terminal. The first terminal of the isolator couples to the output of the transmitter. A first test controller terminal couples to the second supply voltage terminal. A second test controller terminal couples to the input terminal of the apparatus. The first control output couples to the control input of the voltage regulator. The test controller changes a logic state of a control signal at the first control output from a first logic state to a second logic state.

A device includes a signal path including a plurality of inverters connected in series, which comprises a first inverter having a first input and a having first output, a second inverter having a second input coupled to the first output of the first inverter and having a second output, and a third inverter having a third input coupled to the second output of the second inverter and having a third output. The device also includes a first feedback path connecting the second output of the second inverter to the first input of the first inverter, the first feedback path including a fourth inverter and a second feedback path connecting the third output of the third inverter to the second input of the second inverter, the second feedback path including a fifth inverter.

The embodiment of the invention provides a clock gating circuit conversion method and device and related equipment, and the method comprises the steps: obtaining target circuit design data of a clock gating circuit before conversion, the target circuit design data being part of data in the circuit design data of the clock gating circuit before conversion; predicting the power consumption income of the clock gating circuit before conversion based on the target circuit design data by using a pre-established power consumption income prediction model to obtain a power consumption income prediction result; wherein the power consumption income prediction model is used for predicting a power consumption change trend between the clock gating circuit before conversion and the clock gating circuit after conversion so as to form a power consumption income prediction result; if it is determined that the power consumption income prediction result is the forward power consumption income, the clock gating circuit before conversion is converted into the clock gating circuit after conversion. According to the technical scheme provided by the embodiment of the invention, the efficiency of determining the switching effectiveness of the clock gating circuit can be improved.