1054results about "Electric pulse generator" patented technology

An output drive circuit includes: a totem-pole output including: a high-side transistor (HST) with drain and source, an output stage power supply voltage applied to the drain, the source connected to the first node (N1); and a low-side transistor with source and drain, a ground voltage applied to the source, the drain connected to N1; and a bootstrap part including a capacitor supplying charge to a gate of HST when on, the charge being charged when HST is off, and one terminal of the bootstrap part connected to N1, the output drive circuit further including: a first transistor (T1) that conducts when HST is to be on, T1 connected between a drive circuit power supply voltage and the gate of HST; and a second transistor conducting when HST is to be turned on, the second transistor connected between the other terminal of the capacitor and HST gate.

A method of generating driving patterns for an active gate driver, AGD, the method comprising controlling a power semiconductor, at a plurality of operating conditions, with the AGD. For each operating condition, one or more electrical signals of the power semiconductor are obtained, a variation in one or more key parameters of the power semiconductor is detected from the one or more electrical signals, and a driving pattern, corresponding to the variation in the one or more key parameters, is generated based on a pre-determined relationship between the variation in the one or more the key parameters and one or more driving parameters of the driving pattern. The generated driving patterns for each operating condition, and the corresponding variation in the one or more key parameters, are stored in a memory.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.

In a first aspect, the disclosure provides an apparatus (412a) for wireless communication, comprising: a first clock loop (420) comprising a first plurality of latches (422, 424) that generate a first plurality of clock signals (I, Q) having a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) having a corresponding second plurality of phases, where the first clock loop is configured to be enabled or disabled based on the first enable signal and the second clock loop is configured to be enabled or disabled based on the second enable signal. And wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.

An integrated circuit (IC) containing a circuit to be operable using one of multiple unequal power supplies during normal operation of the IC. The IC contains a one time programmable (OTP) memory containing a first bit and a second bit, with each of the bit having an initial value and being programmable to a programmed value. A configuration engine contained in the IC operates the circuit with a first selection with respect to using one of the unequal power supplies during normal operation of the IC if both of the first bit and the second bit have an equal value comprising one of the initial value and the programmed value. The configuration engine operates the circuit with a second selection with respect to using one of the unequal power supplies during normal operation of the IC if the first bit and the second bit have unequal values.

A level-shifter is provided that balances the pull-up and pull-down of a pair of internal nodes. To balance the pull-down of the internal nodes, a pull-down strength of a pull-down network is also responsive to a power supply voltage for the level-shifter. To balance the pull-up of the internal nodes, a pull-up strength of a pull-up network is also responsive to an amplitude of an input signal being level-shifted by the level-shifter.

A frequency multiplier includes an oscillator and a harmonic generator. The oscillator has a resonant cavity and a negative resistance unit. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. The harmonic generator is configured to generate a harmonic signal based on a fundamental frequency signal taken as input. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and to output an intrinsic signal with the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal.

In an embodiment, a device includes: phase frequency detector (PFD) circuitry having an input and an output; an oscillator having an input and an output, the input of the oscillator coupled to the output of the PFD circuitry; clock divider circuitry having a first input, a second input, and an output, the first input of the clock divider circuitry coupled to the output of the oscillator, the output of the clock divider circuitry coupled to the input of the PFD circuitry; and a controller having an output coupled to the second input of the clock divider circuitry.

A power supply circuit generates from the input voltage of a primary circuit system the output voltage of a secondary circuit system by driving a switching output stage. The power supply circuit includes: a pulse feedback signal generation circuit that generates a pulse feedback signal corresponding to the output voltage; an analog control signal generation circuit that generates an analog control signal corresponding to the pulse feedback signal; and a switching driving control circuit that drives the switching output stage according to the result of comparison of the analog control signal with a slope signal. The analog control signal generation circuit raises the maximum value (an internal supply voltage) of the analog control signal with a predetermined gradient during the start-up or renewed start-up of the output voltage.

A clock selector circuit (1) comprises a first input for receiving a first input clock signal (CLK1) having a first frequency, and a second input for receiving a second input clock signal (CLK2) having a second frequency, the second frequency differing from the first frequency by a frequency offset. The clock selector circuit (1) further comprises a clock output for outputting an output clock signal (CLK_OUT), a phase difference detector (7) and switching circuitry (5, 6). The phase difference detector (7) is configured to detect when a phase difference, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using a predetermined type of clock edge, being either a rising edge or a falling edge, crosses zero, and to signal this zero crossing to the switching circuitry (5, 6). The switching circuitry (5, 6) is configured, in response to receiving a zero-crossing signal from the phase difference detector (7), to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch the output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

The integrated circuit includes a delay monitor that monitors a delay of the data signal from the digital circuitry by generating a pulse having a width determined by the delay. In some embodiments, a delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal for clocking the data signal. The pulse generator generates a pulse according to the received data signal and the clock signal, wherein a width of the pulse is determined by a delay of the data signal relative to the clock signal. The event generator generates events that are temporally distributed with respect to the clock signal. As a result, the delay may be estimated based on an overlap between the event and the pulse.

The application discloses an improved structure anti-single event upset flip-flop circuit and a flip-flop, wherein the flip-flop circuit comprises a logic input circuit, a first main stage gate circuit, a second main stage gate circuit, a third main stage gate circuit, a fourth main stage gate circuit, a first slave stage gate circuit, a second slave stage gate circuit, a third slave stage gate circuit, a fourth slave stage gate circuit, a main stage latch, a slave stage latch and at least one inverter in an electric circuit connection relationship. The application can solve the technical problem that the level of the prior art is flipped and cannot be recovered when a particle is incident on the circuit in a radiation environment.

A level shift circuit (1) includes first to fourth P-type transistors, first and second N-type transistors, and a pull-up circuit (30). The first N-type transistor and the first P-type transistor are disposed between the input node and the output node, and the second P-type transistor is disposed between the first power supply and the output node. The second N-type transistor and the third P-type transistor are arranged between the inverted input node and the inverted output node, and the fourth P-type transistor is arranged between the first power supply and the inverted output node. The pull-up circuit (30) is configured to pull up the second node to the third power supply when the first node is converted from the high level to the low level, and pull up the first node to the third power supply when the second node is converted from the high level to the low level.

This provides a clock generation circuit that reduces the frequency of the clock signal when the power supply voltage increases. [Solution] The clock generation circuit 100 of the present invention includes a reference current setting unit 20, a bias voltage generation unit 110, and a ring oscillator 40. The bias voltage generation unit 110 generates a PBIAS voltage to be applied to each gate of the PMOS transistor MP3 of the ring oscillator 40, and an NBIAS voltage to be applied to each gate of the NMOS transistor MN3. In response to the power supply voltage Vcc reaching the target voltage, the bias voltage generation unit 110 increases the PBIAS voltage, thereby reducing the current supplied by the PMOS transistor MP3 and lowering the frequency of the clock signal OSC.

The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

Equipping level converters: an input circuit (120) having a first input terminal (202) and a second input terminal (204) configured to receive complementary input signals at a first voltage level (VSSA) and a second voltage level (VDDA); a cross-latch circuit (110) coupled to the input circuit (120), wherein the cross-latch circuit (110) has a first output terminal (102) and a second output terminal (104) configured to provide complementary output signals at a third voltage level (VSSB) and a fourth voltage level (VDDB), wherein the input circuit (120) has a first control node (206) and a second control node (208) configured to output a first control signal and a second control signal at the first voltage level (VSSB) and the fourth voltage level (VDDB) based on the input signals; and a follow-up circuit (130) coupled to the input circuit (120) and the cross-latch circuit (110), configured to input a first tracking signal and a second tracking signal into the cross-latch circuit (110) based on the first control signal and the second control signal, wherein the first tracking signal is greater than the first control signal and the third voltage level (VSSB), and the second tracking signal is greater than the second control signal and the third voltage level (VSSB).

A serializer circuit includes flipflops and a multiplexing circuit. A first flipflop may be configured to capture a bit of data from a first data signal during each cycle of a clock signal. A second flipflop may be configured to capture a bit of data from a second data signal during each cycle of the clock signal. The multiplexing circuit may be configured to provide an output of the first flipflop as an output of the multiplexing circuit when a delayed version of the clock signal is in a first signaling state, and to provide an output of the second flipflop as the output of the multiplexing circuit when the delayed version of the clock signal is in a second signaling state. The delayed version of the clock signal may be configured to suppress data-dependent glitches in an output signal used in subsequent stages of a receiving device.

A level shifter having: an input configured to receive an input signal, an output configured to provide an output signal, a voltage rail configured to provide a rail voltage, at least two diodes including a first and second diode connected in series between the voltage rail and the input, at least three switches, and a capacitor. The at least three switches include a first switch coupled between the voltage rail and the output of the first diode, a second switch coupled between the voltage rail and the output of the second diode, and a third switch coupled between the voltage rail and the input. The capacitor is coupled between the output of the second diode and ground.

A continuous time linear equalizer (CTLE) includes a first circuit path and a second circuit path. The first circuit path has a first step response. The second circuit path is in parallel with the first circuit path. The second circuit path has a second step response with a pulse response, and includes a transmission line that is configured to control a pulse width of the pulse response according to a length of the transmission line. An output signal of the CTLE is derived from an output signal of the first circuit path and an output signal of the second circuit path.

An integrated circuit (100A) includes an H-bridge circuit (102) having a first output node (OUT1) for coupling to the high-side terminal of an inductor (103) and a second output node (OUT2) for coupling to the low-side terminal of the inductor. A current-sensing FET (SNS-DRV) is coupled between a current source (110) and a lower supply voltage to provide a reference current (Itrip), including a peak current limit at the sensing node. A current-sensing comparator (104) has a first input coupled to the sensing node, a second input coupled to the second output node, and an output (113) coupled to send an output signal to a driver control circuit. A FET linearity detection circuit (112) is coupled to receive the gate voltage (LS2) of an active low-side power FET (Mls2) and has an output (CMP EN) coupled to enable the current-sensing comparator when the active low-side power FET operates in the linear region.

A semiconductor device includes a main circuit and a control circuit. The main circuit includes a plurality of series circuits that are connected in parallel to one another. Each series circuit includes a high-side switching element and a low-side switching element that are connected in series. The control circuit includes first to third input terminals through which a serial drive signal serving as a driving signal of each high-side switching element and each low-side switching element is inputted, a first clock signal, and a second clock signal are respectively inputted, and a plurality of output terminals. The control circuit holds the serial drive signal based on the first clock signal, and based on the second clock signal outputs, to each high-side switching element and each low-side switching element, parallel signals generated from the serial drive signal.

This application provides a frequency multiplier, including an oscillator and a harmonic generator. The oscillator includes a resonant cavity and a negative resistance unit. The harmonic generator is configured to generate a harmonic signal based on an input fundamental frequency signal. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and output an intrinsic signal by using the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. This application further provides a wireless communication device. Therefore, according to the frequency multiplier and the wireless communication device provided in this application, energy efficiency of the frequency multiplier may be improved, thereby optimizing a balance between bandwidth, energy efficiency, and power consumption of the frequency multiplier.

This application relates to a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments in the field of integrated circuit design technology. The latch includes: an excitation module for transmitting input signals to sensitive nodes N2, N4, N6, and Q through multiple clock-controlled transmission gates; an interlock feedback loop consisting of four three-input clock-gated inverting CE units and four three-input inverting CE units; a module responsible for generating voltages for sensitive nodes N1, N3, N5, and N7, and for achieving interference self-recovery of sensitive nodes N1 to N7 and Q based on signals from sensitive nodes A and B; and an AB node generation and recovery module using two four-input inverting CE units and inversion operation to generate voltages for sensitive nodes A and B from signals from N1 to N7 and Q. This latch has good TNU (Terror-Noise Nullification) immunity, enabling three-node flip-flop recovery even when any three sensitive nodes experience a TNU.

To provide a semiconductor device with reduced power consumption.SOLUTION: There is provided a semiconductor device including a first transistor and a second transistor. The first transistor is a p-channel transistor including silicon in a channel formation region, and the second transistor is an n-channel transistor including a metal oxide in a channel formation region. The metal oxide includes indium, an element M (e.g., gallium), and zinc. A gate of the first transistor is electrically connected to a gate of the second transistor, and one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. The first transistor and the second transistor can each operate in a subthreshold region.SELECTED DRAWING: Figure 9

A device includes a clock signal generator and a transmitter circuit. The clock signal generator receives a first input clock signal, generates an output clock signal, and includes a phase generator and a duty cycle corrector. The phase generator generates a plurality of second input clock signals from the input clock signal. The duty cycle corrector adjusts a duty cycle of the second input clock signal with reference to a control signal, generates a single-ended input signal and complementary output signals from the single-ended input signal, compares the complementary output signals, and generates a result of comparison that serves as the control signal. The transmitter circuit receives an input data signal, processes the input data signal in response to the output clock signal, generates an output data signal, and transmits the output data signal.

The invention discloses a high over-bias variable load type quenching device for a single photon avalanche diode, and the device comprises a quenching unit which is used for changing the resistance of a variable load tube to infinity to rapidly cut off the avalanche current when the single photon avalanche diode is avalanche, thereby achieving the variable load type quenching; the reset unit is used for generating a delay-adjustable reset signal after quenching is completed, and controlling the single photon avalanche diode to recover to a to-be-detected state; and the high over-bias supporting unit is used for enabling the two ends of the single photon avalanche diode to obtain over-bias higher than the power supply voltage under the low-voltage process. The quenching and resetting time of the quenching circuit is effectively shortened through a simple circuit structure, and meanwhile, the photon detection probability can be greatly improved through the high over-bias voltage which is nearly twice of the power supply voltage.

An asynchronous finite state machine (FSM) circuit comprises an arc cell configured to receive an analog input signal candidate for propagation over the FSM circuit as an output signal from the arc cell. In response to glitch affecting the analog input signal to the arc cell propagation over the FSM circuit of the analog input signal affected by glitch is conditioned upon either one of: i) the glitch being suppressed at the output of the arc cell, or ii) the glitch being latched within the arc cell. Propagation over the FSM circuit of the analog input signal affected by glitch takes place in response to the glitch being suppressed at the output of the arc cell irrespective of the glitch being latched within the arc cell.

This disclosure provides a power-on reset circuit, a power supply system, a chip, and an electronic device. The power-on reset circuit provided in this disclosure uses BJT transistors with different emitter areas as inputs to a current comparator. When the power supply system is powered on, a current mirror slowly raises the power supply voltage of the Schmitt trigger, causing the output of the power-on reset circuit to flip to a low level. As the power supply voltage continues to increase, the comparator's power supply voltage reaches the flip-flop threshold, causing the Schmitt trigger's power supply voltage to drop, and the output of the power-on reset circuit to flip to a high level. Simultaneously, this power-on reset circuit integrates a power-down detection function, generating a reset pulse when the system loses power to prevent the system from operating in an undefined state. This disclosure achieves a fast power-on reset response through a comparator, offering advantages such as simple circuit structure, small area, and fast response speed. Furthermore, the integrated power-down reset detection function provides better robustness.