275 results about "NAND gate" patented technology

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The utility model relates to the technical field of frequency converters, in particular to a frequency converter protection circuit used for input open-phase and relay pull-in detection, which comprises a relay pull-in detection circuit, an input open-phase detection circuit and a signal synthesis circuit. The input end A of the NAND gate is connected with the relay pull-in detection circuit, the input end B of the NAND gate is connected with the input open-phase detection circuit, and the output end Y of the NAND gate is connected with the controller. Compared with a traditional detection circuit which only has high-level / low-level signals, the technical problems that in the prior art, two detection functions occupy two signal channels, the circuit is difficult to design, and cost is high can be effectively solved, and the advantage that the states of the two detection functions can be expressed only through the same signal line is achieved.

The invention provides a self-checking circuit for overcurrent protection and a self-checking method for overcurrent protection. The signal input end of a self-checking trigger module is connected with the first output end of a control module, and the output end of the self-checking trigger module is connected with the input end of a comparator module; the output end of the comparator module is connected with the input end of the control module; the first input end of the NAND gate module is connected with the second output end of the control module, and the second input end of the NAND gate module is connected with the output end of the comparator module; and the output end of the NAND gate module is connected with the input end of the driving module. During self-checking, the control module controls the self-checking trigger module to output a level signal to the comparator module through a self-checking signal so as to simulate current input, and the comparator module judges whether input level voltage is within a preset range and outputs a comparison result to the control module. The control module can determine the state of the circuit according to the received level signal, and completes the self-inspection of the overcurrent protection circuit.

The invention discloses an overcurrent protection circuit, a driving chip and an intelligent power module wherein the overcurrent protection circuit comprises a first triode, a second triode, a sampling resistor, a first feedback resistor, a second feedback resistor, a first comparator, a second comparator, a first NOT gate, a first NAND gate and a blanking circuit. And the blanking circuit is used for eliminating noise interference of the driving chip. According to the overcurrent protection circuit, signal amplification is carried out through the first triode and the second triode at the preceding stage, then comparison is carried out through the first comparator and the second comparator, so that the comparison result is more accurate, and finally noise interference is eliminated through the blanking circuit; therefore, the condition of false triggering protection of the overcurrent protection circuit due to noise interference can be avoided.

The invention discloses an adaptive mode switching circuit of a BUCK converter for COT control. The adaptive mode switching circuit comprises a conduction time generation circuit, an OR gate, phase inverters INV1, INV2 and INV3, an NAND gate, an AND gate, RS triggers RS1 and RS2, transistors Mon, MN1, MN2 and MN3, a falling edge delay circuit, a rising edge delay circuit and a zero cross detection circuit. According to the invention, a conduction signal and a zero-cross detection signal are fed back to the conduction time generation circuit, the states of two paths of control signals in a DCM mode and a CCM mode are adaptively adjusted, logic operation is carried out on the control signals through an OR gate, and the conduction time of an upper tube is adaptively adjusted. When the DCM mode is switched to the CCM mode, the CCM control signal serves as a conduction time control signal, and the conduction time of an upper tube is increased; and when the CCM mode is switched to the DCM mode, the DCM control signal is used as a conduction time control signal, and the conduction time of the upper tube is reduced.

The invention discloses a universal multiphase clock generation circuit and a combinational logic circuit thereof. The combinational logic circuit comprises a first-stage NAND gate and a second-stage NAND gate which are cascaded, the generation circuit is constructed by taking the combinational logic circuit as a basic unit; the generation circuit is a closed loop formed by connecting 2N basic units end to end; the first-stage NAND gates of the odd-numbered basic units form latches pairwise, and the first-stage NAND gates of the even-numbered basic units also form latches pairwise; each basic unit takes the output of the adjacent previous basic unit as the input and outputs a basic clock signal with a preset duty ratio based on a preset selection signal; performing odd number of times of phase inversion on the 2N basic clock signals output by the 2N basic units to obtain 2N-phase non-overlapping clock signals; and when N is an odd number, performing NAND operation on the N groups of adjacent two basic clock signals to obtain N-phase non-overlapping clock signals.

The invention discloses a multifunctional reset circuit, which is connected with a processor and is consistent with the processor in power supply, and comprises a monitoring circuit used for monitoring the power supply voltage of the processor and a CD4011 NAND gate circuit connected with the monitoring circuit, the monitoring circuit comprises an MAX791 monitoring chip, and the MAX791 monitoring chip is connected with the CD4011 NAND gate circuit. The sixteenth pin end and the fifteenth pin end of the MAX791 monitoring chip are connected with the CD4011 NAND gate circuit, the CD4011 NAND gate circuit comprises a CD4011 chip, and the CD4011 NAND gate circuit is used for outputting a reset signal; the device has the advantages of being simple in structure, complete in function and wide in application range, the power-on reset function, the manual reset function and the crash reset function of the processor can be completed, watchdog shielding can be achieved through manual control, the software online loading function is completed, and the software online loading efficiency is improved. The method can be used for equipment requiring manual reset, power-down reset, software online upgrade and reset time, and is suitable for various processors.

Control circuit (100) which outputs a first signal to discharge charges accumulated in a source line (SL) and a bit line (BL) according to the activation of a word line (WL) and outputs a second signal to put the source line and the bit line into a potential-free state until the start of writing or reading, with respect to a memory cell which has the source line (SL), the bit line (BL), a transistor (Tr5) which is provided between the source line (SL) and the bit line (BL) and is switched on and off by a potential of the word line (WL), and a storage element (R1) connected in series with the transistor (TR5), wherein the control circuit (100) has a first transistor (Tr3) connected to the source line (SL) and a second transistor (Tr4) connected to the bit line (BL), and the first transistor (Tr3) includes a first gate terminal and the second transistor (Tr4) includes a second gate terminal, wherein the first gate terminal is connected to a first NAND gate (69) and the second gate terminal is connected to a second NAND gate (70), and wherein both the source line (SL) and the bit line (BL) are short-circuited to a ground potential at a first time point in response to the first signal and transition from their respective first potential-free states to their respective non-potential-free states, and transition at a second time point in response to the second signal to their respective second potential-free states.

An electronic device includes: an antenna, a PAM including a PA configured to amplify a transmitting signal and a protection circuit, a PMIC configured to supply voltage to the PA, and at least one processor is configured to: provide a first signal, to a NAND gate in the protection circuit, provide to a AND gate in the protection circuit, a second signal indicating a result of a logical operation between the first signal and a bias enable signal for the PA, provide to the AND gate, a third signal indicating whether the transmitting signal is input to the PAM, provide to a switching circuit, a fourth signal indicating a result of logical operation between the second signal and the third signal, identify whether to apply a bias voltage to the PA based on the fourth signal, and transmit the transmitting signal, to the external electronic device, via the antenna.

The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines and a plurality of NAND strings, which are coupled to a plurality of sense nodes. Control circuitry is configured to perform a sensing operation on the memory cells of a selected word line of the plurality of word lines. During the sensing operation, the control circuitry determines a data state to be sensed and then sets a sense time as a function of the data state to be sensed. The control circuitry then applies a reference voltage to the selected word line and, for the sense time, discharges a selected sense node of the plurality of sense nodes through a selected NAND string of the plurality of NAND strings. The selected NAND string includes a selected memory cell of the plurality of memory cells.

The invention discloses a universal input / output interface, and belongs to the technical field of transmission interfaces of digital circuits and analog circuits, the universal input / output interface comprises a TX module, an RX module and a withstand voltage protection circuit, and the TX module comprises a first phase inverter; a second inverter; a first AND gate; a second AND gate; a first NAND gate; a second NAND gate; a third NAND gate; a third AND gate; a bias circuit; a level conversion circuit; a buffer; a first pmos tube; a second pmos tube; a first nmos tube; a second nmos tube; a third pmos tube; a fourth pmos tube; the RX module comprises a Schmitt trigger; a first switch; a pull-up resistor; a pull-down resistor; a second switch; the withstand voltage protection circuit comprises a third nmos tube to a seventh nmos tube; a fifth pmos tube to a tenth pmos tube; the electrostatic discharge protection circuit includes a p-type diode and an n-type diode. The range of the output level signal is selectable, and the application scenarios of the circuit can be increased.

This invention discloses a 4-2 approximation compressor based on memristors, a control method, an apparatus, and applications. It approximates and compresses four 1-bit numbers X1, X2, X3, and X4 using two identical memristor-based majority gate circuits. The two majority gate circuits respectively implement traditional majority gate logic and a novel majority gate logic including inversion logic. The first majority gate circuit implements the traditional majority gate logic M(X1, X3, X4) to obtain the carry result of the 4-2 approximation compressor. The second majority gate circuit implements the novel majority gate logic including inversion logic to obtain the pseudo-sum result of the 4-2 approximation compressor. This invention does not rely on the cascading of a large number of basic logic units such as NAND gates and NOR gates, has a shallow logic depth, and can achieve a 4-2 compressor with good error performance with low circuit complexity, high operation speed, and low power consumption.

A battery management module, including a microcontroller unit, a first comparator configured to compare an input signal with a first reference signal and output a first comparison result and a NAND gate circuit configured to receive a first input from the microcontroller unit and a second input that is the first comparison result from the first comparator to generate an output signal, wherein, in an inspection mode, the first comparator is connected to a battery module tester, the microcontroller unit outputs a low-level signal as the first input, the first comparator receives the input signal from the battery module tester and outputs a low-level signal as the first comparison result and the microcontroller unit is further configured to receive the output signal of the NAND gate circuit and determine the NAND gate circuit is defective in response to the output signal of the NAND gate circuit being a low-level signal.

The application belongs to the field of chips, and provides a zero-temperature duty cycle adjustable oscillation circuit. The circuit comprises a first NAND gate, a first input end of the first NAND gate is connected with an output end of a first NOT gate, an output end is connected with a gate of a first NMOS tube, a drain of the first NMOS tube is connected with a gate of a second NMOS tube, a drain of the second NMOS tube is connected with an input end of a second NOT gate, an output end of the second NOT gate is connected with an input end of a third NOT gate, an output end of the third NOT gate is connected with a first input end of a second NAND gate, an output end of the second NAND gate is connected with a gate of a third NMOS tube, a drain of the third NMOS tube is connected with a gate of a fourth NMOS tube, a drain of the fourth NMOS tube is connected with an input end of a fourth NOT gate, an output end of the fourth NOT gate is connected with an input end of the first NOT gate, and the drains of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are respectively connected with a current source and a grounding capacitor. The first input end and the second input end of the first NAND gate and the second NAND gate are connected with a first input end and a second input end of a logic control chip, a first output end and a second output end of the logic control chip are respectively connected with a second input end of the first NAND gate and the second NAND gate, and the logic control chip has a reset end. The application can realize that the output frequency does not change with temperature and power voltage without increasing the chip area, and the back lock mechanism is introduced to eliminate the indefinite state in the circuit, which may cause the output frequency change problem.

The invention provides a rising edge trigger and a low noise amplifier. The rising edge trigger comprises a first phase inverter, a second phase inverter, a capacitor, a Schmitt trigger, a phase inverter circuit, an NAND gate and a third phase inverter, the input end of the first phase inverter is used for accessing an enable signal for controlling the low-noise amplifier to work; the power supply end of the second phase inverter is used for being connected to the current outflow end of a current source for providing reference current for the low-noise amplifier; the first input end of the NAND gate is connected to the output end of the inverter circuit, and the second input end of the NAND gate is connected to the output end of the first inverter; the input end of the third phase inverter is connected to the output end of the NAND gate, and the output end of the third phase inverter is used for outputting a delay control signal. According to the rising edge trigger, the area of the capacitor can be reduced according to the magnitude of the current of the accessed current source for providing the reference current for the low-noise amplifier, so that the occupied area of the rising edge trigger is reduced.

The utility model relates to a battery charging and discharging current switching control circuit. A charging control signal is respectively connected with the input ends of a first NOT gate and a first NAND gate; the output end of the first NOT gate is respectively connected with the input ends of the second NAND gate and the third NAND gate; a discharge control signal is respectively connected with the input end of the second NOT gate, the other input end of the second NAND gate and the other input end of the third NAND gate; the output end of the second NOT gate is connected with the other input end of the first NAND gate; the output end of the first NAND gate is connected with the base electrode of the first triode through the first resistor; the collector electrode of the first triode is connected with the charging power module and the emitter electrode is connected with the anode of the first diode. The output end of the second NAND gate is connected with the base electrode of a second triode through a second resistor; the collector of the second triode is connected with the discharge power module; the cathodes of the first diode and the second diode are grounded. According to the utility model, instantaneous switching of charging and discharging is ensured.

Disclosed in the present application are a logical unit circuit and an adder circuit, which are applied to a multi-bit adder. A logical operation unit circuit is used for realizing ! P logic and ! G logic, and comprises two NAND gates and one OR gate, wherein two inputs of one NAND gate are respectively ai and bi, an output thereof is ! Gi, and ! Gi is output to one input of the other NAND gate; two inputs of the OR gate are respectively ai and bi, and an output thereof is the other input of the other NAND gate; and two inputs of the other NAND gate are respectively the output of one NAND gate and an output of the OR gate, and an output thereof is ! Pi, i representing an ith bit in a multi-bit adder.

The invention provides an integrated circuit and an operation method thereof. A high order searched in a three-dimensional NAND gate memory is used to receive a search applied to select lines and word lines of a non-volatile three-dimensional memory array. The search word is presented in the three-dimensional NAND memory along a bit line direction of the three-dimensional NAND memory. Each character of the character includes a number of digits, each number matching a respective layer of the three-dimensional NAND memory. Each number may be used to represent one of a plurality of levels according to the selected coding. Selectively, characters of various lengths are accommodated by sequential and / or parallel operation of one or more three-dimensional NAND memories.

A memory cell, an NAND string, a memory cell array, and a data access method. The memory cell comprises a first transistor and a second transistor, the first transistor comprises a first electrode, a second electrode, and two independent gates, i.e., a first gate and a second gate; the second transistor comprises a first electrode, a second electrode, and a gate; the first gate of the first transistor is used as a first word line connecting end; the gate of the second transistor is used as a second word line connecting end; and the second gate of the first transistor is connected to the first electrode of the second transistor.

The present invention discloses a chip protection circuit for preventing laser light attack and a corresponding chip. The chip protection circuit includes a multi-bit lock register, a logic gate, an inverter, a multiplexer, a key register, and a complementary check register; wherein the output end of the lock register is linked to the input end of the logic gate, and the output end of the logic gate is respectively connected to the input end of the first multiplexer and the input end of the second multiplexer; the external signal is respectively connected to the input end of the first multiplexer and the input end of the NOT gate; the output end of the first multiplexer is connected to the input end of the key register, and the output end of the key register is connected to the input end of the first multiplexer; the output end of the NOT gate is connected to the input end of the second multiplexer, and the output end of the second multiplexer is connected to the input end of the complementary check register; the output end of the complementary check register is connected to the input end of the second multiplexer.

The invention discloses a time delay circuit which comprises a first selector, a plurality of series-connected time delay units, an NAND gate, a second selector and a plurality of phase inverters, a first data input end of the first selector is connected with a first enable signal, and the first enable signal serves as an input signal of the time delay circuit in an input mode; the delay units are connected with the output end of the first selector, the first input end of the NAND gate is connected to the output end of the last-stage delay unit, the second input end of the NAND gate is connected with a second enable signal, the second enable signal is used for controlling the working mode of the delay circuit, and the selection control end of the second selector is connected to the output end of the NAND gate. The first data input end and the second data input end are connected through the first phase inverter, the output end is connected to the second data input end of the first selector through the second phase inverter, and the third phase inverter is connected to the output end of the second selector and used for outputting an output signal of the time delay circuit. The method is used for testing register establishment time and retention time.

The application claims a kind of fast level shift circuit for power management chip, including level shift core circuit and low delay path detection circuit.The application uses resistance R1 to make PMOS tube M5-M6 drain voltage can quickly from V DDH Drop to V SSH , improve circuit transient characteristics, shorten voltage conversion delay and reduce switching loss;Adopt PMOS tube M13-M14 to constitute pull-up MOS tube, make PMOS tube M5-M6 drain voltage quickly rise, reduce switching loss;Adopt gate, source and substrate short NMOS tube M7-M8 to realize diode, make PMOS tube M5-M6 drain low voltage not less than V SSH -0.7, improve circuit reliability, adopt inverter to realize delay chain technology, make corresponding NAND gate output a lower pulse signal, and then circuit output a high voltage signal consistent with input signal change, so as to realize high-performance fast level shift circuit.

The invention discloses a high-speed clock duty ratio stabilizing circuit, and relates to the field of integrated circuits. Comprising an integrator, a voltage-controlled delay circuit connected with the integrator, a Schmidt trigger circuit connected with a voltage-controlled delay unit, a second phase inverter connected with the Schmidt trigger circuit, a second NAND gate connected with the second phase inverter, a clock signal output end connected with the second NAND gate, and a clock signal input end. The circuit comprises a clock signal input end, a first phase inverter connected with the clock signal input end, a first NAND gate connected with the first phase inverter, a third NAND gate connected with the first phase inverter, a current mirror module connected with a voltage-controlled delay circuit, a current source connected with the current mirror module, and a common-mode signal input end, the clock signal output end is connected among the first phase inverter, the integrator and the third phase inverter, the third NAND gate is connected to the second NAND gate, the first NAND gate is connected to the voltage-controlled delay circuit, and the common-mode signal input end is connected to the integrator. The structure is suitable for high-speed clock input, and stable clock signals with the duty ratio of 50% are generated.

The utility model belongs to the technical field of optical storage inverters, and particularly discloses a network side relay control circuit of an uninterruptible power supply upgrading program of an optical storage inverter. Comprising a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, triodes, triodes, triodes, a first network side relay, a second network side relay and the like. According to the utility model, through the redundant circuit design of the MCU chip, the DSP chip and the ARM chip, when one chip is used for program upgrading, the relay can be kept in a continuous closed state as long as the other two chips are ensured to output normal drive, so that the bypass output is ensured to be always electrified.

The application discloses a system for verifying the time precision of a TB time stamp recording device and a method thereof, which comprises a GPS antenna, a GPS receiver module, a microprocessor and a NAND gate; the GPS antenna is used for receiving signals transmitted by GPS satellites and transmitting the signals to the GPS receiver module; the GPS receiver module is used for outputting time service second pulses to the microprocessor and the NAND gate respectively after receiving the signals transmitted by the GPS antenna; the microprocessor is used for outputting a pulse control signal to the NAND gate according to a time information control instruction after receiving the time service second pulses transmitted by the GPS receiver module; and the NAND gate is used for outputting corresponding second pulses to the TB time stamp recording device for recording according to the received pulse control signal. The application is used for solving the technical problem that the precision of the TB time stamp recording device cannot be verified, so as to achieve the purpose of ensuring the precision of the TB time stamp recording device.

The utility model discloses a dead zone insertion circuit based on a gate-level circuit, and belongs to the technical field of gate-level circuits. A first input end of a first NAND gate is connected with a first complementary signal; the input end of the first NOT gate is connected with the first input end of the first NAND gate; the first resistance-capacitance circuit is connected with the output end of the first NOT gate through a first resistor; the first input end of the second NAND gate is connected with a second complementary signal, and the second input end of the second NAND gate is connected with the first resistance-capacitance circuit through a second resistor; the input end of the second NOT gate is connected with the first input end of the second NAND gate; the second resistance-capacitance circuit is connected with the output end of the second NOT gate through a third resistor; the first end of the fourth resistor is connected with the second input end of the first NAND gate, and the second end of the fourth resistor is connected between the third resistor and the second resistance-capacitance circuit. The beneficial effects are that through cooperation of the NAND gate, the NOT gate and the resistance-capacitance circuit, the circuit structure is simple, the safety and reliability of circuit work are improved, and the cost is low.

The invention relates to the field of D-type edge triggers, in particular to a D-type edge trigger with a power-on initial state following CLK, which comprises a POR module, an initial state control module, a clock control module and a trigger module, the trigger module comprises a front loop latch unit and a rear loop latch unit, the POR module controls a power-on signal enH to turn over, and the initial state control module controls the clock control module to turn over. The trigger is controlled to be powered on and reset, the clock control module outputs an inverted clock signal clka and an in-phase clock signal clkb to the initial state control module, the high level and the low level of the control signal rst and the control signal perst are controlled, and it is ensured that the control signal rst and the clock signal CLK are in the same phase; on-off of transmission gates of the front loop latch unit and the rear loop latch unit is controlled, and a NAND gate is utilized to ensure that a control signal Q and a clock signal CLK in an initial state are in the same phase.

The invention provides an OSC circuit, an integrated OSC circuit and an integrated circuit chip, and the OSC circuit comprises an annular oscillation circuit which comprises an NAND gate, a frequency control module and a phase inverter module, the first input end of the NAND gate is a control signal input end, the second input end of the NAND gate is electrically connected with the output end of the phase inverter module, and the frequency control module is electrically connected with the output end of the phase inverter module; the output end of the NAND gate is electrically connected with the input end of the frequency control module; wherein when the control signal input end receives a first control signal, the annular oscillation circuit is used for outputting a first clock signal, when the control signal input end receives a second control signal, the annular oscillation circuit is used for stopping outputting the first clock signal, and the frequency control module is used for controlling the frequency of the first clock signal. It can be understood that if necessary, the power supply circuit can keep the power-on state and continuously output the power supply, and a user can input different control signals to the control signal input end to quickly control the ring oscillation circuit to be switched on or switched off.

The disclosed embodiment discloses a layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory, wherein the layout of the delay circuit unit includes a plurality of layout units, the layout units are used to form a NAND gate circuit, and the layout units are arranged in an array; wherein, in the first row of the array, a plurality of layout units conforming to a first layout mode are sequentially arranged; and in the second row of the array, a plurality of layout units conforming to a second layout mode are sequentially arranged; wherein, the first layout mode is different from the second layout mode, and the first layout mode and the second layout mode make the first row and the second row present a central symmetrical structure. In this way, it is not only conducive to achieving the consistency of delay between signals of different phases, but also the overall layout of the delay circuit unit is compact, and the layout area can be saved.

The present invention provides an SRAM word line voltage regulation circuit, comprising: a first n-input NAND gate, whose input receives a row decoding signal from a word line decoding circuit; a first PMOS transistor, whose source is connected to a power supply voltage, and whose output signal from the first n-input NAND gate passes through two stages of inverters and is then input into the gate of the first PMOS transistor; a second n-input NAND gate, whose input receives the row decoding signal; a NOR gate, whose input receives the output signal of the second n-input NAND gate and a read / write control signal; and a second PMOS transistor, whose source and drain are short-circuited and connected to the drain of the first PMOS transistor, and which outputs the regulation signal from the word line decoding circuit. The output signal from the NOR gate passes through a single stage of inverters and is then input into the gate of the second PMOS transistor. The present invention can control the SRAM word line voltage without requiring an external control signal, reducing the circuit's control difficulty. Furthermore, by using the second PMOS transistor for charging, capacitors can be eliminated, thereby reducing occupied area.