171 results about "NAND gate" patented technology

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention discloses an adaptive mode switching circuit of a BUCK converter for COT control. The adaptive mode switching circuit comprises a conduction time generation circuit, an OR gate, phase inverters INV1, INV2 and INV3, an NAND gate, an AND gate, RS triggers RS1 and RS2, transistors Mon, MN1, MN2 and MN3, a falling edge delay circuit, a rising edge delay circuit and a zero cross detection circuit. According to the invention, a conduction signal and a zero-cross detection signal are fed back to the conduction time generation circuit, the states of two paths of control signals in a DCM mode and a CCM mode are adaptively adjusted, logic operation is carried out on the control signals through an OR gate, and the conduction time of an upper tube is adaptively adjusted. When the DCM mode is switched to the CCM mode, the CCM control signal serves as a conduction time control signal, and the conduction time of an upper tube is increased; and when the CCM mode is switched to the DCM mode, the DCM control signal is used as a conduction time control signal, and the conduction time of the upper tube is reduced.

Control circuit (100) which outputs a first signal to discharge charges accumulated in a source line (SL) and a bit line (BL) according to the activation of a word line (WL) and outputs a second signal to put the source line and the bit line into a potential-free state until the start of writing or reading, with respect to a memory cell which has the source line (SL), the bit line (BL), a transistor (Tr5) which is provided between the source line (SL) and the bit line (BL) and is switched on and off by a potential of the word line (WL), and a storage element (R1) connected in series with the transistor (TR5), wherein the control circuit (100) has a first transistor (Tr3) connected to the source line (SL) and a second transistor (Tr4) connected to the bit line (BL), and the first transistor (Tr3) includes a first gate terminal and the second transistor (Tr4) includes a second gate terminal, wherein the first gate terminal is connected to a first NAND gate (69) and the second gate terminal is connected to a second NAND gate (70), and wherein both the source line (SL) and the bit line (BL) are short-circuited to a ground potential at a first time point in response to the first signal and transition from their respective first potential-free states to their respective non-potential-free states, and transition at a second time point in response to the second signal to their respective second potential-free states.

The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines and a plurality of NAND strings, which are coupled to a plurality of sense nodes. Control circuitry is configured to perform a sensing operation on the memory cells of a selected word line of the plurality of word lines. During the sensing operation, the control circuitry determines a data state to be sensed and then sets a sense time as a function of the data state to be sensed. The control circuitry then applies a reference voltage to the selected word line and, for the sense time, discharges a selected sense node of the plurality of sense nodes through a selected NAND string of the plurality of NAND strings. The selected NAND string includes a selected memory cell of the plurality of memory cells.

This invention discloses a 4-2 approximation compressor based on memristors, a control method, an apparatus, and applications. It approximates and compresses four 1-bit numbers X1, X2, X3, and X4 using two identical memristor-based majority gate circuits. The two majority gate circuits respectively implement traditional majority gate logic and a novel majority gate logic including inversion logic. The first majority gate circuit implements the traditional majority gate logic M(X1, X3, X4) to obtain the carry result of the 4-2 approximation compressor. The second majority gate circuit implements the novel majority gate logic including inversion logic to obtain the pseudo-sum result of the 4-2 approximation compressor. This invention does not rely on the cascading of a large number of basic logic units such as NAND gates and NOR gates, has a shallow logic depth, and can achieve a 4-2 compressor with good error performance with low circuit complexity, high operation speed, and low power consumption.

The application belongs to the field of chips, and provides a zero-temperature duty cycle adjustable oscillation circuit. The circuit comprises a first NAND gate, a first input end of the first NAND gate is connected with an output end of a first NOT gate, an output end is connected with a gate of a first NMOS tube, a drain of the first NMOS tube is connected with a gate of a second NMOS tube, a drain of the second NMOS tube is connected with an input end of a second NOT gate, an output end of the second NOT gate is connected with an input end of a third NOT gate, an output end of the third NOT gate is connected with a first input end of a second NAND gate, an output end of the second NAND gate is connected with a gate of a third NMOS tube, a drain of the third NMOS tube is connected with a gate of a fourth NMOS tube, a drain of the fourth NMOS tube is connected with an input end of a fourth NOT gate, an output end of the fourth NOT gate is connected with an input end of the first NOT gate, and the drains of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are respectively connected with a current source and a grounding capacitor. The first input end and the second input end of the first NAND gate and the second NAND gate are connected with a first input end and a second input end of a logic control chip, a first output end and a second output end of the logic control chip are respectively connected with a second input end of the first NAND gate and the second NAND gate, and the logic control chip has a reset end. The application can realize that the output frequency does not change with temperature and power voltage without increasing the chip area, and the back lock mechanism is introduced to eliminate the indefinite state in the circuit, which may cause the output frequency change problem.

The invention provides a rising edge trigger and a low noise amplifier. The rising edge trigger comprises a first phase inverter, a second phase inverter, a capacitor, a Schmitt trigger, a phase inverter circuit, an NAND gate and a third phase inverter, the input end of the first phase inverter is used for accessing an enable signal for controlling the low-noise amplifier to work; the power supply end of the second phase inverter is used for being connected to the current outflow end of a current source for providing reference current for the low-noise amplifier; the first input end of the NAND gate is connected to the output end of the inverter circuit, and the second input end of the NAND gate is connected to the output end of the first inverter; the input end of the third phase inverter is connected to the output end of the NAND gate, and the output end of the third phase inverter is used for outputting a delay control signal. According to the rising edge trigger, the area of the capacitor can be reduced according to the magnitude of the current of the accessed current source for providing the reference current for the low-noise amplifier, so that the occupied area of the rising edge trigger is reduced.

The utility model relates to a battery charging and discharging current switching control circuit. A charging control signal is respectively connected with the input ends of a first NOT gate and a first NAND gate; the output end of the first NOT gate is respectively connected with the input ends of the second NAND gate and the third NAND gate; a discharge control signal is respectively connected with the input end of the second NOT gate, the other input end of the second NAND gate and the other input end of the third NAND gate; the output end of the second NOT gate is connected with the other input end of the first NAND gate; the output end of the first NAND gate is connected with the base electrode of the first triode through the first resistor; the collector electrode of the first triode is connected with the charging power module and the emitter electrode is connected with the anode of the first diode. The output end of the second NAND gate is connected with the base electrode of a second triode through a second resistor; the collector of the second triode is connected with the discharge power module; the cathodes of the first diode and the second diode are grounded. According to the utility model, instantaneous switching of charging and discharging is ensured.

A memory cell, an NAND string, a memory cell array, and a data access method. The memory cell comprises a first transistor and a second transistor, the first transistor comprises a first electrode, a second electrode, and two independent gates, i.e., a first gate and a second gate; the second transistor comprises a first electrode, a second electrode, and a gate; the first gate of the first transistor is used as a first word line connecting end; the gate of the second transistor is used as a second word line connecting end; and the second gate of the first transistor is connected to the first electrode of the second transistor.

The invention discloses a time delay circuit which comprises a first selector, a plurality of series-connected time delay units, an NAND gate, a second selector and a plurality of phase inverters, a first data input end of the first selector is connected with a first enable signal, and the first enable signal serves as an input signal of the time delay circuit in an input mode; the delay units are connected with the output end of the first selector, the first input end of the NAND gate is connected to the output end of the last-stage delay unit, the second input end of the NAND gate is connected with a second enable signal, the second enable signal is used for controlling the working mode of the delay circuit, and the selection control end of the second selector is connected to the output end of the NAND gate. The first data input end and the second data input end are connected through the first phase inverter, the output end is connected to the second data input end of the first selector through the second phase inverter, and the third phase inverter is connected to the output end of the second selector and used for outputting an output signal of the time delay circuit. The method is used for testing register establishment time and retention time.

The application claims a kind of fast level shift circuit for power management chip, including level shift core circuit and low delay path detection circuit.The application uses resistance R1 to make PMOS tube M5-M6 drain voltage can quickly from V DDH Drop to V SSH , improve circuit transient characteristics, shorten voltage conversion delay and reduce switching loss;Adopt PMOS tube M13-M14 to constitute pull-up MOS tube, make PMOS tube M5-M6 drain voltage quickly rise, reduce switching loss;Adopt gate, source and substrate short NMOS tube M7-M8 to realize diode, make PMOS tube M5-M6 drain low voltage not less than V SSH -0.7, improve circuit reliability, adopt inverter to realize delay chain technology, make corresponding NAND gate output a lower pulse signal, and then circuit output a high voltage signal consistent with input signal change, so as to realize high-performance fast level shift circuit.

The utility model belongs to the technical field of optical storage inverters, and particularly discloses a network side relay control circuit of an uninterruptible power supply upgrading program of an optical storage inverter. Comprising a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate, a seventh NAND gate, an eighth NAND gate, triodes, triodes, triodes, a first network side relay, a second network side relay and the like. According to the utility model, through the redundant circuit design of the MCU chip, the DSP chip and the ARM chip, when one chip is used for program upgrading, the relay can be kept in a continuous closed state as long as the other two chips are ensured to output normal drive, so that the bypass output is ensured to be always electrified.

The application discloses a system for verifying the time precision of a TB time stamp recording device and a method thereof, which comprises a GPS antenna, a GPS receiver module, a microprocessor and a NAND gate; the GPS antenna is used for receiving signals transmitted by GPS satellites and transmitting the signals to the GPS receiver module; the GPS receiver module is used for outputting time service second pulses to the microprocessor and the NAND gate respectively after receiving the signals transmitted by the GPS antenna; the microprocessor is used for outputting a pulse control signal to the NAND gate according to a time information control instruction after receiving the time service second pulses transmitted by the GPS receiver module; and the NAND gate is used for outputting corresponding second pulses to the TB time stamp recording device for recording according to the received pulse control signal. The application is used for solving the technical problem that the precision of the TB time stamp recording device cannot be verified, so as to achieve the purpose of ensuring the precision of the TB time stamp recording device.

The utility model discloses a dead zone insertion circuit based on a gate-level circuit, and belongs to the technical field of gate-level circuits. A first input end of a first NAND gate is connected with a first complementary signal; the input end of the first NOT gate is connected with the first input end of the first NAND gate; the first resistance-capacitance circuit is connected with the output end of the first NOT gate through a first resistor; the first input end of the second NAND gate is connected with a second complementary signal, and the second input end of the second NAND gate is connected with the first resistance-capacitance circuit through a second resistor; the input end of the second NOT gate is connected with the first input end of the second NAND gate; the second resistance-capacitance circuit is connected with the output end of the second NOT gate through a third resistor; the first end of the fourth resistor is connected with the second input end of the first NAND gate, and the second end of the fourth resistor is connected between the third resistor and the second resistance-capacitance circuit. The beneficial effects are that through cooperation of the NAND gate, the NOT gate and the resistance-capacitance circuit, the circuit structure is simple, the safety and reliability of circuit work are improved, and the cost is low.

The invention relates to the field of D-type edge triggers, in particular to a D-type edge trigger with a power-on initial state following CLK, which comprises a POR module, an initial state control module, a clock control module and a trigger module, the trigger module comprises a front loop latch unit and a rear loop latch unit, the POR module controls a power-on signal enH to turn over, and the initial state control module controls the clock control module to turn over. The trigger is controlled to be powered on and reset, the clock control module outputs an inverted clock signal clka and an in-phase clock signal clkb to the initial state control module, the high level and the low level of the control signal rst and the control signal perst are controlled, and it is ensured that the control signal rst and the clock signal CLK are in the same phase; on-off of transmission gates of the front loop latch unit and the rear loop latch unit is controlled, and a NAND gate is utilized to ensure that a control signal Q and a clock signal CLK in an initial state are in the same phase.

The present invention provides an SRAM word line voltage regulation circuit, comprising: a first n-input NAND gate, whose input receives a row decoding signal from a word line decoding circuit; a first PMOS transistor, whose source is connected to a power supply voltage, and whose output signal from the first n-input NAND gate passes through two stages of inverters and is then input into the gate of the first PMOS transistor; a second n-input NAND gate, whose input receives the row decoding signal; a NOR gate, whose input receives the output signal of the second n-input NAND gate and a read / write control signal; and a second PMOS transistor, whose source and drain are short-circuited and connected to the drain of the first PMOS transistor, and which outputs the regulation signal from the word line decoding circuit. The output signal from the NOR gate passes through a single stage of inverters and is then input into the gate of the second PMOS transistor. The present invention can control the SRAM word line voltage without requiring an external control signal, reducing the circuit's control difficulty. Furthermore, by using the second PMOS transistor for charging, capacitors can be eliminated, thereby reducing occupied area.

Provided are a semiconductor structure for a three-dimensional (3D) memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a substrate, an insulating wall and a stacked structure. The substrate has an array region and a staircase region surrounding the array region. The insulating wall is disposed on the substrate and surrounds the array region and the staircase region. The stacked structure is disposed on the substrate in the array region and the staircase region, and includes a plurality of insulating layers and a plurality of conductive layers alternately stacked. The plurality of insulating layers and the plurality of conductive layers extend conformally onto the insulating wall.

The application discloses an optimization method, a verification method and a storage medium of a circuit containing uncertain signals. The optimization method of the circuit containing uncertain signals includes at least one of tieX and tieZ, and the optimization method includes: mapping a circuit to be subjected to equivalence verification into a simple circuit structure in which only AND gates and NOT gates exist; and performing traversal on the simple structure circuit, and optimizing the AND gate and / or the NOT gate with an input signal being an uncertain signal, so that the input signal of the AND gate and / or the NOT gate is converted from the uncertain signal into a determined signal. The uncertain signals are subjected to normalization processing, and the uncertainty during verification is avoided.

The application discloses a digital comprehensive dynamic voltage comparator based on a disordered voltage calibration technology, comprising a comparison unit composed of two three-input NAND gates and a disordered voltage calibration unit, wherein: the three-input NAND gates are cross-coupled to realize fast comparison of positive input voltage and negative input voltage, the disordered voltage calibration unit detects output voltage of the comparison unit when the input end Vin + is short-circuited and generates a calibration voltage, and the calibration voltage is inputted into the comparison unit after being operated with the input voltage to form a negative feedback to reduce disordered voltage. ‑ The application completely uses digital standard units to realize a dynamic voltage comparator circuit based on cross-coupling of two three-input NAND gates and fusion of the disordered voltage calibration technology, and has the advantages of small area, low power consumption, automatic layout synthesis and small disordered voltage and the like.

The utility model discloses a cable rapid detection device, which belongs to the field of electronic detection, and is characterized in that a cable or a flat cable is rapidly connected through a rapid plugging male head and a rapid plugging female head, so that plugging is convenient; the purpose of detecting the multi-core cable can be achieved through the clock circuit, the pulse generation circuit and the pulse transmission circuit. The device mainly comprises a shell, a detection controller is arranged in the shell, the shell is further provided with a plurality of detection lamps, a power lamp and a test button S1, the detection controller is connected with a connector J1, a connector J2 and a connector J3 through the detection lamps, and the detection controller comprises a clock circuit, a pulse generation circuit and a pulse transmission circuit. The pulse generation circuit comprises a NOR gate U2A and a NOR gate U2B, and an input pin 3 of the NOR gate U2A is connected with the test button S1 through the RC delay circuit. The cable rapid detection device is mainly used for cable rapid detection.

The utility model discloses a capacitance liquid level sensor, which is mounted in a vacuum excrement collector of a sanitation system of a railway passenger vehicle, and comprises a protective shell, an inductive probe, a signal generation module, a signal conditioning module, an MCU (Microprogrammed Control Unit) control module and a power supply module, the signal generation module comprises a voltage follower, an oscillating circuit, a first NOT gate, a second NOT gate and other matched circuits; the oscillating circuit is composed of variable capacitance diodes, the first NOT gate is connected with the oscillating circuit in parallel, and the first NOT gate serves as an amplifier and provides gain for the oscillating circuit; the input end of the second NOT gate is connected with the output end of the first NOT gate, and the output end of the second NOT gate is connected with the inductive probe after passing through other matched circuits; the voltage follower amplifies the voltage of an input signal and outputs a signal with the same amplitude, and the output end of the voltage follower is connected with the oscillating circuit.

A clock generation circuit generates an internal clock signal with a specified pulse width in response to a clock signal and an enable signal. The clock generation circuit includes a latch circuit receiving the clock signal, the enable signal, and an inverse internal clock signal and outputs a first signal, a NAND gate performing a NAND operation on the clock signal and the first signal to output a second signal, a generation circuit outputting the internal clock signal based on the second signal, and a reset circuit connected to the generation circuit and outputting a reset signal after a second time corresponding to the specified pulse width elapses from a point in time when the internal clock signal transitions to a high level. The inverse internal clock signal is generated by inverting and delaying the internal clock signal as much as a first time.

The invention provides a circuit structure for solving single-particle inversion and a method for solving single-particle inversion. The circuit structure comprises three groups of two-input NAND gates and a three-input NOR gate, wherein the three groups of two-input NAND gates are formed by transforming a first six-transistor static memory unit, and the three-input NOR gate is formed by transforming at least one second six-transistor static memory unit. And the outputs of the three groups of NAND gates are connected to the input of the NOR gate so as to realize a majority voting function on the three paths of redundant input signals. According to the embedded majority voter, the circuit connection of the standard static memory unit is reconstructed, and the embedded majority voter is realized by multiplexing the existing resources on the premise of not changing the layout of a bottom transistor. Compared with the prior art, the scheme effectively solves the problems of extra signal propagation delay and chip area overhead caused by the adoption of an external voter, improves the integration level and time sequence performance of the circuit, and is highly compatible with a standard process.

The application provides a rising edge trigger and a low noise amplifier. The rising edge trigger comprises a first inverter, a second inverter, a capacitor, a Schmitt trigger, an inverting circuit, a NAND gate and a third inverter. An input end of the first inverter is used for connecting an enable signal for controlling the working of the low noise amplifier. A power supply end of the second inverter is used for connecting to a current outflow end of a current source for providing a reference current for the low noise amplifier. A first input end of the NAND gate is connected to an output end of the inverting circuit, and a second input end of the NAND gate is connected to an output end of the first inverter. An input end of the third inverter is connected to an output end of the NAND gate, and an output end of the third inverter is used for outputting a delay control signal. The rising edge trigger can reduce the area of the capacitor by the current size of the current source for providing the reference current for the low noise amplifier, so as to reduce the occupied area of the rising edge trigger.

A gate drive circuit, a display substrate, and a display apparatus. The gate drive circuit comprises a shift register circuit (100) arranged on a silicon base (101), and the shift register circuit (100) comprises a plurality of transistor groups sequentially arranged in a first direction, wherein at least one transistor group comprises a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a second direction, the P-type transistor at least comprises a P-type active region, the N-type transistor at least comprises an N-type active region, a gap region (50) is provided between the P-type active region and the N-type active region in the second direction, and the gap region (50) has a gap center line (OC), the first direction intersecting the second direction; and the plurality of transistor groups form at least one transmission gate, at least one NAND gate and at least one inverter, and the gap center lines (OC) of the transistor groups in the at least one transmission gate, the at least one NAND gate and the at least one inverter are in the same straight line extending in the first direction.

The application discloses an in-memory multiplication and accumulation computing device and method based on SRAM, and the device comprises a first SRAM bit cell, a second SRAM bit cell, a first transmission gate circuit and a second transmission gate circuit, wherein the first transmission gate circuit comprises a first NMOS tube, a first PMOS tube and a first input port; the second transmission gate circuit comprises a second NMOS tube, a second PMOS tube and a second input port; a third MOS tube and a fourth MOS tube are arranged between the BLL bit line and the first and second transmission gate circuits; a fifth MOS tube and a sixth MOS tube are arranged between the BLR bit line and the first and second transmission gate circuits; a NAND gate is arranged between the BLR bit line and the carry output port, or the input end of the NAND gate is connected with the output end of the NAND gate and the BLL bit line. By adopting the technical scheme, the multiplication and accumulation results of two groups of inputs and weights can be directly outputted, the first-stage half-adder circuit in the multiplication unit and the addition tree is not needed, the use of transistors is saved, the area and power consumption of the addition tree are reduced, and the energy efficiency of the overall CIM macro is improved.

The application discloses a delay circuit, which comprises a first selector, a plurality of serially connected delay units, a NAND gate, a second selector and a plurality of inverters, wherein a first data input end of the first selector is connected with a first enable signal, the first enable signal is used as an input signal of the delay circuit in an input mode, the delay units are connected with an output end of the first selector, a first input end of the NAND gate is connected with an output end of the last stage delay unit, a second input end is connected with a second enable signal, the second enable signal is used for controlling a working mode of the delay circuit, a selection control end of the second selector is connected with an output end of the NAND gate, a first data input end and a second data input end are connected through a first inverter, an output end is connected with a second data input end of the first selector through a second inverter, a third inverter is connected with an output end of the second selector and is used for outputting an output signal of the delay circuit. The delay circuit is used for testing register setup time and hold time.

A flip-flop circuit may be used to latch data responsive to an edge of a clock signal. An example flip-flop circuit includes a first latch which latches a value of the data when the clock is at a level, a NAND gate coupled to the output of the first latch and the clock signal, and a second latch which is set to provide a high logical output based on the output of the NAND gate. In this way, the second latch is set on a next rising edge of the clock signal. The flip-flop circuit may be faster and more consistent than a conventional flip-flop. In an example application, the flip-flop circuit may be used as part of a synchronizer circuit in a memory device for external write leveling.

The invention discloses a power-on reset circuit with a self-detection backlock function. The power-on reset circuit comprises a first detection unit, a second detection unit and a logic comparison unit, a first RC charging and discharging unit of a first detection unit is used for power supply voltage detection and pre-charging, and a first back lock turn-off unit of the first detection unit is used for back lock turn-off and signal locking, so that first detection voltage is obtained; power supply voltage detection and pre-charging are carried out through a second RC charging and discharging unit of a second detection unit, and back lock turn-off and signal locking are carried out through a second back lock turn-off unit of the second detection unit, so that second detection voltage is obtained; outputting a corresponding reset signal through an NAND gate of the logic comparison unit according to the first detection voltage and the second detection voltage; therefore, power consumption is greatly reduced, and the whole circuit area is reduced.