104 results about "NAND gate" patented technology

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention discloses an adaptive mode switching circuit of a BUCK converter for COT control. The adaptive mode switching circuit comprises a conduction time generation circuit, an OR gate, phase inverters INV1, INV2 and INV3, an NAND gate, an AND gate, RS triggers RS1 and RS2, transistors Mon, MN1, MN2 and MN3, a falling edge delay circuit, a rising edge delay circuit and a zero cross detection circuit. According to the invention, a conduction signal and a zero-cross detection signal are fed back to the conduction time generation circuit, the states of two paths of control signals in a DCM mode and a CCM mode are adaptively adjusted, logic operation is carried out on the control signals through an OR gate, and the conduction time of an upper tube is adaptively adjusted. When the DCM mode is switched to the CCM mode, the CCM control signal serves as a conduction time control signal, and the conduction time of an upper tube is increased; and when the CCM mode is switched to the DCM mode, the DCM control signal is used as a conduction time control signal, and the conduction time of the upper tube is reduced.

Control circuit (100) which outputs a first signal to discharge charges accumulated in a source line (SL) and a bit line (BL) according to the activation of a word line (WL) and outputs a second signal to put the source line and the bit line into a potential-free state until the start of writing or reading, with respect to a memory cell which has the source line (SL), the bit line (BL), a transistor (Tr5) which is provided between the source line (SL) and the bit line (BL) and is switched on and off by a potential of the word line (WL), and a storage element (R1) connected in series with the transistor (TR5), wherein the control circuit (100) has a first transistor (Tr3) connected to the source line (SL) and a second transistor (Tr4) connected to the bit line (BL), and the first transistor (Tr3) includes a first gate terminal and the second transistor (Tr4) includes a second gate terminal, wherein the first gate terminal is connected to a first NAND gate (69) and the second gate terminal is connected to a second NAND gate (70), and wherein both the source line (SL) and the bit line (BL) are short-circuited to a ground potential at a first time point in response to the first signal and transition from their respective first potential-free states to their respective non-potential-free states, and transition at a second time point in response to the second signal to their respective second potential-free states.

The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines and a plurality of NAND strings, which are coupled to a plurality of sense nodes. Control circuitry is configured to perform a sensing operation on the memory cells of a selected word line of the plurality of word lines. During the sensing operation, the control circuitry determines a data state to be sensed and then sets a sense time as a function of the data state to be sensed. The control circuitry then applies a reference voltage to the selected word line and, for the sense time, discharges a selected sense node of the plurality of sense nodes through a selected NAND string of the plurality of NAND strings. The selected NAND string includes a selected memory cell of the plurality of memory cells.

This invention discloses a 4-2 approximation compressor based on memristors, a control method, an apparatus, and applications. It approximates and compresses four 1-bit numbers X1, X2, X3, and X4 using two identical memristor-based majority gate circuits. The two majority gate circuits respectively implement traditional majority gate logic and a novel majority gate logic including inversion logic. The first majority gate circuit implements the traditional majority gate logic M(X1, X3, X4) to obtain the carry result of the 4-2 approximation compressor. The second majority gate circuit implements the novel majority gate logic including inversion logic to obtain the pseudo-sum result of the 4-2 approximation compressor. This invention does not rely on the cascading of a large number of basic logic units such as NAND gates and NOR gates, has a shallow logic depth, and can achieve a 4-2 compressor with good error performance with low circuit complexity, high operation speed, and low power consumption.

The invention provides a rising edge trigger and a low noise amplifier. The rising edge trigger comprises a first phase inverter, a second phase inverter, a capacitor, a Schmitt trigger, a phase inverter circuit, an NAND gate and a third phase inverter, the input end of the first phase inverter is used for accessing an enable signal for controlling the low-noise amplifier to work; the power supply end of the second phase inverter is used for being connected to the current outflow end of a current source for providing reference current for the low-noise amplifier; the first input end of the NAND gate is connected to the output end of the inverter circuit, and the second input end of the NAND gate is connected to the output end of the first inverter; the input end of the third phase inverter is connected to the output end of the NAND gate, and the output end of the third phase inverter is used for outputting a delay control signal. According to the rising edge trigger, the area of the capacitor can be reduced according to the magnitude of the current of the accessed current source for providing the reference current for the low-noise amplifier, so that the occupied area of the rising edge trigger is reduced.

The utility model relates to a battery charging and discharging current switching control circuit. A charging control signal is respectively connected with the input ends of a first NOT gate and a first NAND gate; the output end of the first NOT gate is respectively connected with the input ends of the second NAND gate and the third NAND gate; a discharge control signal is respectively connected with the input end of the second NOT gate, the other input end of the second NAND gate and the other input end of the third NAND gate; the output end of the second NOT gate is connected with the other input end of the first NAND gate; the output end of the first NAND gate is connected with the base electrode of the first triode through the first resistor; the collector electrode of the first triode is connected with the charging power module and the emitter electrode is connected with the anode of the first diode. The output end of the second NAND gate is connected with the base electrode of a second triode through a second resistor; the collector of the second triode is connected with the discharge power module; the cathodes of the first diode and the second diode are grounded. According to the utility model, instantaneous switching of charging and discharging is ensured.

A memory cell, an NAND string, a memory cell array, and a data access method. The memory cell comprises a first transistor and a second transistor, the first transistor comprises a first electrode, a second electrode, and two independent gates, i.e., a first gate and a second gate; the second transistor comprises a first electrode, a second electrode, and a gate; the first gate of the first transistor is used as a first word line connecting end; the gate of the second transistor is used as a second word line connecting end; and the second gate of the first transistor is connected to the first electrode of the second transistor.

The invention discloses a time delay circuit which comprises a first selector, a plurality of series-connected time delay units, an NAND gate, a second selector and a plurality of phase inverters, a first data input end of the first selector is connected with a first enable signal, and the first enable signal serves as an input signal of the time delay circuit in an input mode; the delay units are connected with the output end of the first selector, the first input end of the NAND gate is connected to the output end of the last-stage delay unit, the second input end of the NAND gate is connected with a second enable signal, the second enable signal is used for controlling the working mode of the delay circuit, and the selection control end of the second selector is connected to the output end of the NAND gate. The first data input end and the second data input end are connected through the first phase inverter, the output end is connected to the second data input end of the first selector through the second phase inverter, and the third phase inverter is connected to the output end of the second selector and used for outputting an output signal of the time delay circuit. The method is used for testing register establishment time and retention time.

The application claims a kind of fast level shift circuit for power management chip, including level shift core circuit and low delay path detection circuit.The application uses resistance R1 to make PMOS tube M5-M6 drain voltage can quickly from V DDH Drop to V SSH , improve circuit transient characteristics, shorten voltage conversion delay and reduce switching loss;Adopt PMOS tube M13-M14 to constitute pull-up MOS tube, make PMOS tube M5-M6 drain voltage quickly rise, reduce switching loss;Adopt gate, source and substrate short NMOS tube M7-M8 to realize diode, make PMOS tube M5-M6 drain low voltage not less than V SSH -0.7, improve circuit reliability, adopt inverter to realize delay chain technology, make corresponding NAND gate output a lower pulse signal, and then circuit output a high voltage signal consistent with input signal change, so as to realize high-performance fast level shift circuit.

The application discloses a system for verifying the time precision of a TB time stamp recording device and a method thereof, which comprises a GPS antenna, a GPS receiver module, a microprocessor and a NAND gate; the GPS antenna is used for receiving signals transmitted by GPS satellites and transmitting the signals to the GPS receiver module; the GPS receiver module is used for outputting time service second pulses to the microprocessor and the NAND gate respectively after receiving the signals transmitted by the GPS antenna; the microprocessor is used for outputting a pulse control signal to the NAND gate according to a time information control instruction after receiving the time service second pulses transmitted by the GPS receiver module; and the NAND gate is used for outputting corresponding second pulses to the TB time stamp recording device for recording according to the received pulse control signal. The application is used for solving the technical problem that the precision of the TB time stamp recording device cannot be verified, so as to achieve the purpose of ensuring the precision of the TB time stamp recording device.

The utility model discloses a dead zone insertion circuit based on a gate-level circuit, and belongs to the technical field of gate-level circuits. A first input end of a first NAND gate is connected with a first complementary signal; the input end of the first NOT gate is connected with the first input end of the first NAND gate; the first resistance-capacitance circuit is connected with the output end of the first NOT gate through a first resistor; the first input end of the second NAND gate is connected with a second complementary signal, and the second input end of the second NAND gate is connected with the first resistance-capacitance circuit through a second resistor; the input end of the second NOT gate is connected with the first input end of the second NAND gate; the second resistance-capacitance circuit is connected with the output end of the second NOT gate through a third resistor; the first end of the fourth resistor is connected with the second input end of the first NAND gate, and the second end of the fourth resistor is connected between the third resistor and the second resistance-capacitance circuit. The beneficial effects are that through cooperation of the NAND gate, the NOT gate and the resistance-capacitance circuit, the circuit structure is simple, the safety and reliability of circuit work are improved, and the cost is low.

The invention relates to the field of D-type edge triggers, in particular to a D-type edge trigger with a power-on initial state following CLK, which comprises a POR module, an initial state control module, a clock control module and a trigger module, the trigger module comprises a front loop latch unit and a rear loop latch unit, the POR module controls a power-on signal enH to turn over, and the initial state control module controls the clock control module to turn over. The trigger is controlled to be powered on and reset, the clock control module outputs an inverted clock signal clka and an in-phase clock signal clkb to the initial state control module, the high level and the low level of the control signal rst and the control signal perst are controlled, and it is ensured that the control signal rst and the clock signal CLK are in the same phase; on-off of transmission gates of the front loop latch unit and the rear loop latch unit is controlled, and a NAND gate is utilized to ensure that a control signal Q and a clock signal CLK in an initial state are in the same phase.

The application discloses an optimization method, a verification method and a storage medium of a circuit containing uncertain signals. The optimization method of the circuit containing uncertain signals includes at least one of tieX and tieZ, and the optimization method includes: mapping a circuit to be subjected to equivalence verification into a simple circuit structure in which only AND gates and NOT gates exist; and performing traversal on the simple structure circuit, and optimizing the AND gate and / or the NOT gate with an input signal being an uncertain signal, so that the input signal of the AND gate and / or the NOT gate is converted from the uncertain signal into a determined signal. The uncertain signals are subjected to normalization processing, and the uncertainty during verification is avoided.

The application discloses a digital comprehensive dynamic voltage comparator based on a disordered voltage calibration technology, comprising a comparison unit composed of two three-input NAND gates and a disordered voltage calibration unit, wherein: the three-input NAND gates are cross-coupled to realize fast comparison of positive input voltage and negative input voltage, the disordered voltage calibration unit detects output voltage of the comparison unit when the input end Vin + is short-circuited and generates a calibration voltage, and the calibration voltage is inputted into the comparison unit after being operated with the input voltage to form a negative feedback to reduce disordered voltage. ‑ The application completely uses digital standard units to realize a dynamic voltage comparator circuit based on cross-coupling of two three-input NAND gates and fusion of the disordered voltage calibration technology, and has the advantages of small area, low power consumption, automatic layout synthesis and small disordered voltage and the like.

The utility model discloses a capacitance liquid level sensor, which is mounted in a vacuum excrement collector of a sanitation system of a railway passenger vehicle, and comprises a protective shell, an inductive probe, a signal generation module, a signal conditioning module, an MCU (Microprogrammed Control Unit) control module and a power supply module, the signal generation module comprises a voltage follower, an oscillating circuit, a first NOT gate, a second NOT gate and other matched circuits; the oscillating circuit is composed of variable capacitance diodes, the first NOT gate is connected with the oscillating circuit in parallel, and the first NOT gate serves as an amplifier and provides gain for the oscillating circuit; the input end of the second NOT gate is connected with the output end of the first NOT gate, and the output end of the second NOT gate is connected with the inductive probe after passing through other matched circuits; the voltage follower amplifies the voltage of an input signal and outputs a signal with the same amplitude, and the output end of the voltage follower is connected with the oscillating circuit.

A clock generation circuit generates an internal clock signal with a specified pulse width in response to a clock signal and an enable signal. The clock generation circuit includes a latch circuit receiving the clock signal, the enable signal, and an inverse internal clock signal and outputs a first signal, a NAND gate performing a NAND operation on the clock signal and the first signal to output a second signal, a generation circuit outputting the internal clock signal based on the second signal, and a reset circuit connected to the generation circuit and outputting a reset signal after a second time corresponding to the specified pulse width elapses from a point in time when the internal clock signal transitions to a high level. The inverse internal clock signal is generated by inverting and delaying the internal clock signal as much as a first time.

The application provides a rising edge trigger and a low noise amplifier. The rising edge trigger comprises a first inverter, a second inverter, a capacitor, a Schmitt trigger, an inverting circuit, a NAND gate and a third inverter. An input end of the first inverter is used for connecting an enable signal for controlling the working of the low noise amplifier. A power supply end of the second inverter is used for connecting to a current outflow end of a current source for providing a reference current for the low noise amplifier. A first input end of the NAND gate is connected to an output end of the inverting circuit, and a second input end of the NAND gate is connected to an output end of the first inverter. An input end of the third inverter is connected to an output end of the NAND gate, and an output end of the third inverter is used for outputting a delay control signal. The rising edge trigger can reduce the area of the capacitor by the current size of the current source for providing the reference current for the low noise amplifier, so as to reduce the occupied area of the rising edge trigger.

The application discloses a delay circuit, which comprises a first selector, a plurality of serially connected delay units, a NAND gate, a second selector and a plurality of inverters, wherein a first data input end of the first selector is connected with a first enable signal, the first enable signal is used as an input signal of the delay circuit in an input mode, the delay units are connected with an output end of the first selector, a first input end of the NAND gate is connected with an output end of the last stage delay unit, a second input end is connected with a second enable signal, the second enable signal is used for controlling a working mode of the delay circuit, a selection control end of the second selector is connected with an output end of the NAND gate, a first data input end and a second data input end are connected through a first inverter, an output end is connected with a second data input end of the first selector through a second inverter, a third inverter is connected with an output end of the second selector and is used for outputting an output signal of the delay circuit. The delay circuit is used for testing register setup time and hold time.

A flip-flop circuit may be used to latch data responsive to an edge of a clock signal. An example flip-flop circuit includes a first latch which latches a value of the data when the clock is at a level, a NAND gate coupled to the output of the first latch and the clock signal, and a second latch which is set to provide a high logical output based on the output of the NAND gate. In this way, the second latch is set on a next rising edge of the clock signal. The flip-flop circuit may be faster and more consistent than a conventional flip-flop. In an example application, the flip-flop circuit may be used as part of a synchronizer circuit in a memory device for external write leveling.

The invention discloses a power-on reset circuit with a self-detection backlock function. The power-on reset circuit comprises a first detection unit, a second detection unit and a logic comparison unit, a first RC charging and discharging unit of a first detection unit is used for power supply voltage detection and pre-charging, and a first back lock turn-off unit of the first detection unit is used for back lock turn-off and signal locking, so that first detection voltage is obtained; power supply voltage detection and pre-charging are carried out through a second RC charging and discharging unit of a second detection unit, and back lock turn-off and signal locking are carried out through a second back lock turn-off unit of the second detection unit, so that second detection voltage is obtained; outputting a corresponding reset signal through an NAND gate of the logic comparison unit according to the first detection voltage and the second detection voltage; therefore, power consumption is greatly reduced, and the whole circuit area is reduced.

The invention discloses a PUF (Physical Unclonable Function) circuit based on a ring oscillator and a design method thereof, and belongs to the technical field of integrated circuits, the ring oscillator comprises an NAND gate and n phase inverters, the n phase inverters are connected end to end in series to form a linear structure, a first input end of the NAND gate is used for accessing input voltage, and a second input end of the NAND gate is used for accessing output voltage; the output end of the NAND gate is connected with the input end of the linear structure, the output end of the linear structure is used for providing output voltage, and the output end of the NAND gate and the output end of each phase inverter are grounded through the external capacitor. The ring oscillators with different stages are formed by using the NAND gate and the n phase inverters, the circuits of the ring oscillators are compensated by using the externally-hung capacitors, the output time delay of output voltage can be reduced by setting the proper number of the phase inverters and the capacitance value of the externally-hung capacitors, and the PUFRO operation speed can be accelerated by enabling oscillation signals to enter the multiplexer.

The application relates to a memristor bionic circuit with an associative memory function, which comprises a first memristor M1, a second memristor M2, a first PMOS transistor T1, a second PMOS transistor T2, a first NMOS transistor T3, a first resistor R1, a second resistor R2, a third resistor R3, a first voltage-controlled switch S1, a first NAND gate, a first operational amplifier OP1, a first comparator COMP1, an analog food signal input end Vfood, an analog ring signal input end Vring, a first constant voltage V1, a second constant voltage V2, a first comparison voltage V th . The circuit controls the on / off state of the first PMOS transistor T1, the second PMOS transistor T2 and the first NMOS transistor T3 through the analog food signal input end V food and the analog ring signal input end V ring , adjusts the memristor values of the first memristor M1 and the second memristor M2, and changes the value of an output voltage.

The application discloses a logic acceleration circuit and method of high-speed capacitive SAR ADC. The logic acceleration circuit comprises a two-way selector, a latch, a comparator and an adaptive asynchronous clock generator. The two-way selector is used for selecting the output latch result and the comparator result and is connected to the switch of the control capacitor array analog-digital converter (CDAC). The latch is used for latching the comparator result and is connected to the two-way selector. The comparator is used for comparing the output value of the CDAC with a reference voltage V ref , and outputting the comparison result. The comparison result is output to the two-way selector. After the comparison is completed, a comparison completion flag signal is output to the adaptive asynchronous clock generator. The adaptive asynchronous clock generator comprises a delay module DELAY and a plurality of NAND gates and NOT gates and is used for controlling the successive approximation steps. The application accelerates the logic operation, and each bit operation can be accelerated.

The invention discloses a bit stream random number generator, a random multiplication circuit and a calculation method, and belongs to the technical field of integrated circuits. A reverse signal end of a highest-bit D trigger Ln of a linear feedback shift register is respectively connected with a NOR gate and a NAND gate, and output signal ends of n-1 low-bit triggers in the linear feedback shift register are respectively connected with a comparator; a sign bit xn of an n-bit binary number corresponding to the target numerical value is input into the NOR gate and the NAND gate respectively; bits corresponding to the amplitude bits of the n-bit binary number are input to the comparator; the comparator and the NOR gate are connected with the OR gate; the OR gate and the NAND gate are connected with the AND gate. In the application, the two bit stream random number generators can generate two bit streams with low correlation, so that the numerical value shown by the bit stream obtained by carrying out multiplication (namely XNOR operation) on the two bit streams is closer to the product result of two target numerical values.

An apparatus comprises a first OR gate, a second OR gate, a first NAND gate, and a second NAND gate. The first OR gate comprises a first input terminal, a second input terminal, and an output terminal. The second OR gate comprises a first input terminal, a second input terminal, and an output terminal. The first NAND gate comprises a first input terminal coupled to the output terminal of the first OR gate. The first NAND gate also comprises a second input terminal coupled to the output terminal of the second OR gate. The second NAND gate comprises an output terminal coupled to the first input terminal of the second OR gate.

The utility model discloses a kind of bridge drive anti-through protection circuit, including double-channel driver N2, its enable end EN and two output ends;Terminal PWMA_OUT and terminal PWMB_OUT are led out from the two output ends of double-channel driver N2, for output bridge circuit's drive signal;The terminal PWMA_OUT and terminal PWMB_OUT are respectively connected to the two input ends of NAND gate N3;The output end Y of NAND gate N3 is connected to level adjustment circuit;The level adjustment circuit is connected with the enable end EN of double-channel driver N2, to control the high and low of the enable end EN level of double-channel driver N2 according to the output end signal of NAND gate N3.The utility model has the advantages that: protection to bridge circuit is realized, protection can be carried out quickly when through occurs in bridge circuit, simultaneously with the holding lock of protection action, reset control etc., simultaneously, circuit is simple and reliable, protection is stable.

The utility model provides a T-type inverter driving signal interlocking circuit and an inverter. Comprising a first NOT gate for receiving a first signal and outputting a first inversion signal; the second NOT gate receives the second signal and outputs a second inverted signal; the third NOT gate receives the third signal and outputs a third inversion signal; the fourth NOT gate receives the fourth signal and outputs a fourth inverted signal; the first input end of the first AND gate driving unit receives a first signal, the second input end of the first AND gate driving unit is connected with the output end of the second NOT gate, and the third input end of the first AND gate driving unit is connected with the output end of the third NOT gate; the first input end of the second AND gate driving unit receives a second signal, the second input end is connected with the output end of the first NOT gate, the third input end is connected with the output end of the fourth NOT gate, and the second AND gate driving unit outputs a lower tube driving signal. Interlocking of driving signals is achieved, it is guaranteed that the upper pipe and the lower pipe, the upper pipe and one middle pipe, and the lower pipe and the other middle pipe of the T-type inverter cannot be switched on at the same time during operation, and operation safety of the inverter is effectively guaranteed.

The invention discloses an off-line high-speed CAN communication relay device, which comprises a CAN transceiver I, a CAN transceiver II, a single-channel analog switch 1, a single-channel analog switch 2, an RS trigger 1 with a control signal, an RS trigger 2 with a control signal, an NAND gate 1, an NAND gate 2, an NAND gate 3, an NAND gate 4 and four pull-up resistors, can realize a target function only by using a hardware circuit, does not use a CPU (Central Processing Unit), and is convenient to use. A software program does not need to be written, and development difficulty and material cost are reduced; only a hardware circuit is used, the communication delay can be reduced to the nanosecond level, and the method can be applied to a high-speed communication scene above 1Mbps; the data transmission direction can be identified only by using signals on the CAN bus, additional control signals are not needed, the anti-interference capability and reliability of the circuit are enhanced, other equipment does not need to be matched and changed, and the application range is wide.

The application relates to a dynamic clock monitoring circuit and belongs to the field of integrated circuit design. The circuit comprises a first part, a second part, a third part for indefinite state setting, and resistance R, capacitor Cc, third NMOS tube N3, Schmidt trigger S1, first inverter INV1, first two-input AND gate AND1, fourth inverter INV4 and fifth inverter INV5; the first part comprises third inverter INV3, second two-input NAND gate NAND2 and first switch S1; the second part comprises first two-input NAND gate NAND1, second inverter INV2 and second switch S2; and the third part 12 comprises two PMOS tubes and two NMOS tubes. The circuit monitors the condition of the system clock through the circuit monitoring system, and outputs two kinds of monitoring signals to provide effective clock monitoring signals for the system.