Frequency discrimination phase discriminator and method applying to phase-locked loop

Abstract

The embodiment of the invention discloses a frequency discrimination phase discriminator. The phase discriminator comprises two D triggers D1 and D2, as well as a nand gate NA1 and a buffer 1, the output ends of the two D triggers D1 and D2 are utilized as an input end of the nand gate; an output end of the nand gate NA1 passes through the buffer 1 to utilize as a second reset terminal RST 2 of the two D triggers, and the output ends of the D trigger D1 and the D trigger D2 can respectively obtain signal Q1 and Q2; and the phase discriminator also comprises a timing control unit, the signals Q1 and Q2 are input signals of the timing control unit, and the timing control unit is used for controlling phase and pulse width of an output signal of the frequency discrimination phase discriminator. The invention also discloses a charge pump phase locked loop applying to the frequency discrimination phase discriminator and a method of a phase locked loop applying to the frequency discrimination phase discriminator. The technical scheme of the phase discriminator and the phase locked loop and the method can effectively avoid an error caused by mismatch charge pump current through a simple circuit structure.

Description

technical field [0001] The invention relates to the field of analog phase-locked loop circuits, in particular to a frequency and phase detection circuit applied to the phase-locked loop circuit and a method for applying the frequency and phase detection circuit to the phase-locked loop. Background technique [0002] PLL-Phase Locked Loop is a basic and very important module in analog and digital-analog hybrid circuits. The indirect frequency synthesizer composed of phase-locked loop plays a very important role in the field of wireless communication. The phase-locked loop is a phase error control system. By comparing the phase difference between the input signal and the output signal of the voltage-controlled oscillator, an error control voltage is generated, and the frequency of the voltage-controlled oscillator is adjusted to achieve the same frequency as the input signal. A high-performance phase-locked loop must meet the requirements of high speed, high stability and low...

AI Technical Summary

Problems solved by technology

When operating at low supply voltages, the charge pump current mismatch becomes an important factor limiting the performance of the PLL due to the fact that the cascode circuit structure may not be suitable

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