6 results about "Charge pump phase locked loop" patented technology

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

This application relates to the field of electronic circuit technology, providing a current-steering charge pump circuit and a charge pump phase-locked loop. The current-steering charge pump circuit includes: a reference current mirror connected to the analog circuit's positive power supply, current source, first switch, and the non-inverting input of the first rail-to-rail operational amplifier; a discharge current mirror connected to the first switch, the output of the first rail-to-rail operational amplifier, a second switch, a fifth switch, a seventh switch, and analog ground; a charging current mirror connected to the analog circuit's positive power supply, a third switch, a fourth switch, a sixth switch, and the output of the second rail-to-rail operational amplifier; a third switch connected to the second switch and the non-inverting input of the second rail-to-rail operational amplifier; and a fourth switch connected to the fifth switch and the output of the third rail-to-rail operational amplifier. This circuit can increase the output voltage swing while ensuring that the charging and discharging currents are equal.

The invention relates to a compensation circuit, a compensation method and a calibration system, which are used for connecting a charge pump phase-locked loop circuit. The charge pump phase-locked loop circuit adjusts the control voltage under the action of the charging current and the discharging current; the compensation circuit comprises a detection module and a comparison module, and the detection module is used for being connected with the charge pump phase-locked loop circuit and providing feedback voltage and detection voltage. The feedback voltage is equal to the control voltage, and the magnitude relationship between the detection voltage and the feedback voltage corresponds to the magnitude relationship between the charging current and the discharging current; the comparison module is connected with the detection module and is used for outputting an adjusting signal corresponding to a difference voltage between the control voltage and the detection voltage; the adjusting signal is used for adjusting charging current and / or discharging current of the charge pump phase-locked loop circuit. According to the charge pump phase-locked loop circuit, current mismatch of the charge pump phase-locked loop circuit can be reduced, so that the noise and stray performance of the charge pump phase-locked loop circuit is improved.

This application provides a real-time calibration circuit, method, and apparatus for a charge pump phase-locked loop (PLL) based on phase detection. The real-time calibration circuit includes a time-to-digital converter (TDD) circuit, a thermometer code conversion circuit, and a logic state machine circuit. The TDD circuit converts two output signals from a frequency and phase detector into digital time signals based on the PLL lock indication signal output from the lock detection circuit. The thermometer code conversion circuit converts the digital time signals into binary code. The logic state machine circuit generates a calibration feedback control signal based on the binary code and transmits this signal to the current-rudder dual-channel switch charge pump in the PLL circuit to calibrate the voltage control signal output by the current-rudder dual-channel switch charge pump in real time. This real-time calibration circuit improves the consistency of the circuit under different processes, temperatures, and power supply voltages, and improves the reference spurious level of the PLL circuit.

The utility model relates to a low-current mismatch charge pump circuit applied to a CMOS charge pump phase-locked loop (CPPLL). According to the low-current mismatch circuit, through a negative feedback loop formed by a source follower (SF), an operational amplifier (OPA) and a common gate buffer (CG), the drain end voltage of a common source of a cascode current source is clamped, and the change of the drain end voltage of the current source caused by the change of the drain end voltage of a common gate of a cascode current mirror is suppressed, so that low-current mismatch is realized. In addition, through a buffer formed by a cascode current mirror, a current source and drain electrode switch tube and a rail-to-rail operational amplifier capable of clamping an output point, the problems of electric leakage of a charge pump with a conventional structure, mismatch of currents of a positive current source and a negative current source and charge sharing are solved.

The application discloses a charge pump phase-locked loop and relates to the field of phase-locked loops. In order to solve the problem that a traditional charge pump phase-locked loop cannot effectively reduce VCO output phase noise while ensuring normal operation of the charge pump, the application provides a charge pump phase-locked loop. The charge pump phase-locked loop is structured by a new type of analog phase detector + charge pump, and the difference between mirror currents of the charge pump generated by a reference clock signal and a feedback clock signal in different phase stages is used to charge / discharge a loop filter. The charge pump phase-locked loop can meet stable control of a control voltage of the loop filter, and CMOS switches are not needed. Therefore, the adverse effects caused by clock feedthrough and charge injection can be obviously reduced, and the normal operation of the charge pump phase-locked loop is not affected.