13 results about "Charge pump phase locked loop" patented technology

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

This application relates to the field of electronic circuit technology, providing a current-steering charge pump circuit and a charge pump phase-locked loop. The current-steering charge pump circuit includes: a reference current mirror connected to the analog circuit's positive power supply, current source, first switch, and the non-inverting input of the first rail-to-rail operational amplifier; a discharge current mirror connected to the first switch, the output of the first rail-to-rail operational amplifier, a second switch, a fifth switch, a seventh switch, and analog ground; a charging current mirror connected to the analog circuit's positive power supply, a third switch, a fourth switch, a sixth switch, and the output of the second rail-to-rail operational amplifier; a third switch connected to the second switch and the non-inverting input of the second rail-to-rail operational amplifier; and a fourth switch connected to the fifth switch and the output of the third rail-to-rail operational amplifier. This circuit can increase the output voltage swing while ensuring that the charging and discharging currents are equal.

The invention relates to a compensation circuit, a compensation method and a calibration system, which are used for connecting a charge pump phase-locked loop circuit. The charge pump phase-locked loop circuit adjusts the control voltage under the action of the charging current and the discharging current; the compensation circuit comprises a detection module and a comparison module, and the detection module is used for being connected with the charge pump phase-locked loop circuit and providing feedback voltage and detection voltage. The feedback voltage is equal to the control voltage, and the magnitude relationship between the detection voltage and the feedback voltage corresponds to the magnitude relationship between the charging current and the discharging current; the comparison module is connected with the detection module and is used for outputting an adjusting signal corresponding to a difference voltage between the control voltage and the detection voltage; the adjusting signal is used for adjusting charging current and / or discharging current of the charge pump phase-locked loop circuit. According to the charge pump phase-locked loop circuit, current mismatch of the charge pump phase-locked loop circuit can be reduced, so that the noise and stray performance of the charge pump phase-locked loop circuit is improved.

This application provides a real-time calibration circuit, method, and apparatus for a charge pump phase-locked loop (PLL) based on phase detection. The real-time calibration circuit includes a time-to-digital converter (TDD) circuit, a thermometer code conversion circuit, and a logic state machine circuit. The TDD circuit converts two output signals from a frequency and phase detector into digital time signals based on the PLL lock indication signal output from the lock detection circuit. The thermometer code conversion circuit converts the digital time signals into binary code. The logic state machine circuit generates a calibration feedback control signal based on the binary code and transmits this signal to the current-rudder dual-channel switch charge pump in the PLL circuit to calibrate the voltage control signal output by the current-rudder dual-channel switch charge pump in real time. This real-time calibration circuit improves the consistency of the circuit under different processes, temperatures, and power supply voltages, and improves the reference spurious level of the PLL circuit.

This invention relates to the field of charge pump phase-locked loop (CPPLL) design technology, specifically to an adaptive temperature-compensated charge pump PLL circuit and module based on a magnetic tunnel junction (MTJ). The invention provides an MTJ-based adaptive temperature-compensated charge pump PLL circuit, comprising: a frequency and phase discriminator, a charge pump section, a low-pass filter section, a voltage-controlled oscillator (VCO) section, and a frequency divider section. Based on the traditional charge pump PLL, this invention connects a magnetic tunnel junction (MTJ) in series with the upper and lower charge / discharge circuits of the charge pump section, and also connects a MTJ in series with the output terminal of the dual-input, dual-output VCO section. Utilizing the MTJ for temperature compensation effectively reduces the current mismatch of the charge pump and significantly improves the frequency stability of the VCO, ensuring and enhancing the performance of the CPPLL. This invention solves the problem of CPPLLs being easily affected by on-chip system temperature changes.

The invention relates to a low-noise double-path digital auxiliary phase-locked loop circuit for a large-area-array image sensor, and belongs to the technical field of integrated circuit clock circuits. The problems that a traditional charge pump phase-locked loop cannot achieve fractional frequency division, the resolution ratio is low, the frequency modulation range is limited, the locking speed is low, and frequency control is inaccurate are solved. According to the technical scheme, a double-path structure is included, a proportional path adopts a third-order passive filter to optimize dynamic response and suppress in-band phase noise, and an integral path eliminates charge pump nonlinearity to lock frequency; the digital-to-time converter compensates the quantization error of the sigma modulator in a feedback path; and the DTC calibration module dynamically adjusts the gain through a symbol least mean square algorithm. The method has the technical effects that the phase noise is obviously reduced, the output frequency precision is improved, the environmental adaptability is enhanced, the system stability and the locking speed are optimized, and wide-range application such as a large-area-array image sensor is supported.

The invention discloses a charge pump, a phase-locked loop and a DCDC converter. The charge pump comprises a first upper current source, a first lower current source, a first switch group, a charging and discharging unit, a control unit, a first current generation unit and a second current generation unit. The charging and discharging unit detects the frequency of a reference clock signal in real time in a charging and discharging mode, and the control unit generates a corresponding control signal based on frequency detection so as to control the first current generation unit and the second current generation unit to change the current of the charge pump. According to the charge pump, the phase-locked loop and the DCDC converter provided by the invention, the phase difference between the reference clock signal and the switch clock signal under the high frequency of the reference clock signal is reduced while the loop stability under the low frequency of the reference clock signal is ensured, the frequency establishment stabilization time is reduced, and the performance of the phase-locked loop is improved.

The invention provides a charge pump phase-locked loop real-time calibration circuit, method and device based on phase detection, and the circuit comprises a time-to-digital conversion circuit, a thermometer code conversion circuit, and a logic state machine circuit. The time-to-digital conversion circuit converts two output signals of the phase frequency detector into time-to-digital signals based on phase-locked loop locking indication signals output by the locking detection circuit, the thermometer code conversion circuit converts the time-to-digital signals into binary codes, and the logic state machine circuit forms calibration feedback control signals based on the binary codes. And transmitting the calibration feedback control signal to a current steering type two-way switch charge pump of a charge pump phase-locked loop circuit so as to calibrate a voltage control signal output by the current steering type two-way switch charge pump in real time. According to the charge pump phase-locked loop real-time calibration circuit, the consistency of the circuit under different processes, temperatures and power voltages can be improved, and the reference stray level of the charge pump phase-locked loop circuit is improved.

The utility model relates to a low-current mismatch charge pump circuit applied to a CMOS charge pump phase-locked loop (CPPLL). According to the low-current mismatch circuit, through a negative feedback loop formed by a source follower (SF), an operational amplifier (OPA) and a common gate buffer (CG), the drain end voltage of a common source of a cascode current source is clamped, and the change of the drain end voltage of the current source caused by the change of the drain end voltage of a common gate of a cascode current mirror is suppressed, so that low-current mismatch is realized. In addition, through a buffer formed by a cascode current mirror, a current source and drain electrode switch tube and a rail-to-rail operational amplifier capable of clamping an output point, the problems of electric leakage of a charge pump with a conventional structure, mismatch of currents of a positive current source and a negative current source and charge sharing are solved.

The present invention provides an open-closed loop smooth switching system based on a charge pump phase-locked loop, comprising: a reference clock fault detection module connected to the charge pump phase-locked loop, which detects whether a reference clock fault has occurred and provides reference clock fault indication control; a PLL lock detection module, which performs phase-locked loop lock indication control based on the phase difference between the reference clock's frequency-divided signal and the charge pump output clock's frequency-divided signal; an ADC / DAC control module, which performs auxiliary hold of the charge pump open loop and auxiliary release of the charge pump phase-locked loop from open loop to closed loop; and a PLL control state machine module, which controls the state machine to select clocks, enter hold state, and exit hold state. The present invention can identify fault information as early as possible, realize open-closed loop conversion of the charge pump phase-locked loop, and enter or exit hold state. Furthermore, the deviation between the charge pump's reacquired reference clock and the initial frequency value is less than 0.15ppm, and the switching is completed smoothly without affecting subsequent circuits.

The application discloses a charge pump phase-locked loop and relates to the field of phase-locked loops. In order to solve the problem that a traditional charge pump phase-locked loop cannot effectively reduce VCO output phase noise while ensuring normal operation of the charge pump, the application provides a charge pump phase-locked loop. The charge pump phase-locked loop is structured by a new type of analog phase detector + charge pump, and the difference between mirror currents of the charge pump generated by a reference clock signal and a feedback clock signal in different phase stages is used to charge / discharge a loop filter. The charge pump phase-locked loop can meet stable control of a control voltage of the loop filter, and CMOS switches are not needed. Therefore, the adverse effects caused by clock feedthrough and charge injection can be obviously reduced, and the normal operation of the charge pump phase-locked loop is not affected.

The invention discloses a low-current mismatch charge pump circuit for a phase-locked loop, which belongs to the technical field of charge pump phase-locked loops and comprises a PMOS (P-channel Metal Oxide Semiconductor) tube MP1, an NMOS (N-channel Metal Oxide Semiconductor) tube MN1, switches S1-S4, an operational amplifier OP1, a current detection unit and a current-to-voltage conversion and amplification unit. The switches S1 to S4 form a switch matrix, the switch S1 and the switch S2 are located on one side of the switch matrix, the switch S4 and the switch S3 are located on one side of the switch matrix, the switch S2 and the switch S4 are located above, the switch S3 and the switch S1 are located below, a source electrode of the PMOS tube MP1 is connected with a VDD power supply end, a drain electrode of the PMOS tube MP1 is connected with a node Y, and a grid electrode of the PMOS tube MP1 is connected with an output end of the current-to-voltage conversion and amplification unit. The control loop directly controls the current source, errors are prevented from being introduced by using a reference current branch, and current matching is guaranteed; and a NAND gate circuit is added, so that instability of bias voltage of the current source during inherent pulse is avoided.

The present disclosure provides a charge pump, a phase-locked loop circuit and a transceiver. The charge pump comprises: a first current source circuit comprising a first transistor and a first variable resistor open-loop gain module for causing a voltage at an input terminal of the first transistor to be consistent with a first reference voltage; a second current source circuit comprising a second transistor and a second variable resistor open-loop gain module for causing a voltage at an output terminal of the second transistor to be consistent with a second reference voltage; and a switching circuit coupled to the first and second current source circuits and the loop filter, and configured to control charging of the loop filter in response to an output signal from a phase frequency detector. The charge pump, the phase-locked loop circuit and the transceiver can suppress the flicker noise for the charge pump.