106 results about "Built in self testing" patented technology

A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum operating voltage of an integrated circuit is determined either during external testing of the integrated circuit or during built-in-self-testing. The minimum operating voltage is transmitted to a variable voltage regulator where it is used to set the output of the regulator. The output of the regulator supplies the integrated circuit with its operating voltage. This technique enables tailoring of the operating voltage of integrated circuits on a part-by-part basis which results in power consumption optimization by adapting operating voltage in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms. Alternatively, the invention enables adaptive adjustment of the operating frequency of an integrated circuit. The invention enables system designers to adaptively optimize either system performance or power consumption on a part-by-part basis in response to tester-to system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms.

An integrated device including a functional circuitry and a built-in self testing circuit for executing a structured test on the functional circuitry is proposed. The functional circuitry includes means for receiving input test values from the built-in self testing circuit and returning output test values to the built-in self testing circuit. In the solution of the invention, the built-in self testing circuit includes a memory for storing starting test values and expected test values, means for generating the input test values according to the starting test values, and means for determining a result of the structured test according to a comparison between the output test values and the expected test values.

Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.

A semiconductor integrated circuit includes: a memory collars including: a memory cell; a fetch register that is configured to fetch data as a first fetch data; a comparing unit that is configured to compare the first fetch data with an expected value; a failure detecting signal output unit that is configured to receive the compared result and output a failure detecting signal; and a BIST circuit including: a BIST control unit that is configured to output an instruction and output a BIST status; a shift controller that is configured to receive a first clock signal, the BIST status signal, and the failure detecting signal and output sift enable signal; a shift counter that counts the number of clock pulses on the first clock signal; a first storage register that is configured to receive the first clock signal and the shift enable signal, and a second storage register that is configured to receive a second clock signal.