Interconnection line test circuit used in field programmable gate array device

Abstract

The invention relates to an interconnection line testing circuit used in a field programmable gate array device, which comprises even number of vector generation and respond analyzers. Each vector generation and respond analyzer in the even number of vector generation and respond analyzers comprises an n-input and n-output logic combined circuit and a group of n-bit registers, wherein, n is a natural number; and every two vector generation and respond analyzers are connected by interconnection lines with opposite direction and the bit width of n and are combined into a built-in self-testing circuit. The built-in self-testing circuit can achieve the simultaneous test of the two groups of interconnection lines with opposite direction and larger bit width on the condition that the number of the registers is not changed, shorten the testing time of a FPGA device, and reduce the testing cost of the FPGA device.

Description

technical field [0001] The invention relates to an interconnection testing technology, in particular to an interconnection circuit used in a field programmable gate array device. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, FPGA) is composed of logic cell array (Logic Cell Array, LCA), which includes configurable logic block (Configurable Logic Block, CLB), output and input module (InputOutput Block, IOB) and internal wiring (Interconnect, IR) three parts; IOB can provide the connection interface between FPGA internal logic and package pins, CLB can be used to realize the logic and timing storage function of FPGA chip, and IR is used to realize FPGA Signal communication between CLB and IOB in the chip. [0003] There are configurable logic and timing resources such as look-up tables (Look Up Table, LUT) and registers in the two-dimensional CLB array to realize logic design and timing design functions; in FPGA, each CLB correspo...

AI Technical Summary

Problems solved by technology

[0008] With the development of FPGA test technology, there are two other test methods for multi-bit interconnection lines formed by FPGA test configuration. One is to use the method of directly loading test stimuli through the external pins of FPGA devices. The disadvantage is that if the scale of the FPGA device increases, the increase in the number of external pins is far behind the increase in the number of interconnect resources in the FPGA device; therefore, the method of directly adding test incentives is not suitable for the existing large-scale Interconnect lines formed during interconnect resource testing in FPGA devices

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