6 results about "Processor register" patented technology

A method of preloading address translation information directly into cache memory of an IOMMU includes storing the address translation information in a register set of memory management input / output registers of an input-output memory management unit and loading the address translation information into cache memory of the input-output memory management unit. The address translation information includes a virtual address and a corresponding physical address of system memory of a computing system. The address translation information is sent by software being executed by a processor of the computing system. The address translation information is received directly from the processor.

The trusted platform module (TPM) includes a TPM logic circuit, a receive buffer, a TPM register, and one or more processors. The TPM register is a storage space obtained by dividing a memory of the TPM. The TPM logic circuit receives a TPM register write command from a host and stores a payload of the write command into the receive buffer. The payload of the TPM register write command is a part or all of content forming TPM command data. When data in the receive buffer reaches a first data amount threshold, the processor dumps the data in the receive buffer into the TPM register. When all the content of the TPM command data is stored in the TPM register, the one or more processors execute the TPM command data.

The application discloses a kind of hardware perception type vector quantization calculation fusion acceleration instruction parallel processing system and method.For the memory bandwidth bottleneck problem of asymmetric distance calculation in large-scale vector retrieval, the application is inside processor register, 8-bit quantization encoding is loaded, zero extension to 32-bit floating point precision, affine correction based on quantization offset and scale factor, and distance accumulation operation for query vector are fused into single instruction multiple data stream driven in-register execution pipeline.The method eliminates the intermediate memory copy and register overflow operation in the traditional scheme, improves the throughput capacity of vector retrieval and processor resource utilization under the premise of maintaining the calculation accuracy.

A processing device (20) has a processor (200) including a plurality of delay push processor registers (214) and a processor register control circuit (220, 222, 224, 226, 228). The processor register control circuit (220, 222, 224, 226, 228) includes a plurality of status registers (226), each status register (226) corresponding to a respective different delay push register (214). The processor register control circuit (220, 222, 224, 226, 228) is configured to detect a write of a new value to a register (214) in the delay push registers (214) and determine whether a status register (226) of the delay push register (214) has a first value indicating an unsaved state of the delay push register (214). The processor control circuit (220, 222, 224, 226, 228) is configured, when the status register (226) has the first value, to read a current value from the delay push register (214) before completion of the write of the new value to the delay push register (214), write the current value to a memory (202), and set the status register (226) of the delay push register (214) to a second value indicating a saved state of the delay push register (214).

The application discloses a microcontroller unit (MCU) firmware grey box fuzzing test method. The method first establishes a high-fidelity peripheral simulator in a simulation execution environment, the peripheral simulator including peripheral registers, internal states and state machines, and determines the interrupt line enable state by jointly monitoring the global interrupt controller register and the peripheral interrupt control register to realize the controlled triggering of the peripheral interrupt. Secondly, the time when the firmware or DMA reads the peripheral data register is determined as an input consumption point during firmware execution, an incremental snapshot containing the processor register state, the peripheral state and the memory dirty page information is saved at the input consumption point, and only the input data that has not been read is mutated after the snapshot is restored. Finally, the test input is divided into multiple input streams corresponding to different peripherals or data registers, a probability distribution is constructed according to the access frequency of each input stream, and the input stream to be mutated is selected, so that the path exploration efficiency and the vulnerability discovery capability of the fuzzing test are improved.

The application discloses a kind of space and feature coupling coding geographic data index construction and screening method and system, belong to geographic information system and distributed computing technical field.The method constructs coupling identifier containing spatial position coding domain and business feature coding domain, the identifier is the fixed bit width binary integer of adaptation processor register bit width, support two coding domain high-low configuration, and construct ordered index with it as sorting key;When screening, according to request generation space bit mask and feature bit mask, execute branchless bit operation sequence to coupling identifier, complete double determination of spatial correlation and business feature matching in single instruction stream;System supports the dynamic maintenance of fragment based on routing mapping relationship adjustment, and fragment operation only adjusts routing mapping relationship while identifier coding is unchanged, to avoid piece by piece rehashing and recoding.System includes coupling coding module, storage module, bit mask screening engine and communication module.