22 results about "Processor register" patented technology

The invention discloses a closed source software system behavior description method based on virtualization, which comprises the following steps of: starting a VMX mode, and configuring a processor register to support a virtualization environment; a binary instruction stream of the closed source software is analyzed, and a real function entry address of the target is obtained; setting an INT3 breakpoint at the function entry address, and storing an original instruction; and breakpoint triggering information is received and processed through the Hypervisor layer. According to the method, the execution process of the closed source software is captured and analyzed in the virtual environment, the analysis process reduces the dependence on the symbol table, the system call sequence is modeled and analyzed in combination with the Markov chain model, the operation behavior of the closed source software is accurately described, and in addition, the operation efficiency of the closed source software is improved. According to the method, regular behaviors of normal applications can be found, and potential abnormal calling and malicious behaviors can be identified in time, so that a customization function is realized according to requirements, and a reliable basis is provided for system security monitoring and behavior analysis.

The invention provides a vehicle-mounted black box protection system, a control method, a storage medium and a product. The vehicle-mounted black box protection system comprises a shell assembly, a sensor module, a lock catch fusing mechanism and a circuit board, the circuit board comprises a processor, a register, a memory and a power supply; the lock catch fusing mechanism is installed between the inner wall of the shell assembly and the circuit board, and the sensor module is arranged on the shell assembly; the lock catch fusing mechanism is connected with the register and the memory; when the sensor module detects that the shell is opened illegally, a sensing signal is triggered and sent to the processor, the processor controls the lock catch fusing mechanism to be powered on, and therefore the lock catch fusing mechanism works to fuse the register and the storage. Therefore, when the case is detected to be opened illegally, the automatic fusing mechanism of the internal circuit board can destroy the hardware environment for data storage in time, so that the data cannot be tampered, and the integrity and authenticity of the data recorded by the data recording system (EDR) are ensured.

One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.

A method of preloading address translation information directly into cache memory of an IOMMU includes storing the address translation information in a register set of memory management input / output registers of an input-output memory management unit and loading the address translation information into cache memory of the input-output memory management unit. The address translation information includes a virtual address and a corresponding physical address of system memory of a computing system. The address translation information is sent by software being executed by a processor of the computing system. The address translation information is received directly from the processor.

Provided is a method for a secure execution of a first instruction by a processor of an electronic system comprising fetching said first instruction in an execution pipeline of the processor, and determining if said first instruction to be executed is a load instruction to be protected for loading protected data, or a store instruction to be protected for storing protected data, and associated security information from said at least one memory to the processor registers. The method includes executing sequentially at least a first operation, a second operation and a third operation, depending on whether said first instruction is a load instruction or store instruction. Other embodiments disclosed.

The present application relates to the technical field of digital data processing and digital signal processor computing power allocation, and discloses a fiber communication abnormal peak early warning method based on modulation instability gain spectrum, comprising: mapping link parameter data stream to generate discrete topological node array according to set distance resolution; generating resonance proximity data according to disturbance and resonance angular frequency data of each node; when the resonance proximity data reaches the set hard logic threshold, determining that the corresponding node is an active node, and directing the computing resource to the local slice composed of the active node and adjacent nodes; calculating the risk characteristic quantity by calculating the multi-dimensional spectrum matrix of the equivalent parameter sequence in the local slice, and outputting the early warning signal when the risk level threshold is reached; the present application avoids data divergence caused by global synchronous calculation through local allocation of computing resource space dimension, reduces the computing power overhead of processor register, and improves the parameter convergence stability of multi-dimensional parameter matrix calculation under noise interference working condition.

The trusted platform module (TPM) includes a TPM logic circuit, a receive buffer, a TPM register, and one or more processors. The TPM register is a storage space obtained by dividing a memory of the TPM. The TPM logic circuit receives a TPM register write command from a host and stores a payload of the write command into the receive buffer. The payload of the TPM register write command is a part or all of content forming TPM command data. When data in the receive buffer reaches a first data amount threshold, the processor dumps the data in the receive buffer into the TPM register. When all the content of the TPM command data is stored in the TPM register, the one or more processors execute the TPM command data.

The application discloses a processor supporting register release, a register release method, a display card and equipment, and belongs to the technical field of register management. The processor comprises a plurality of registers, an allocation management unit and a resource management unit. The allocation management unit is used for allocating at least two register sets for a first thread group, and each register set in the at least two register sets comprises at least one register in the plurality of registers. The resource management unit is used for releasing a first register set in response to the end of use of all registers in the first register set by the first thread group, and the first register set is one register set in the at least two register sets. The processor supports early release of the first register set when the first thread group ends the use of all registers in the first register set, thereby avoiding the problem of low utilization of register resources caused by long-term occupation of the first register set by the first thread group.

The application discloses a kind of hardware perception type vector quantization calculation fusion acceleration instruction parallel processing system and method.For the memory bandwidth bottleneck problem of asymmetric distance calculation in large-scale vector retrieval, the application is inside processor register, 8-bit quantization encoding is loaded, zero extension to 32-bit floating point precision, affine correction based on quantization offset and scale factor, and distance accumulation operation for query vector are fused into single instruction multiple data stream driven in-register execution pipeline.The method eliminates the intermediate memory copy and register overflow operation in the traditional scheme, improves the throughput capacity of vector retrieval and processor resource utilization under the premise of maintaining the calculation accuracy.

The invention discloses a method for achieving exception protection based on a signal processing mechanism, a medium and electronic equipment, and the method comprises the steps that in the program running process, when preset error type information is generated, a signal processor registered according to the preset error type information receives the preset error type information; the signal processor obtains current operation information and packages the current operation information into abnormal log information; the signal processor determines a processing rule corresponding to the preset error type information; under the condition that the processing rule is determined to return the storage point, the signal processor acquires information of the storage point which needs to be returned currently; and the signal processor loads the information of the storage point and executes corresponding operation according to the abnormal protection behavior corresponding to the storage point. According to the technical scheme provided by the invention, the phenomenon that the program crashes can be avoided, and problems in the program can be quickly and accurately checked, so that the stability and robustness of the program can be improved.

A processing device (20) has a processor (200) including a plurality of delay push processor registers (214) and a processor register control circuit (220, 222, 224, 226, 228). The processor register control circuit (220, 222, 224, 226, 228) includes a plurality of status registers (226), each status register (226) corresponding to a respective different delay push register (214). The processor register control circuit (220, 222, 224, 226, 228) is configured to detect a write of a new value to a register (214) in the delay push registers (214) and determine whether a status register (226) of the delay push register (214) has a first value indicating an unsaved state of the delay push register (214). The processor control circuit (220, 222, 224, 226, 228) is configured, when the status register (226) has the first value, to read a current value from the delay push register (214) before completion of the write of the new value to the delay push register (214), write the current value to a memory (202), and set the status register (226) of the delay push register (214) to a second value indicating a saved state of the delay push register (214).

Disclosed herein is a new technique for providing a storage controller with variable interface communication speeds to allow the storage controller to set different communication speeds and frequencies for different communication channels between the storage controller and respective memories. A controller comprises: a processor; registers; and a clock generator configured to generate clock signals respectively for multiple communication channels based on values stored in the registers. The controller is configured to communicate with non-volatile memories through the communication channels respectively using the clock signals.

The present disclosure is directed to a method for writing to a register file of a processor. The method includes receiving a first instruction associated with a first execution unit of the processor, with the first instruction being associated with writing to one or more banks of a plurality of banks of the register file via a write port of the register file. The method includes determining a conflict between the first instruction and a second instruction associated with a second execution unit, with the second instruction being associated with writing to the one or more banks via the write port. The method includes performing one or more actions with respect to the first instruction and the second instruction based on determining the conflict.

The application discloses a microcontroller unit (MCU) firmware grey box fuzzing test method. The method first establishes a high-fidelity peripheral simulator in a simulation execution environment, the peripheral simulator including peripheral registers, internal states and state machines, and determines the interrupt line enable state by jointly monitoring the global interrupt controller register and the peripheral interrupt control register to realize the controlled triggering of the peripheral interrupt. Secondly, the time when the firmware or DMA reads the peripheral data register is determined as an input consumption point during firmware execution, an incremental snapshot containing the processor register state, the peripheral state and the memory dirty page information is saved at the input consumption point, and only the input data that has not been read is mutated after the snapshot is restored. Finally, the test input is divided into multiple input streams corresponding to different peripherals or data registers, a probability distribution is constructed according to the access frequency of each input stream, and the input stream to be mutated is selected, so that the path exploration efficiency and the vulnerability discovery capability of the fuzzing test are improved.

The present disclosure is directed to a method for writing to a register file of a processor. The method includes receiving a first instruction associated with a first execution unit of the processor, with the first instruction being associated with writing to one or more banks of a plurality of banks of the register file via a write port of the register file. The method includes determining a conflict between the first instruction and a second instruction associated with a second execution unit, with the second instruction being associated with writing to the one or more banks via the write port. The method includes performing one or more actions with respect to the first instruction and the second instruction based on determining the conflict.

The application discloses a fault processing method, device, equipment and medium, and belongs to the technical field of servers. The method comprises the following steps: setting a security network configuration item and an error processing configuration item for a manager port; in response to receiving fault alarm information through the manager, obtaining processor register information, wherein the processor register information comprises a current fault diagnosis state, and determining whether to collect fault diagnosis source data according to the current fault diagnosis state; in response to collecting the fault diagnosis source data, determining whether to perform a soft restart on the system according to the error processing configuration item; in response to performing the soft restart on the system according to the security network configuration item, determining a fault type according to the fault diagnosis source data, and automatically analyzing and processing the fault according to the fault type. The application can realize compatibility of hardware and software, and can automatically collect fault source data and process the fault after the fault occurs, thereby improving the correctness of fault processing.

The application discloses a kind of space and feature coupling coding geographic data index construction and screening method and system, belong to geographic information system and distributed computing technical field.The method constructs coupling identifier containing spatial position coding domain and business feature coding domain, the identifier is the fixed bit width binary integer of adaptation processor register bit width, support two coding domain high-low configuration, and construct ordered index with it as sorting key;When screening, according to request generation space bit mask and feature bit mask, execute branchless bit operation sequence to coupling identifier, complete double determination of spatial correlation and business feature matching in single instruction stream;System supports the dynamic maintenance of fragment based on routing mapping relationship adjustment, and fragment operation only adjusts routing mapping relationship while identifier coding is unchanged, to avoid piece by piece rehashing and recoding.System includes coupling coding module, storage module, bit mask screening engine and communication module.

The invention discloses an RISC-V processor-oriented finite field modular operation acceleration implementation method. Comprising the following steps: 1, constructing an unsaturated multi-limb representation model of finite field elements in a 64-bit general register of a processor; 2, based on a multiplication instruction execution delay characteristic of the RISC-V processor, designing a calculation and memory access interleaved instruction scheduling strategy; 3, carrying out decoupling scheduling on carry propagation and a modular reduction path by adopting a delay correction mechanism in the general register; 4, aiming at modular square operation, constructing an instruction level reduction path in a processor instruction set environment, and realizing cross-limb carry processing through a logic shift instruction and an unsigned comparison instruction; and 5, realizing a delay accumulation and mask correction mechanism of modular addition and subtraction operation on a register level by using a redundant bit width represented by unsaturation. According to the method, on the premise of not changing the mathematical structure of the original cryptographic algorithm, the operation acceleration which is several times of the existing implementation is realized by optimizing the register resources and instruction scheduling of the processor.

A processing apparatus has a processor comprising a plurality of deferred-push processor registers and processor-register control circuitry. The processor-register control circuitry comprises a plurality of status registers, each status register corresponding to a different respective deferred-push register. The processor-register control circuitry is configured to: detect a write of a new value to a register of the deferred-push registers; and determine whether the status register for the deferred-push register has a first value, indicative of an unsaved status for the deferred-push register. The processor-control circuitry is configured, when the status register has the first value, to: read a current value from the deferred-push register before the writing of the new value to the deferred-push register completes; write the current value to a memory; and set the status register for the deferred-push register to a second value, indicative of a saved status for the deferred-push register.

An image processing apparatus, comprises a hardware processor and a display part that displays a plurality of display areas assigned to respective users, and arranges and displays operation keys associated with jobs in the respective display areas. The hardware processor registers and manages, for each user, a setting value of a setting item to be applied to a job. When the operation key in any one of the plurality of display areas is operated, the hardware processor identifies a user based on the display area in which the operation key is operated, reads the setting value registered for the identified user, and reflects the setting value as an initial value of the setting item to be applied to the job.