48 results about "Processor register" patented technology

The invention provides a communication method of a TPM (Trusted Platform Module), the TPM, a single board and equipment, and is applied to the technical field of computers, the TPM comprises a TPM logic module, a receiving buffer, a TPM register and a processor, and the TPM register is a storage space divided from a memory of the TPM. The TPM logic module receives a TPM register write command sent by the host and stores the effective load of the write command to the receiving buffer, and the effective load of the TPM register write command is part of or all of the content forming TPM command data; when the data in the receiving buffer reaches a first data volume threshold value, the processor transfers and stores the data in the receiving buffer into a TPM (Trusted Platform Module) register; when all contents of the TPM command data are stored in the TPM register, the processor executes the TPM command data. The problem that TPM hardware cost is high due to the fact that a pure hardware scheme is adopted in TPM communication in the related technology can be solved.

Apparatuses, methods, and systems are disclosed for registering with a core network after NSWO authentication. One apparatus includes a processor coupled to a transceiver, the processor configured to cause the apparatus to connect to a WLAN AN using credentials associated with a network, including performing a first authentication procedure without registering the apparatus with the network. The processor determines to register with the network and the transceiver sends a first message including a first container derived based on information generated during the first authentication procedure, where the first message initiates registration with the network. The transceiver receives a second message including a second container derived based on information generated during the first authentication procedure. The processor registers with the network based on validating the second container.

3D image data of a skeletal portion is acquired. While a portion of a tool is disposed at a first location along an insertion path, first and second x-rays are acquired from first and second image views. A processor registers the x-rays with the 3D image data, identifies a location of a tool within the x-rays, and computes an anticipated forward path of the tool within the 3D image data from the x-rays. The tool is moved to a second location along the insertion path and an additional x-ray is acquired from a single image view. The processor facilitates identifying if the tool has deviated from the anticipated forward path by registering the additional x-ray to the 3D image data and identifying a location of the portion of the tool within the additional x-ray. Other embodiments are also described.

A method for operating secure computer processes includes storing a local encryption key in a register of a processor. The local encryption key is stored in a masked state. The method further includes receiving, from a memory communicating with the processor, an operational encryption key. The method includes encrypting the operational encryption key using the local encryption key and an initialization vector to generate an encrypted operation key. The local encryption key is unmasked prior to encrypting the operational encryption key. Further, the method includes storing the encrypted operational key, the initialization vector, and a verification hash value in the memory. The method includes decryption of symmetric operational keys directly to processor registers without using memory. The method includes decryption of asymmetric operational keys. In the method, the asymmetric key material is decrypted temporarily to memory and that memory is sanitized following the use of the key.

The invention discloses a fault processing method and device, equipment and a medium, and belongs to the technical field of servers, and the method comprises the steps: setting a security network configuration item and an error processing configuration item for a manager port, and obtaining processor register information in response to fault alarm information received through a manager, the processor register information comprises a current fault diagnosis state, and whether fault diagnosis source data are collected or not is judged according to the current fault diagnosis state; in response to the collected fault diagnosis source data, judging whether the system is subjected to soft restart or not according to the error processing configuration item; and in response to soft restart of the system according to the security network configuration item, determining a fault type according to the fault diagnosis source data, and performing automatic analysis processing on the fault according to the fault type. Through compatibility of hardware and software, after a fault occurs, the manager can automatically collect fault source data and process the fault, and the correctness of fault processing is improved.

In an example, a system includes a processor, where the processor includes a plurality of processor registers, and where the processor is configured to execute a first instruction in a first execution context. The processor is also configured to receive a PRESERVE instruction that indicates at least one processor register among the plurality of processor registers. The processor is configured to, responsive to the PRESERVE instruction, preserve parameters in the at least one processor register and clear other processor registers in the plurality of processor registers in the first execution context. The processor is also configured to execute a second instruction in a second execution context.

A device may have a processor to execute a first process comprising a plurality of instructions; a plurality of processor registers to store data associated with one or more of the plurality of instructions; and a context switch instruction, executable by the processor, to move a contiguous set of the plurality of processor registers to or from a memory corresponding to a given memory address, wherein the contiguous set of the plurality of processor registers comprises at least two processor registers and is a proper subset of a total number of processor registers available in the device.

In an example, a system includes a processor, where the processor includes a plurality of processor registers, and where the processor is configured to execute a first instruction in a first execution context. The processor is also configured to receive a PRESERVE instruction that indicates at least one processor register among the plurality of processor registers. The processor is configured to, responsive to the PRESERVE instruction, preserve parameters in the at least one processor register and clear other processor registers in the plurality of processor registers in the first execution context. The processor is also configured to execute a second instruction in a second execution context.

The invention discloses a closed source software system behavior description method based on virtualization, which comprises the following steps of: starting a VMX mode, and configuring a processor register to support a virtualization environment; a binary instruction stream of the closed source software is analyzed, and a real function entry address of the target is obtained; setting an INT3 breakpoint at the function entry address, and storing an original instruction; and breakpoint triggering information is received and processed through the Hypervisor layer. According to the method, the execution process of the closed source software is captured and analyzed in the virtual environment, the analysis process reduces the dependence on the symbol table, the system call sequence is modeled and analyzed in combination with the Markov chain model, the operation behavior of the closed source software is accurately described, and in addition, the operation efficiency of the closed source software is improved. According to the method, regular behaviors of normal applications can be found, and potential abnormal calling and malicious behaviors can be identified in time, so that a customization function is realized according to requirements, and a reliable basis is provided for system security monitoring and behavior analysis.

The invention provides a vehicle-mounted black box protection system, a control method, a storage medium and a product. The vehicle-mounted black box protection system comprises a shell assembly, a sensor module, a lock catch fusing mechanism and a circuit board, the circuit board comprises a processor, a register, a memory and a power supply; the lock catch fusing mechanism is installed between the inner wall of the shell assembly and the circuit board, and the sensor module is arranged on the shell assembly; the lock catch fusing mechanism is connected with the register and the memory; when the sensor module detects that the shell is opened illegally, a sensing signal is triggered and sent to the processor, the processor controls the lock catch fusing mechanism to be powered on, and therefore the lock catch fusing mechanism works to fuse the register and the storage. Therefore, when the case is detected to be opened illegally, the automatic fusing mechanism of the internal circuit board can destroy the hardware environment for data storage in time, so that the data cannot be tampered, and the integrity and authenticity of the data recorded by the data recording system (EDR) are ensured.

One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.

The invention discloses a data processing method and device for auxiliary debugging of a processor. The method is applied to an Intel C600 platform to achieve analysis of processor MCE errors and comprises the steps that when auxiliary debugging request data are obtained, error report data are obtained, and the error report data are report data used for representing errors of an error reporting processor; performing identification processing on the error report data based on register characteristics to obtain register state data which are data used for representing processor register contents; and performing debugging positioning processing on the register state data, and generating an auxiliary debugging report according to a debugging positioning result. The method comprises the following steps: obtaining processor register data, and carrying out debugging positioning on the register data to obtain processor debugging positioning result data; the problem that in the prior art, the efficiency of analyzing the abnormal error code of the processor of the downtime equipment through an analysis tool is low is solved, and the technical effect of efficiently analyzing the downtime equipment is achieved.

A method of preloading address translation information directly into cache memory of an IOMMU includes storing the address translation information in a register set of memory management input / output registers of an input-output memory management unit and loading the address translation information into cache memory of the input-output memory management unit. The address translation information includes a virtual address and a corresponding physical address of system memory of a computing system. The address translation information is sent by software being executed by a processor of the computing system. The address translation information is received directly from the processor.

Provided is a method for a secure execution of a first instruction by a processor of an electronic system comprising fetching said first instruction in an execution pipeline of the processor, and determining if said first instruction to be executed is a load instruction to be protected for loading protected data, or a store instruction to be protected for storing protected data, and associated security information from said at least one memory to the processor registers. The method includes executing sequentially at least a first operation, a second operation and a third operation, depending on whether said first instruction is a load instruction or store instruction. Other embodiments disclosed.

The present application relates to the technical field of digital data processing and digital signal processor computing power allocation, and discloses a fiber communication abnormal peak early warning method based on modulation instability gain spectrum, comprising: mapping link parameter data stream to generate discrete topological node array according to set distance resolution; generating resonance proximity data according to disturbance and resonance angular frequency data of each node; when the resonance proximity data reaches the set hard logic threshold, determining that the corresponding node is an active node, and directing the computing resource to the local slice composed of the active node and adjacent nodes; calculating the risk characteristic quantity by calculating the multi-dimensional spectrum matrix of the equivalent parameter sequence in the local slice, and outputting the early warning signal when the risk level threshold is reached; the present application avoids data divergence caused by global synchronous calculation through local allocation of computing resource space dimension, reduces the computing power overhead of processor register, and improves the parameter convergence stability of multi-dimensional parameter matrix calculation under noise interference working condition.

The invention discloses a PAD multiplexing device for a system-on-chip. The PAD multiplexing device comprises a processor, a register module, a signal selection module and a plurality of PAD modules. The register module comprises a plurality of register units, and effective state values or ineffective state values are configured through one register unit connected with the signal selection module for a plurality of function modes of the PAD module. And aiming at each output function mode supported by the PAD module, the processor is respectively provided with an output signal channel connected to the signal selection module, and the output signal channel is used for outputting a processor signal. And aiming at each function mode of input supported by the PAD module, the processor is respectively provided with an input signal channel connected with the signal selection module. And the signal selection module is connected with each PAD module, and the signal selection module controls the signal output of the corresponding output signal channel and / or the signal input of the input signal channel according to the state value output by the register module, so that multiplexing of the PAD modules can be realized, and one PAD module can support multiple functional modes.

A TPM communication method, a TPM, a single board, and a device, applied to the technical field of computers. The TPM comprises: a TPM logic module, a receiving buffer, a TPM register, and a processor. The TPM register is a storage space obtained by dividing a memory of the TPM. The method comprises: the TPM logic module receives a TPM register write command sent by a host, and stores the payload of the write command to the receiving buffer, wherein the payload of the TPM register write command is part or all of the content forming TPM command data; when data in the receiving buffer reaches a first data volume threshold, the processor transfers the data in the receiving buffer to the TPM register; and when all the content of the TPM command data has been stored in the TPM register, the processor executes the TPM command data. In this way, the problem in the related art of high TPM hardware costs caused by using a hardware-only solution for TPM communication can be solved.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for implementing a zero knowledge prover are disclosed. In one aspect, a method includes the actions of accessing an instruction set of a processor. The actions include generating a representation of a computing instruction using Boolean logic operations. The actions include assigning a polynomial constraint of a group of polynomial constraints to each Boolean logic operation. The actions include providing, to the processor, an executable program that includes various computing instructions and a request to execute the executable program. The actions include monitoring a value of a register of the processor. The actions include determining whether the value of the register complies with polynomial constraints of the group of polynomial constraints that correspond to instructions performed on the register. The actions include determining whether the execution of the executable program by the processor has been interfered with.

To provide an information management device and an inspection system capable of easily performing inspection.SOLUTION: An information management device according to an embodiment has a communication interface, a first storage unit, a second storage unit, and a processor. The communication interface communicates with an information acquisition device which acquires information from a to-be-inspected baggage as an inspection object. The first storage unit has a brand database which stores brand information regarding brands as detection objects. The second storage unit has a baggage information database which stores baggage information including information acquired from the to-be-inspected baggage by the information acquisition device. When an inspection result indicates that the to-be-inspected baggage includes an article of a brand on which brand information is stored in the brand database, the processor registers baggage information on the to-be-inspected baggage including an image of a brand display portion on the to-be-inspected baggage and the inspection result on the to-be-inspected baggage.SELECTED DRAWING: Figure 2

The trusted platform module (TPM) includes a TPM logic circuit, a receive buffer, a TPM register, and one or more processors. The TPM register is a storage space obtained by dividing a memory of the TPM. The TPM logic circuit receives a TPM register write command from a host and stores a payload of the write command into the receive buffer. The payload of the TPM register write command is a part or all of content forming TPM command data. When data in the receive buffer reaches a first data amount threshold, the processor dumps the data in the receive buffer into the TPM register. When all the content of the TPM command data is stored in the TPM register, the one or more processors execute the TPM command data.

The application discloses a processor supporting register release, a register release method, a display card and equipment, and belongs to the technical field of register management. The processor comprises a plurality of registers, an allocation management unit and a resource management unit. The allocation management unit is used for allocating at least two register sets for a first thread group, and each register set in the at least two register sets comprises at least one register in the plurality of registers. The resource management unit is used for releasing a first register set in response to the end of use of all registers in the first register set by the first thread group, and the first register set is one register set in the at least two register sets. The processor supports early release of the first register set when the first thread group ends the use of all registers in the first register set, thereby avoiding the problem of low utilization of register resources caused by long-term occupation of the first register set by the first thread group.

Disclosed herein is a new technique for providing a storage controller with variable interface communication speeds to allow the storage controller to set different communication speeds and frequencies for different communication channels between the storage controller and respective memories. A controller comprises: a processor; registers; and a clock generator configured to generate clock signals respectively for multiple communication channels based on values stored in the registers. The controller is configured to communicate with non-volatile memories through the communication channels respectively using the clock signals.

The invention discloses a register data backup method of a processor and a computer readable storage medium. The method comprises the following steps: determining a plurality of target backup registers based on a data backup requirement of a general register file; generating backup register masks corresponding to a plurality of target backup registers, and determining a backup demand space; determining a backup initial address of a target memory space of the processor based on a preset backup rule, and generating a backup end point idle address according to the backup demand space and the backup initial address; and the compiler generates a register backup instruction according to the backup register mask, the backup initial address and the backup terminal idle address, so that the processor backs up the to-be-backed-up data of the multiple target backup registers to the target memory space based on the register backup instruction. According to the method, data backup of a plurality of registers is completed through one register backup instruction, the data backup efficiency is improved, meanwhile, the number of instructions is reduced, and the utilization rate of instruction storage space is optimized.

A device may have a processor to execute a first process comprising a plurality of instructions; a plurality of processor registers to store data associated with one or more of the plurality of instructions; and a context switch instruction, executable by the processor, to move a contiguous set of the plurality of processor registers to or from a memory corresponding to a given memory address, wherein the contiguous set of the plurality of processor registers comprises at least two processor registers and is a proper subset of a total number of processor registers available in the device.

The application discloses a kind of hardware perception type vector quantization calculation fusion acceleration instruction parallel processing system and method.For the memory bandwidth bottleneck problem of asymmetric distance calculation in large-scale vector retrieval, the application is inside processor register, 8-bit quantization encoding is loaded, zero extension to 32-bit floating point precision, affine correction based on quantization offset and scale factor, and distance accumulation operation for query vector are fused into single instruction multiple data stream driven in-register execution pipeline.The method eliminates the intermediate memory copy and register overflow operation in the traditional scheme, improves the throughput capacity of vector retrieval and processor resource utilization under the premise of maintaining the calculation accuracy.

The invention discloses a method for achieving exception protection based on a signal processing mechanism, a medium and electronic equipment, and the method comprises the steps that in the program running process, when preset error type information is generated, a signal processor registered according to the preset error type information receives the preset error type information; the signal processor obtains current operation information and packages the current operation information into abnormal log information; the signal processor determines a processing rule corresponding to the preset error type information; under the condition that the processing rule is determined to return the storage point, the signal processor acquires information of the storage point which needs to be returned currently; and the signal processor loads the information of the storage point and executes corresponding operation according to the abnormal protection behavior corresponding to the storage point. According to the technical scheme provided by the invention, the phenomenon that the program crashes can be avoided, and problems in the program can be quickly and accurately checked, so that the stability and robustness of the program can be improved.

A processing device (20) has a processor (200) including a plurality of delay push processor registers (214) and a processor register control circuit (220, 222, 224, 226, 228). The processor register control circuit (220, 222, 224, 226, 228) includes a plurality of status registers (226), each status register (226) corresponding to a respective different delay push register (214). The processor register control circuit (220, 222, 224, 226, 228) is configured to detect a write of a new value to a register (214) in the delay push registers (214) and determine whether a status register (226) of the delay push register (214) has a first value indicating an unsaved state of the delay push register (214). The processor control circuit (220, 222, 224, 226, 228) is configured, when the status register (226) has the first value, to read a current value from the delay push register (214) before completion of the write of the new value to the delay push register (214), write the current value to a memory (202), and set the status register (226) of the delay push register (214) to a second value indicating a saved state of the delay push register (214).

Disclosed herein is a new technique for providing a storage controller with variable interface communication speeds to allow the storage controller to set different communication speeds and frequencies for different communication channels between the storage controller and respective memories. A controller comprises: a processor; registers; and a clock generator configured to generate clock signals respectively for multiple communication channels based on values stored in the registers. The controller is configured to communicate with non-volatile memories through the communication channels respectively using the clock signals.