12 results about "Lower field" patented technology

This application relates to the field of air respirator masks, and more particularly to an air respirator mask with a quickly fixed Bluetooth microphone, comprising a base, a lens mounted on the outside of the base, and a mouth and nose mask mounted on the lower side of the base. The lens abuts against the side wall of the mouth and nose mask, and a receiving cavity is formed on the upper side of the mouth and nose mask. The Bluetooth microphone is detachably fixed to the inner wall of the receiving cavity. This application has the effect of reducing obstruction of the worker's lower field of vision by changing the installation method of the Bluetooth microphone, thereby increasing the worker's full field of vision and binocular field of vision.

The invention provides a rectangular field-of-view design method for an ultraviolet non-line-of-sight communication receiving end and application thereof, and belongs to the technical field of wireless optical communication, the method comprises the following steps: pre-determining the center distance length of a light shield and the upper field-of-view angle, the lower field-of-view angle, the left field-of-view angle and the right field-of-view angle of a rectangular receiving field-of-view; based on the center distance length, the upper view field angle, the lower view field angle, the left view field angle, the right view field angle and the width and length of the rectangular light sensing surface, calculating structural parameters of a light shield used for generating the rectangular receiving view field; wherein the structural parameters comprise the upper and lower edge lengths, the left and right edge lengths and the position of a vertical center point of a larger rectangular opening of the light shield. Through the design of the rectangular view field and the accurate matching of the rectangular light-sensitive surface, the photon receiving efficiency is remarkably improved, stray light and electromagnetic interference are effectively inhibited, and thus the signal-to-noise ratio of weak light signal detection and the system sensitivity are improved.

The invention relates to the technical field of large ring piece detection, in particular to a portable detection method and instrument for flatness and machining allowance of a large ring piece, and the method comprises the steps: firstly, building a workpiece coordinate system fixedly connected with the ring piece, rapidly obtaining circumferential thickness distribution based on the coordinate system, generating an upper end face contour curve, and carrying out the detection of the flatness and machining allowance of the ring piece; through real-time analysis of the contour curve, the defect types such as overall inclination, local concave-convex or periodic wave deformation and the like are synchronously diagnosed, then different fine scanning strategies are adaptively triggered according to diagnosis results to obtain corresponding high-precision morphology data, and finally, the high-precision morphology data are obtained. And fusing multi-source data to calculate an end face flatness error and a global minimum machining allowance, and directly judging the process machinability of the ring piece according to the end face flatness error and the global minimum machining allowance. According to the invention, the closed loop from rapid detection and intelligent diagnosis to process decision is realized, and the problems of low field detection efficiency, inaccurate defect judgment and disjunction between detection and processing decision of a large ring piece are solved.

A semiconductor device includes: a channel layer; a barrier layer disposed on the channel layer; a gate electrode disposed on the barrier layer; a source electrode and a drain electrode connected to the channel layer and on respective sides of the gate electrode; lower field distribution patterns spaced between the gate electrode and the drain electrode; and an upper field distribution pattern spaced from the lower field distribution patterns on the lower field distribution patterns, and connected to the source electrode.

A stacked field effect transistor structure includes a lower field effect transistor with a lower first drain-source region, a lower second drain-source region, and at least one lower nanosheet channel region interconnecting the lower drain-source regions. An upper field effect transistor has an upper first drain-source region, an upper second drain-source region, and at least one upper nanosheet channel region interconnecting the upper drain-source regions. A high-K metal gate structure surrounds at least a portion of the lower and upper nanosheet channel regions. A middle dielectric isolation region separates the upper and lower field effect transistors. Gate spacers are on sides of the gate structure, which includes gate metal, and high-K liner material on the lower and upper nanosheet channel regions, and in a first wall region extending up the gate spacers next to the lower field effect transistor no further than the middle dielectric isolation region.

The method including forming a first photoresist (PR) pattern by exposing first field areas of a first PR layer, forming a second PR pattern by exposing first top field areas and first bottom field areas of a second PR layer, measuring a first top intra-field overlay for the first top field areas and a first bottom intra-field overlay for the first bottom field areas, and determining a top intra-field correction parameter and a bottom intra-field correction parameter based on the first top intra-field overlay and the first bottom intra-field overlay, respectively, may be provided.

The present disclosure provides a method of manufacturing a semiconductor device and a vertically stacked semiconductor device. The method includes: arranging lower and upper field effect transistors on a substrate, an upper surface of the substrate is connected to lower surfaces of a lowest gate stack and a source / drain layer in the lower field effect transistor; forming a fully silicided layer on exposed lower surfaces of the gate stack and the source / drain layer in the lower field effect transistor; patterning the fully silicided layer to form an opening exposing the lower surface of the lowest gate stack in the lower field effect transistor and a silicided pattern connected to the lower surface of the source / drain layer in the lower field effect transistor; filling the opening with a dielectric material to serve as a lower isolation layer of the gate stack; arranging a contact hole connected to the silicided pattern.

A stacked field effect transistor structure includes a lower field effect transistor including a lower first drain-source region, a lower second drain-source region, at least one lower channel region interconnecting the lower first and lower second drain-source regions, and a lower gate structure adjacent the at least one lower channel region. An upper field effect transistor includes an upper first drain-source region, an upper second drain-source region, and at least one upper channel region interconnecting the upper first and upper second drain-source regions, and an upper gate structure adjacent the at least one upper channel region. A gate interconnect connects the lower gate structure to the upper gate structure. The gate interconnect includes: a gate contact directly connected to the lower gate structure; and a contact plug directly connected to the top gate structure and electrically coupled to the gate contact.

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a channel layer; a barrier layer disposed on the channel layer; a gate electrode disposed on the barrier layer; a source electrode and a drain electrode connected to the channel layer and on respective sides of the gate electrode; lower field distribution patterns spaced apart from each other between the gate electrode and the drain electrode; and an upper field distribution pattern spaced apart from the lower field distribution pattern on the lower field distribution pattern, and connected to the source electrode.