39 results about "Dual gate" patented technology

A dual gate IGBT is presented, where the active region includes a first section and a second section. Both sections may be controlled by two control signals. For example, the active region or a second section of the active region comprises a second barrier region. For example, the first section has a first characteristic transfer curve, with load current in dependence of the voltage of the first control signal, and the second section has a second characteristic transfer curve, with load current in dependence of the voltage of the first control signal. At least the second characteristic transfer curve is changeable based on the voltage of the second control signal.

The application discloses a double-gate pixel architecture, a display panel and a display device, and the double-gate pixel architecture comprises a pixel array, a plurality of data lines and a plurality of gate lines, and the gate lines are arranged on the upper and lower sides of each row of sub-pixels in pairs; wherein the data line connection architecture of the pixel array is configured as follows: the polarities of data line signals accessed by any two adjacent sub-pixels in the row direction and the column direction are opposite. The application successfully realizes 1Dot inversion driving through the specific double-gate pixel connection architecture, so that adjacent sub-pixels generate opposite coupling effects on the common electrode voltage, effectively suppresses the one-way deviation of the common electrode voltage and promotes the rapid recovery of the common electrode voltage to the design value, thereby fundamentally and significantly improving the picture flicker problem under low-frequency driving and improving the display quality.

A semiconductor structure includes a two-dimensional array of unit cell structures overlying a substrate. Each unit cell structure includes an active layer, a gate dielectric underlying the active layer, two gate electrodes underlying the gate dielectric, and two source electrodes and a drain electrode overlying the active layer. Word lines underlie the active layers. Each unit cell structure includes portions of a respective set of four word lines, which includes two word lines that are electrically connected to two electrodes in the unit cell structure and two additional word lines that are electrically isolated from the two electrodes in the unit cell structure.

The application discloses a double-gate driving liquid crystal display array, which comprises a sub-pixel array arranged in a matrix form, each row of the sub-pixel array is composed of a plurality of transverse arrangement units, a pair of gate driving lines are arranged in a wave shape and periodically pass through between the second and third sub-pixels of each transverse arrangement unit and between adjacent transverse arrangement units; the pair of gate driving lines comprises a first gate driving line arranged on the upper side and a second gate driving line arranged on the lower side, and the sub-pixel array further comprises edge gate driving lines arranged on the top and the bottom, the edge gate driving lines are connected with the remaining sub-pixels which are not connected in the top row and the bottom row. By increasing two gate driving lines and changing the connection mode of the gate driving lines, the gate driving lines can be connected with the liquid crystal molecules of the same color with opposite polarities between adjacent rows in the double-gate driving liquid crystal display array, so that the load requirement during the polarity switching of the liquid crystal molecules in the double-gate driving is reduced.

According to the high-resolution and lighting effect optimization type display array substrate and the preparation method thereof, metal layer wiring is optimized, that is, a grid signal line is arranged on a third metal layer and is vertically overlapped with a TFT grid, and the shading area is reduced; a touch signal line moves downwards to a first metal layer, the touch signal-to-noise ratio is increased, a data signal line is additionally arranged on the first metal layer and is equipotential with a data signal line of a second metal layer, a double-layer data line driving structure design is formed, and the touch signal-to-noise ratio is increased under the condition that the thickness of the metal layer, the width of the metal line, the metal material and the like are not increased. Therefore, the impedance of the data line can be greatly reduced to half of the original impedance, the IC driving capability is effectively improved, 8K-resolution driving can be supported at most, and the problem that the S-IC driving capability is insufficient due to the fact that the load of the data line is increased under the dual Gate driving design of a high-resolution panel is solved.

Achieving high gain and low noise in RF circuits. [Solution] A III-N dual gate device and a method for manufacturing a III-N dual gate device. An example semiconductor device includes a III-N back barrier, a III-N channel layer on the III-N back barrier, and a two-dimensional electron gas (2DEG) channel in the III-N channel layer. The semiconductor device includes a source contact and a drain contact, and includes a first gate contact and a second gate contact between the source contact and the drain contact. Between the first gate contact and the second gate contact, the semiconductor device includes an n+GaN contact coupled to the III-N channel layer in a connection region.

A synapse device may include an oxide semiconductor transistor divided into a write transistor and a read transistor. The write transistor is an oxide semiconductor transistor having a dual gate including a bottom gate located below a thin oxide semiconductor layer and a top gate located above the thin oxide semiconductor layer.

The utility model provides a kind of double door transmission valve of semiconductor processing etching equipment, belong to semiconductor transmission valve technical field, to solve the tiny dust generated by the friction of sealing element and contact surface, long time use is easy to cause dust particle accumulation on the sealed contact surface, can accelerate wear and tear, while dust particle can float into the cavity or transmission channel of valve body, pollute semiconductor piece surface, can affect product yield problem, the invention includes main valve and the drive seat installed in the middle below main valve, the invention can utilize the double measures of directional blowing and directional suction, can greatly reduce particle residue, reduce pollution from the source of particle generation, guarantee the effect of dust removal, improve semiconductor product yield, while nitrogen of inert gas can be cleaned in the inner surface of the fitting groove, to ensure the neatness and smoothness in the fitting groove, ensure that semiconductor transmission process is always in high vacuum, high-clean environment, guarantee transmission stability and consistency.

A memory device includes at least one transistor having a dual gate structure including a first gate metal and a second gate metal, where the first gate metal has a work function of less than 4.55 eV and the second gate metal has a work function of greater than 4.55 eV. A method of forming the memory device is also provided.

The application relates to the field of MOS semiconductor technology, and discloses a self-aligned double-gate MOSFET which is composed of a plurality of MOS cells connected in parallel, a single MOS cell sequentially comprises a drain, a semiconductor epitaxial layer, a gate and a source from bottom to top, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P well layer and a P+ layer, a P-type doped area is formed in the inside of the N drift layer and below the gate through ion implantation, and the P-type doped area is in ohmic contact with the gate. The application constructs the P-type doped area below the gate and realizes ohmic contact, so that the gate contact resistance is remarkably reduced; meanwhile, a self-aligned N-type doped gate is deposited in the P-type area, so that the gate control structure is accurately aligned with the channel position. The design not only improves the control ability of the gate on the channel carriers, but also simultaneously reduces the conduction loss and enhances the switching response speed.

The utility model provides a kind of high-resolution and light efficiency optimization type display array substrate, by optimizing metal layer wiring, i.e., gate signal line is arranged in third metal layer and is vertically overlapped with TFT gate, reduces light shielding area;Touch signal line is moved to first metal layer, improves touch signal-to-noise ratio, and data signal line is additionally provided in first metal layer, and the data signal line of second metal layer is equipotential, forms double-layer data line driving structure design, without increasing metal layer thickness, metal line width, metal material and the like, data line impedance can be reduced to original half substantially, effectively improves IC driving capability, can support 8K resolution driving at most, breaks through the problem that S-IC driving capability is insufficient due to data line load improvement under high-resolution panel dual Gate driving design.

The application belongs to the technical field of display driving, and particularly relates to an array substrate, a display panel and a driving method, the array substrate comprising 2N rows of scanning lines and M columns of pixel columns, the pixel column comprising a data line, a constant voltage line and N rows of pixel circuits; wherein the nth row of pixel circuits comprises a first sub-pixel unit, a second sub-pixel unit and a control unit, the control unit being configured to apply a constant voltage on the constant voltage line to a pixel electrode of the first sub-pixel unit before the first sub-pixel unit writes the first data voltage, and to apply the constant voltage on the constant voltage line to a pixel electrode of the second sub-pixel unit before the second sub-pixel unit writes the second data voltage; the application effectively improves the problem of insufficient charging when high refresh rate display is performed under the Dual Gate architecture, eliminates bright and dark lines under specific pictures such as water blue pictures, and improves the picture quality uniformity of the display panel.

The invention discloses a display driving framework and a time sequence control method thereof, a display panel and display equipment, and relates to the technical field of display, the display driving framework comprises a pixel array formed by a plurality of pixels distributed in an array, a gate driving circuit and a time sequence control module, the pixels are composed of sub-pixels of different colors which are sequentially arranged in the column direction, and the colors of the sub-pixels in the same row are the same; the gate driving circuit is electrically connected with the sub-pixels in the corresponding rows through the gate scanning lines in the rows; the time sequence control module is electrically connected with the gate driving circuit, and the time sequence control module is configured to respond to a preset double-gate line driving mode, provide a gate driving time sequence for the gate driving circuit and control the gate driving circuit to perform gate driving on the pixel array according to the gate driving time sequence, therefore, grid scanning lines corresponding to two sub-pixel rows which belong to the same color and are spaced by two rows in the column direction are opened at the same time, and a double-grid-line driving mode is compatible under a three-row driving framework.

The application relates to a double-gate structure, a field oxygen structure and a manufacturing method of a semiconductor device, and the manufacturing method of the double-gate structure comprises the following steps: obtaining a wafer formed with a first gate dielectric layer and a second gate dielectric layer; forming a gate material layer on the first and second gate dielectric layers; forming a photoresist anti-reflection layer on the gate material layer; coating photoresist on the photoresist anti-reflection layer, exposing by using a polysilicon gate photoetching plate, developing the photoresist, then etching the photoresist anti-reflection layer and the gate material layer, forming a first gate on the first gate dielectric layer and a second gate on the second gate dielectric layer, and the first gate dielectric layer extends from the bottom of the first gate on both sides; removing the photoresist, then dry etching the first gate dielectric layer extending from the bottom of the first gate, and the photoresist anti-reflection layer is used as a blocking layer of the dry etching. The application uses the photoresist anti-reflection layer as an etching blocking layer, removes the excess first gate dielectric layer extending out of the first gate by dry etching, and ensures that the device does not break the trench.

The invention relates to the technical field of data preprocessing, and provides a double-door sentry type entrance dirty data cleaning and error classification method and system. The double-door sentry type entrance dirty data cleaning and error classification method comprises the following steps: calculating the root mean square of each window; calculating spectrum dispersion; if the minimum value of the root-mean-square is smaller than the idle calibration value of the production line or the spectrum dispersion is larger than a spectrum dispersion threshold value, the event window is discarded; calculating a vibration peak value or a root-mean-square of the offline industrial sensing signal data, and if the vibration peak value or the root-mean-square exceeds a first threshold value, determining that the data is signal distortion data; performing consistency judgment on the sampling rate of the off-line industrial sensing signal data, and screening sampling rate error data; and calculating a cross correlation coefficient and an energy difference between the current event window and the previous frame event window, and if the cross correlation coefficient is smaller than a second threshold value and the energy difference is more than K times, judging that the data is packet loss data. The closed loop of training data self-cleaning and error reutilization in the offline environment of the local area network is realized.

The present disclosure relates to semiconductor structures, memory arrays, and manufacturing methods thereof. The semiconductor structure includes a first dielectric layer, a semiconductor layer, and a dual gate structure. The semiconductor layer is disposed over the first dielectric layer. The semiconductor layer includes a source region, a drain region, and a body region between the source region and the drain region. The dual gate structure is disposed over the body region. The dual gate structure includes a first gate, a second gate, and a spacing material. The second gate includes a first horizontal section laterally distanced from the first gate. The spacing material is disposed between the first gate and the first horizontal section of the second gate.

The invention discloses a gallium integrated circuit chip and a preparation method thereof, and belongs to the technical field of semiconductor device integration. The gallium integrated circuit chip comprises a basic circuit module formed by connecting a main pipe device and an auxiliary pipe device, a drain electrode of the auxiliary pipe device is connected with a grid electrode of the main pipe device, and source electrodes of the auxiliary pipe device and the main pipe device are connected together; grid electrodes of the main tube and the auxiliary tube receive inverted input signals; when the main pipe generates grid voltage ringing due to coupling of adjacent circuit switches, the conducted auxiliary pipe provides a discharge path for grid charges of the main pipe, and misconduction is restrained. Preferably, the auxiliary tube and the main tube are integrated in a monolithic manner, and a high-reliability device structure comprising a cylindrical P-GaN region, double grids and a field plate is adopted; and the chip can be integrated with a phase inverter formed by a GaN device, so that a phase inversion control signal is generated locally, and external driving is simplified. The invention also provides a corresponding preparation method. On the premise that the switching speed is not sacrificed, the ringing problem of the gallium nitride power integrated circuit is effectively solved, and the reliability and the integration degree of the system are remarkably improved.

The invention provides a dual-gate transistor and a display device including the same. The dual gate transistor includes a first gate electrode disposed in an inverted tapered shape on a first gate insulating layer, a buffer layer disposed to cover the first gate electrode, an active layer disposed on the buffer layer, a second gate insulating layer disposed to cover the active layer, and a second gate electrode disposed in a tapered shape on the second gate insulating layer.

Embodiments relate to a vertical transistor dual gate biosensor. A technique includes forming a first vertical field-effect transistor (VFET) having a first gate and forming a second VFET having a second gate. The first and second gates include a shared trench formed in between the first VFET and the second VFET, where the first gate includes a first sidewall of the shared trench, and where the second gate includes a second sidewall of the shared trench. The first sidewall is opposite the second sidewall in the shared trench.

A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.

A pixel circuit includes a first transistor including a 1-1-th electrode connected to a first node, a 1-2-th electrode connected to a second node, a 1-1-th dual gate electrode connected to a third node, and a 1-2-th dual gate electrode connected to a fourth node. The pixel circuit further includes a light emitting diode including an anode electrode connected to the second node and a cathode electrode receiving a low potential driving voltage and emitting light according to a driving current transmitted from the first transistor in an emission period. The pixel circuit further includes: a first capacitor connected between the second node and the third node, and a compensation circuit which is connected to the first transistor to sample a threshold voltage of the first transistor to generate the driving current in which the threshold voltage is compensated, in a sensing period before the emission period.

The invention relates to a semiconductor structure, a memory array and a manufacturing method thereof. The semiconductor structure comprises a first dielectric layer, a semiconductor layer and a bigrid structure. The semiconductor layer is arranged on the first dielectric layer. The semiconductor layer includes a source region, a drain region, and a body region between the source region and the drain region. The dual gate structure is disposed on the body region. The dual-gate structure includes a first gate, a second gate, and a spacer material. The second gate includes a first horizontal section laterally spaced from the first gate. A spacer material is disposed between the first gate and the first horizontal section of the second gate.

Various embodiments herein include a thin film transistor (TFT) including a channel layer stack having layers of different mobility. Since the carrier density in the high mobility channel layer and / or the plurality of high mobility channel layers is higher, the TFTs disclosed herein transport a higher total current through the low mobility and high mobility channel layers, which increases the response speed of the TFTs. The TFT further includes a gate structure disposed over the channel layer stack. The gate structure includes one or more gate electrodes, and thus the TFT is a top gate (TG), dual gate (DG), or bottom gate (BG) TFT. The channel layer stack includes a plurality of layers having different mobility. Layers with different mobility impart various benefits to the TFT. The high mobility layer increases the response speed of the TFT.

The application discloses a kind of breathable conductive material, manufacturing method, semiconductor device and double-gate TFT device, breathable conductive material includes host material and doping material;Host material includes at least one metal oxide, metal oxide is conductive oxide, and the grain size of metal oxide is 1nm-100nm;Doping material includes at least one element or oxide in transition metal and post-transition metal, and the content of doping material is 1%-50% by mass percentage.Doping is carried out in conductive oxide by specific element, so as to change the microstructure of conductive oxide, improve the air permeability of conductive oxide while ensuring its conductivity, so that the electrode made of the breathable conductive material can be applied in semiconductor devices requiring conductivity and air permeability.

The invention relates to a dual-gate power semiconductor device and a method of controlling a dual-gate power semiconductor device. A dual gate IGBT (1) is presented in which an active region (1-2) comprises a first segment region (1-21) and a second segment region (1-22). Both segments can be controlled by means of two control signals (13-21, 13-22). For example, the active region (1-2) or a second segment region (1-22) of the active region (1-2) comprises a second barrier region (115). For example, the first segment (1-21) exhibits a first characteristic transfer curve, i.e., a load current dependent on the voltage of the first control signal (13-21), and the second segment (1-22) exhibits a second characteristic transfer curve, i.e., a load current dependent on the voltage of the first control signal (13-21), wherein at least the second characteristic transfer curve is variable on the basis of the voltage of the second control signal (13-22).

A pixel module, a driving method, and a display device. The pixel module comprises multiple rows and columns of sub-pixels, multiple rows of scanning lines, and multiple columns of data lines; two sub-pixels located in an n-th row are disposed among a (2n-1)-th row of scanning line, a 2n-th row of scanning line, an m-th column of data line, and an (m+1)-th column of data line, wherein n and m are positive integers; each sub-pixel receives a data voltage under the control of a scanning signal; among the sub-pixels electrically connected to the (2n-1)-th row of scanning line and the sub-pixels electrically connected to a (2n+1)-th row of scanning line, the sub-pixels electrically connected to the same column of data line have the same color; and among the sub-pixels electrically connected to the 2n-th row of scanning line and the sub-pixels electrically connected to a (2n+2)-th row of scanning line, the sub-pixels electrically connected to the same column of data line have the same color. When the pixel module is in a dual gate mode, color display errors would not occur when a monochromatic picture is displayed.

A cascode circuit is formed using a high voltage transistor in series with a low voltage transistor. A clamp switch device is used to discharge the gate of the high voltage transistor when the cascode is off. Rate limiting devices may be used control turn on and turn off characteristics of the cascode. Rate limiting devices may be include resistors and / or transistors. The high voltage transistor may be a normally on silicon carbide JFET, for example, and the low voltage transistor may be a silicon MOSFET.

A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.

An embodiment includes a controller and a driver. The controller determines and sets either of a first mode or a second mode. The first mode is set when a direction of a current into a semiconductor element is a forward direction. The second mode is set when the direction of the current into the semiconductor element is a backward direction. The semiconductor includes a reverse conducting IGBT having dual gate electrodes. The diving unit generates independent gate signals for the dual gate electrodes in accordance with the setting of the controller. And the driver drives the dual gate electrodes as to shorten an off time of the semiconductor element in the first mode, and as to shorten a reverse recovery time in a diode operation of the semiconductor device in the second mode.

A display apparatus includes a substrate including a display area on which a display element is disposed, an emission control transistor which is disposed in the display area, includes a first semiconductor layer, and is connected to a pixel electrode of an organic light-emitting diode, a switching transistor disposed in the display area and including a second semiconductor layer, and a first initialization transistor disposed in the display area and including a third semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer each include a silicon semiconductor, the third semiconductor layer includes an oxide semiconductor, and at least one of the emission control transistor, the switching transistor, and the first initialization transistor includes a dual gate electrode.