54 results about "Dual gate" patented technology

A circuit includes an input node configured to receive a gate control signal for controlling a dual gate transistor arrangement, a first output node configured to be coupled to a first gate node of the dual gate transistor arrangement, a first switch coupled between the input node and the first output node, and a second output node configured to be coupled to a second gate node of the dual gate transistor arrangement and coupled to the input node. A control circuit is configured to, upon detecting that the gate control signal indicates a turn-off of the dual gate transistor arrangement, open the first switch for a first predefined time period, and close the first switch after the first predefined time period.

A dual gate IGBT is presented, where the active region includes a first section and a second section. Both sections may be controlled by two control signals. For example, the active region or a second section of the active region comprises a second barrier region. For example, the first section has a first characteristic transfer curve, with load current in dependence of the voltage of the first control signal, and the second section has a second characteristic transfer curve, with load current in dependence of the voltage of the first control signal. At least the second characteristic transfer curve is changeable based on the voltage of the second control signal.

The application discloses a double-gate pixel architecture, a display panel and a display device, and the double-gate pixel architecture comprises a pixel array, a plurality of data lines and a plurality of gate lines, and the gate lines are arranged on the upper and lower sides of each row of sub-pixels in pairs; wherein the data line connection architecture of the pixel array is configured as follows: the polarities of data line signals accessed by any two adjacent sub-pixels in the row direction and the column direction are opposite. The application successfully realizes 1Dot inversion driving through the specific double-gate pixel connection architecture, so that adjacent sub-pixels generate opposite coupling effects on the common electrode voltage, effectively suppresses the one-way deviation of the common electrode voltage and promotes the rapid recovery of the common electrode voltage to the design value, thereby fundamentally and significantly improving the picture flicker problem under low-frequency driving and improving the display quality.

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes: a substrate, a dielectric layer, a first gate structure and a second gate structure. The substrate includes discrete semiconductors arranged at a top of the substrate and extending in a vertical direction. The first gate structure is arranged in a first region of the semiconductor pillar and surrounds the semiconductor pillar. The second gate structure is arranged in a second region of the semiconductor pillar and includes a ring structure and at least one bridge structure. The ring structure surrounds the semiconductor pillar, and the at least one bridge structure penetrates through the semiconductor pillar and extends to an inner wall of the ring structure in a penetrating direction. The dielectric layer is located between the first gate structure and the semiconductor pillar, and between the second gate structure and the semiconductor pillar.

A pixel circuit includes a first transistor including a 1-1-th electrode connected to a first node, a 1-2-th electrode connected to a second node, a 1-1-th dual gate electrode connected to a third node, and a 1-2-th dual gate electrode connected to a fourth node. The pixel circuit further includes a light emitting diode including an anode electrode connected to the second node and a cathode electrode receiving a low potential driving voltage and emitting light according to a driving current transmitted from the first transistor in an emission period. The pixel circuit further includes: a first capacitor connected between the second node and the third node, and a compensation circuit which is connected to the first transistor to sample a threshold voltage of the first transistor to generate the driving current in which the threshold voltage is compensated, in a sensing period before the emission period.

A method of carrier-based modulation with a dual gate bidirectional switch includes the steps of receiving a sine triangle pulse width modulation (PWM) signal; converting the received sine triangle PWM signal from a voltage source inverter (VSI) input to a current source inverter (CSI) output involving vector matching; converting the CSI output to internal model control (IMG) signal pulses; generating a PWM signal for each dual gate bidirectional switches based on the IMG signal pulses; generating two gate signals for each dual gate bidirectional switch; and selectively applying a phase shift or delay between the gate signals applied to a high side of the dual gate bidirectional switch relative to a low side of the dual gate bidirectional switch.

A semiconductor structure includes a two-dimensional array of unit cell structures overlying a substrate. Each unit cell structure includes an active layer, a gate dielectric underlying the active layer, two gate electrodes underlying the gate dielectric, and two source electrodes and a drain electrode overlying the active layer. Word lines underlie the active layers. Each unit cell structure includes portions of a respective set of four word lines, which includes two word lines that are electrically connected to two electrodes in the unit cell structure and two additional word lines that are electrically isolated from the two electrodes in the unit cell structure.

Circuits, devices, and methods related to dual gate transistor arrangements are provided. The circuit comprises an input node (10) configured to receive a gate control signal for controlling the dual-gate transistor arrangement (14), a first output node (11) configured to be coupled to a first gate node (G1) of the dual-gate transistor arrangement (14); a first switch (S1) coupled between the input node (10) and the first output node (11); a second output node (12) configured to be coupled to a second gate node (G2) of the dual-gate transistor arrangement (14) and to the input node (10). Furthermore, the control circuit (15) is configured to open the first switch (S1) for a first predefined period of time upon detecting that the gate control signal is indicative of turning off the dual-gate transistor arrangement (14), and to close the first switch (S1) after the first predefined period of time.

The application discloses a double-gate driving liquid crystal display array, which comprises a sub-pixel array arranged in a matrix form, each row of the sub-pixel array is composed of a plurality of transverse arrangement units, a pair of gate driving lines are arranged in a wave shape and periodically pass through between the second and third sub-pixels of each transverse arrangement unit and between adjacent transverse arrangement units; the pair of gate driving lines comprises a first gate driving line arranged on the upper side and a second gate driving line arranged on the lower side, and the sub-pixel array further comprises edge gate driving lines arranged on the top and the bottom, the edge gate driving lines are connected with the remaining sub-pixels which are not connected in the top row and the bottom row. By increasing two gate driving lines and changing the connection mode of the gate driving lines, the gate driving lines can be connected with the liquid crystal molecules of the same color with opposite polarities between adjacent rows in the double-gate driving liquid crystal display array, so that the load requirement during the polarity switching of the liquid crystal molecules in the double-gate driving is reduced.

According to the high-resolution and lighting effect optimization type display array substrate and the preparation method thereof, metal layer wiring is optimized, that is, a grid signal line is arranged on a third metal layer and is vertically overlapped with a TFT grid, and the shading area is reduced; a touch signal line moves downwards to a first metal layer, the touch signal-to-noise ratio is increased, a data signal line is additionally arranged on the first metal layer and is equipotential with a data signal line of a second metal layer, a double-layer data line driving structure design is formed, and the touch signal-to-noise ratio is increased under the condition that the thickness of the metal layer, the width of the metal line, the metal material and the like are not increased. Therefore, the impedance of the data line can be greatly reduced to half of the original impedance, the IC driving capability is effectively improved, 8K-resolution driving can be supported at most, and the problem that the S-IC driving capability is insufficient due to the fact that the load of the data line is increased under the dual Gate driving design of a high-resolution panel is solved.

Achieving high gain and low noise in RF circuits. [Solution] A III-N dual gate device and a method for manufacturing a III-N dual gate device. An example semiconductor device includes a III-N back barrier, a III-N channel layer on the III-N back barrier, and a two-dimensional electron gas (2DEG) channel in the III-N channel layer. The semiconductor device includes a source contact and a drain contact, and includes a first gate contact and a second gate contact between the source contact and the drain contact. Between the first gate contact and the second gate contact, the semiconductor device includes an n+GaN contact coupled to the III-N channel layer in a connection region.

The invention provides a super junction LDMOS device with double gates, which comprises a substrate, a source region, a drain region, a gate region and a super junction structure region, and is characterized in that the gate region comprises a first gate and a second gate. The first grid electrode and the second grid electrode use a conducting medium wrapped by a high-dielectric-constant material, a sandwich structure of the conducting medium-HK-P-well can be generated, a channel of the sandwich structure is of a longitudinal structure, and when the grid electrodes are in a pressurized state, namely in a device starting state, the structure can be regarded as a capacitor to accumulate a certain number of electrons at the edge, close to HK, of the P-well, so that the performance of the device is improved. Therefore, the on-resistance of the channel is reduced, and the current is increased. The dual-gate structure can also increase the current paths of the N region and the P-well region, and the on-resistance is effectively reduced through the parallel connection characteristic of multiple current paths.

A semiconductor structure includes a two-dimensional array of unit cell structures overlying a substrate. Each unit cell structure includes an active layer, a gate dielectric underlying the active layer, two gate electrodes underlying the gate dielectric, and two source electrodes and a drain electrode overlying the active layer. Word lines underlie the active layers. Each unit cell structure includes portions of a respective set of four word lines, which includes two word lines that are electrically connected to two electrodes in the unit cell structure and two additional word lines that are electrically isolated from the two electrodes in the unit cell structure.

A synapse device may include an oxide semiconductor transistor divided into a write transistor and a read transistor. The write transistor is an oxide semiconductor transistor having a dual gate including a bottom gate located below a thin oxide semiconductor layer and a top gate located above the thin oxide semiconductor layer.

The utility model provides a kind of double door transmission valve of semiconductor processing etching equipment, belong to semiconductor transmission valve technical field, to solve the tiny dust generated by the friction of sealing element and contact surface, long time use is easy to cause dust particle accumulation on the sealed contact surface, can accelerate wear and tear, while dust particle can float into the cavity or transmission channel of valve body, pollute semiconductor piece surface, can affect product yield problem, the invention includes main valve and the drive seat installed in the middle below main valve, the invention can utilize the double measures of directional blowing and directional suction, can greatly reduce particle residue, reduce pollution from the source of particle generation, guarantee the effect of dust removal, improve semiconductor product yield, while nitrogen of inert gas can be cleaned in the inner surface of the fitting groove, to ensure the neatness and smoothness in the fitting groove, ensure that semiconductor transmission process is always in high vacuum, high-clean environment, guarantee transmission stability and consistency.

A memory device includes at least one transistor having a dual gate structure including a first gate metal and a second gate metal, where the first gate metal has a work function of less than 4.55 eV and the second gate metal has a work function of greater than 4.55 eV. A method of forming the memory device is also provided.

The application relates to the field of MOS semiconductor technology, and discloses a self-aligned double-gate MOSFET which is composed of a plurality of MOS cells connected in parallel, a single MOS cell sequentially comprises a drain, a semiconductor epitaxial layer, a gate and a source from bottom to top, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P well layer and a P+ layer, a P-type doped area is formed in the inside of the N drift layer and below the gate through ion implantation, and the P-type doped area is in ohmic contact with the gate. The application constructs the P-type doped area below the gate and realizes ohmic contact, so that the gate contact resistance is remarkably reduced; meanwhile, a self-aligned N-type doped gate is deposited in the P-type area, so that the gate control structure is accurately aligned with the channel position. The design not only improves the control ability of the gate on the channel carriers, but also simultaneously reduces the conduction loss and enhances the switching response speed.

The utility model provides a kind of high-resolution and light efficiency optimization type display array substrate, by optimizing metal layer wiring, i.e., gate signal line is arranged in third metal layer and is vertically overlapped with TFT gate, reduces light shielding area;Touch signal line is moved to first metal layer, improves touch signal-to-noise ratio, and data signal line is additionally provided in first metal layer, and the data signal line of second metal layer is equipotential, forms double-layer data line driving structure design, without increasing metal layer thickness, metal line width, metal material and the like, data line impedance can be reduced to original half substantially, effectively improves IC driving capability, can support 8K resolution driving at most, breaks through the problem that S-IC driving capability is insufficient due to data line load improvement under high-resolution panel dual Gate driving design.

The application belongs to the technical field of display driving, and particularly relates to an array substrate, a display panel and a driving method, the array substrate comprising 2N rows of scanning lines and M columns of pixel columns, the pixel column comprising a data line, a constant voltage line and N rows of pixel circuits; wherein the nth row of pixel circuits comprises a first sub-pixel unit, a second sub-pixel unit and a control unit, the control unit being configured to apply a constant voltage on the constant voltage line to a pixel electrode of the first sub-pixel unit before the first sub-pixel unit writes the first data voltage, and to apply the constant voltage on the constant voltage line to a pixel electrode of the second sub-pixel unit before the second sub-pixel unit writes the second data voltage; the application effectively improves the problem of insufficient charging when high refresh rate display is performed under the Dual Gate architecture, eliminates bright and dark lines under specific pictures such as water blue pictures, and improves the picture quality uniformity of the display panel.

A display device includes a substrate including a sub-pixel area, an active layer disposed in the sub-pixel area and including first to third regions, a first channel region between the first and second regions, and a second channel region between the second and third regions, a first gate electrode disposed in the first and second channel regions, and constituting a dual gate transistor together with the first and second regions, the first channel region, the second and third regions, and the second channel region, a first gate insulating layer disposed between the active layer and the first gate electrode, and defining an opening exposing the second region, an insulating pattern in the opening, a gate electrode pattern contacting a top surface of the insulating pattern, and is spaced apart from the first gate electrode, and a light emitting structure on the dual gate transistor and the gate electrode pattern.

The invention discloses a display driving framework and a time sequence control method thereof, a display panel and display equipment, and relates to the technical field of display, the display driving framework comprises a pixel array formed by a plurality of pixels distributed in an array, a gate driving circuit and a time sequence control module, the pixels are composed of sub-pixels of different colors which are sequentially arranged in the column direction, and the colors of the sub-pixels in the same row are the same; the gate driving circuit is electrically connected with the sub-pixels in the corresponding rows through the gate scanning lines in the rows; the time sequence control module is electrically connected with the gate driving circuit, and the time sequence control module is configured to respond to a preset double-gate line driving mode, provide a gate driving time sequence for the gate driving circuit and control the gate driving circuit to perform gate driving on the pixel array according to the gate driving time sequence, therefore, grid scanning lines corresponding to two sub-pixel rows which belong to the same color and are spaced by two rows in the column direction are opened at the same time, and a double-grid-line driving mode is compatible under a three-row driving framework.

The application relates to a double-gate structure, a field oxygen structure and a manufacturing method of a semiconductor device, and the manufacturing method of the double-gate structure comprises the following steps: obtaining a wafer formed with a first gate dielectric layer and a second gate dielectric layer; forming a gate material layer on the first and second gate dielectric layers; forming a photoresist anti-reflection layer on the gate material layer; coating photoresist on the photoresist anti-reflection layer, exposing by using a polysilicon gate photoetching plate, developing the photoresist, then etching the photoresist anti-reflection layer and the gate material layer, forming a first gate on the first gate dielectric layer and a second gate on the second gate dielectric layer, and the first gate dielectric layer extends from the bottom of the first gate on both sides; removing the photoresist, then dry etching the first gate dielectric layer extending from the bottom of the first gate, and the photoresist anti-reflection layer is used as a blocking layer of the dry etching. The application uses the photoresist anti-reflection layer as an etching blocking layer, removes the excess first gate dielectric layer extending out of the first gate by dry etching, and ensures that the device does not break the trench.

The invention discloses a silicon carbide phase shift LLC type safety power supply, which comprises a double-gate relay module, an electronic switch H bridge module, a high-frequency transformation module, a bidirectional switch module, a low-pass filtering module, a detection loop reduction module and a power supply control module, and is characterized in that the input end of the double-gate relay module is used for inputting a direct current or alternating current power supply; the output end of the double-brake relay module is electrically connected with the electronic switch H-bridge module and the power supply control module, the output end of the electronic switch H-bridge module is electrically connected with the input end of the high-frequency voltage transformation module, and the output end of the high-frequency voltage transformation module is electrically connected with the bidirectional switch module. The output end of the bidirectional switch module outputs a restored power supply after passing through the low-pass filtering module and the detection loop restoring module; and the power supply control module is also electrically connected with the double-brake relay module, the electronic switch H bridge module, the high-frequency transformation module, the bidirectional switch module, the low-pass filtering module and the detection loop reduction module respectively.

The invention relates to the technical field of data preprocessing, and provides a double-door sentry type entrance dirty data cleaning and error classification method and system. The double-door sentry type entrance dirty data cleaning and error classification method comprises the following steps: calculating the root mean square of each window; calculating spectrum dispersion; if the minimum value of the root-mean-square is smaller than the idle calibration value of the production line or the spectrum dispersion is larger than a spectrum dispersion threshold value, the event window is discarded; calculating a vibration peak value or a root-mean-square of the offline industrial sensing signal data, and if the vibration peak value or the root-mean-square exceeds a first threshold value, determining that the data is signal distortion data; performing consistency judgment on the sampling rate of the off-line industrial sensing signal data, and screening sampling rate error data; and calculating a cross correlation coefficient and an energy difference between the current event window and the previous frame event window, and if the cross correlation coefficient is smaller than a second threshold value and the energy difference is more than K times, judging that the data is packet loss data. The closed loop of training data self-cleaning and error reutilization in the offline environment of the local area network is realized.

The present disclosure relates to semiconductor structures, memory arrays, and manufacturing methods thereof. The semiconductor structure includes a first dielectric layer, a semiconductor layer, and a dual gate structure. The semiconductor layer is disposed over the first dielectric layer. The semiconductor layer includes a source region, a drain region, and a body region between the source region and the drain region. The dual gate structure is disposed over the body region. The dual gate structure includes a first gate, a second gate, and a spacing material. The second gate includes a first horizontal section laterally distanced from the first gate. The spacing material is disposed between the first gate and the first horizontal section of the second gate.

A display device includes a substrate including a sub-pixel area, an active layer disposed in the sub-pixel area and including first to third regions, a first channel region between the first and second regions, and a second channel region between the second and third regions, a first gate electrode disposed in the first and second channel regions, and constituting a dual gate transistor together with the first and second regions, the first channel region, the second and third regions, and the second channel region, a first gate insulating layer disposed between the active layer and the first gate electrode, and defining an opening exposing the second region, an insulating pattern in the opening, a gate electrode pattern contacting a top surface of the insulating pattern, and is spaced apart from the first gate electrode, and a light emitting structure on the dual gate transistor and the gate electrode pattern.

A display substrate, a manufacturing method thereof and a display device. The display substrate includes a base substrate and a plurality of subpixels arranged in an array form on the base substrate. Each subpixel includes a voltage stabilizing electrode, and a subpixel driving circuitry including a driving transistor, and a first transistor, a first electrode of which is coupled to a second electrode of the driving transistor, and a second electrode of which is coupled to a gate electrode of the driving transistor. An active layer of the first transistor includes a first semiconductor portion and a second semiconductor portion spaced apart from each other, and a conductor portion coupled to thereto. An orthogonal projection of the conductor portion onto the base substrate overlaps an orthogonal projection of voltage stabilizing electrode of a previous subpixel in the first direction onto the base substrate.

The invention discloses a gallium integrated circuit chip and a preparation method thereof, and belongs to the technical field of semiconductor device integration. The gallium integrated circuit chip comprises a basic circuit module formed by connecting a main pipe device and an auxiliary pipe device, a drain electrode of the auxiliary pipe device is connected with a grid electrode of the main pipe device, and source electrodes of the auxiliary pipe device and the main pipe device are connected together; grid electrodes of the main tube and the auxiliary tube receive inverted input signals; when the main pipe generates grid voltage ringing due to coupling of adjacent circuit switches, the conducted auxiliary pipe provides a discharge path for grid charges of the main pipe, and misconduction is restrained. Preferably, the auxiliary tube and the main tube are integrated in a monolithic manner, and a high-reliability device structure comprising a cylindrical P-GaN region, double grids and a field plate is adopted; and the chip can be integrated with a phase inverter formed by a GaN device, so that a phase inversion control signal is generated locally, and external driving is simplified. The invention also provides a corresponding preparation method. On the premise that the switching speed is not sacrificed, the ringing problem of the gallium nitride power integrated circuit is effectively solved, and the reliability and the integration degree of the system are remarkably improved.

The invention provides a dual-gate transistor and a display device including the same. The dual gate transistor includes a first gate electrode disposed in an inverted tapered shape on a first gate insulating layer, a buffer layer disposed to cover the first gate electrode, an active layer disposed on the buffer layer, a second gate insulating layer disposed to cover the active layer, and a second gate electrode disposed in a tapered shape on the second gate insulating layer.

Embodiments relate to a vertical transistor dual gate biosensor. A technique includes forming a first vertical field-effect transistor (VFET) having a first gate and forming a second VFET having a second gate. The first and second gates include a shared trench formed in between the first VFET and the second VFET, where the first gate includes a first sidewall of the shared trench, and where the second gate includes a second sidewall of the shared trench. The first sidewall is opposite the second sidewall in the shared trench.