6 results about "Dual gate" patented technology

The application discloses a double-gate driving liquid crystal display array, which comprises a sub-pixel array arranged in a matrix form, each row of the sub-pixel array is composed of a plurality of transverse arrangement units, a pair of gate driving lines are arranged in a wave shape and periodically pass through between the second and third sub-pixels of each transverse arrangement unit and between adjacent transverse arrangement units; the pair of gate driving lines comprises a first gate driving line arranged on the upper side and a second gate driving line arranged on the lower side, and the sub-pixel array further comprises edge gate driving lines arranged on the top and the bottom, the edge gate driving lines are connected with the remaining sub-pixels which are not connected in the top row and the bottom row. By increasing two gate driving lines and changing the connection mode of the gate driving lines, the gate driving lines can be connected with the liquid crystal molecules of the same color with opposite polarities between adjacent rows in the double-gate driving liquid crystal display array, so that the load requirement during the polarity switching of the liquid crystal molecules in the double-gate driving is reduced.

The utility model provides a kind of high-resolution and light efficiency optimization type display array substrate, by optimizing metal layer wiring, i.e., gate signal line is arranged in third metal layer and is vertically overlapped with TFT gate, reduces light shielding area;Touch signal line is moved to first metal layer, improves touch signal-to-noise ratio, and data signal line is additionally provided in first metal layer, and the data signal line of second metal layer is equipotential, forms double-layer data line driving structure design, without increasing metal layer thickness, metal line width, metal material and the like, data line impedance can be reduced to original half substantially, effectively improves IC driving capability, can support 8K resolution driving at most, breaks through the problem that S-IC driving capability is insufficient due to data line load improvement under high-resolution panel dual Gate driving design.

The present disclosure relates to semiconductor structures, memory arrays, and manufacturing methods thereof. The semiconductor structure includes a first dielectric layer, a semiconductor layer, and a dual gate structure. The semiconductor layer is disposed over the first dielectric layer. The semiconductor layer includes a source region, a drain region, and a body region between the source region and the drain region. The dual gate structure is disposed over the body region. The dual gate structure includes a first gate, a second gate, and a spacing material. The second gate includes a first horizontal section laterally distanced from the first gate. The spacing material is disposed between the first gate and the first horizontal section of the second gate.

The application discloses a kind of breathable conductive material, manufacturing method, semiconductor device and double-gate TFT device, breathable conductive material includes host material and doping material;Host material includes at least one metal oxide, metal oxide is conductive oxide, and the grain size of metal oxide is 1nm-100nm;Doping material includes at least one element or oxide in transition metal and post-transition metal, and the content of doping material is 1%-50% by mass percentage.Doping is carried out in conductive oxide by specific element, so as to change the microstructure of conductive oxide, improve the air permeability of conductive oxide while ensuring its conductivity, so that the electrode made of the breathable conductive material can be applied in semiconductor devices requiring conductivity and air permeability.

A cascode circuit is formed using a high voltage transistor in series with a low voltage transistor. A clamp switch device is used to discharge the gate of the high voltage transistor when the cascode is off. Rate limiting devices may be used control turn on and turn off characteristics of the cascode. Rate limiting devices may be include resistors and / or transistors. The high voltage transistor may be a normally on silicon carbide JFET, for example, and the low voltage transistor may be a silicon MOSFET.

This application provides a semiconductor structure, its manufacturing method, and an electronic device. The manufacturing method of the semiconductor structure includes: fabricating a first sacrificial structure on one side of a substrate; fabricating a second sacrificial structure; the second sacrificial structure and the first sacrificial structure having different heights and thicknesses; fabricating a first trench; exposing the second sacrificial structure and the first sacrificial structure on the sides of the first trench; fabricating a semiconductor layer; the semiconductor layer at least conformally covering the first trench; replacing the first and second sacrificial structures with a first gate structure and a second gate structure to obtain a transistor; the first gate structure includes a first gate electrically isolated from the semiconductor layer, and the second gate structure includes a second gate electrically isolated from the semiconductor layer. This application achieves a transistor with dual gates of different heights and thicknesses, which can comprehensively enhance the gate's control over the channel region, improve the channel electric field, enhance carrier transport, increase the drive current, and enable the semiconductor structure to have a high on / off ratio.