437 results about "Conduction channel" patented technology

A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device.

A III-nitride device includes a recessed electrode to produce a nominally off, or an enhancement mode, device. By providing a recessed electrode, a conduction channel formed at the interface of two III-nitride materials is interrupted when the electrode contact is inactive to prevent current flow in the device. The electrode can be a schottky contact or an insulated metal contact. Two ohmic contacts can be provided to form a rectifier device with nominally off characteristics. The recesses formed with the electrode can have sloped sides. The electrode can be formed in a number of geometries in conjunction with current carrying electrodes of the device. A nominally on device, or pinch resistor, is formed when the electrode is not recessed. A diode is also formed by providing non-recessed ohmic and schottky contacts through an insulator to an AlGaN layer.

The invention discloses a surface-modification three-dimensional-network-carbon-fiber-reinforced composite material and a preparing method.Three-dimensional carbon fiber frameworks with different bore diameters are prepared as required, and after surface pretreatment, diamond, carbon nanometer tubes and graphene are subjected to chemical vapor deposition; then the mixture and matrix materials are compounded, wherein the matrix materials are metal or polymers; the carbon-fiber-reinforced metal-based or polymer-based composite material with the three-dimensional net-shaped framework structure is obtained.A three-dimensional continuous heat conduction channel is formed in the composite material through the surface-modification three-dimensional net-shaped carbon fibers, and therefore the heat conduction performance of the composite material is greatly improved; meanwhile, according to space distribution of carbon fibers in the matrix material, the mechanical performance of the composite material can also be improved, and the density and the thermal expansion coefficient can be decreased; the thermal expansion coefficient, the mechanical performance and the thermal performance can be further regulated and controlled by adding zero-dimensional particle reinforcement.

A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.

According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.

A normally off JFET is formed by the implantation of a P base; and a shallower P island atop the P base, forming a narrow lateral conduction channel between the two and a shallow gate implant in the device top surface which forms a second lateral conduction channel with the island. The two channels are each less than 0.5 microns thick and have an impurity concentration such that the channels are depleted at zero gate voltage and are turned on when the gate is forward biased. The gate surrounds a source implant region and a remote drain is provided which is connected to the top surface of the device for a lateral JFET or the bottom of the device for a vertical conduction JFET.

The invention relates to a quasi-one-dimensional metal oxide nano-material biosensor and a method for manufacturing the same. The sensor comprises a silicon chip, a silicon dioxide oxidation layer grown on the silicon chip, a grid electrode, a source electrode, a drain electrode and a microfluid channel; and a quasi-one-dimensional metal oxide semiconductor nano-material is connected with the source electrode and the drain electrode to form a conduction channel. A process for the quasi-one-dimensional metal oxide nano-material biosensor comprises the following steps: firstly, synthesizing thequasi-one-dimensional metal oxide semiconductor nano-material; secondly, adopting a micro-nanometer photolithography standard process and a top-down method to manufacture the quasi-one-dimensional metal oxide semiconductor nano-material and a field effect transistor in array; thirdly, using polydimethylsiloxane to manufacture the microfluid channel; finally, performing surface modification on thequasi-one-dimensional metal oxide semiconductor nano-material, modifying a joining unilayer combined with a target molecule through a self-assembling method, and connecting biological molecules on the surface of the nano-material through joining molecules so as to detect a symbolic molecule of a disease. The quasi-one-dimensional metal oxide nano-material biosensor has the characteristics of rapid response, high sensitivity, strong selectivity, no labeled molecule and the like.

The invention discloses a manufacturing technique of a bipolar plate for a fuel battery. By using expanded graphite as a carbon base material and resin powder as an adhesive, carbon black is added in the composite material preparation process, so that small carbon black particles help to form conduction channels among the graphite particles, thereby enhancing the electric conductivity; and carbon fibers merged into the composite bipolar plate can generate favorable bending strength. Thus, the bipolar plate for a fuel battery, which has the advantages of favorable corrosion resistance, favorable electric and thermal conductivity, high gas barrier property, high mechanical strength and low cost, and can be prepared by a reasonable compounding process.

Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

The invention relates to an underfill adhesive and a preparation method thereof. The underfill adhesive comprises the following ingredients by weight percent: 30 to 70 percent of filler, 10 to 50 percent of epoxy resin, 2 to 20 percent of curing agent, 0.1 to 0.5 percent of catalyst, 1 to 15 percent of flexibilizer, 1 to 25 percent of diluting agent, 0.1 to 3 percent of dispersing agent, 0.05 to 1 percent of defoaming agent, 0.1 to 1 percent of coupling agent and 0.1 to 0.5 percent of pigment; the filler comprises a first component and a second component, wherein the first component is spherical silicon dioxide, and the second component is selected from one of spherical nano aluminum oxide, spherical nano boron nitride, spherical nano aluminum nitride, spherical nano silicon carbide, spherical nano silicon nitride and spherical nano diamond powder. The filler comprises the first component and the second component, and a heat conduction channel can be formed in the underfill adhesive, so that the heat conduction coefficient can be increased; and the underfill adhesive has high heat conductivity and can be widely applied to high-density systematic encapsulation.

The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.

Disclosed is a III-nitride heterojunction device that includes a conduction channel having a two dimensional electron gas formed at an interface between a first III-nitride material and a second III-nitride material. A modification including a contact insulator, for example, a gate insulator formed under a gate contact, is disposed over the conduction channel, wherein the contact insulator includes aluminum to alter formation of the two dimensional electron gas at the interface. The contact insulator can include AlSiN, or can be SiN doped with aluminum. The modification results in programming the threshold voltage of the III-nitride heterojunction device to, for example, make the device an enhancement mode device. The modification can further include a recess, an ion implanted region, a diffused region, an oxidation region, and/or a nitridation region. In one embodiment, the first III-nitride material comprises GaN and the second III-nitride material comprises AlGaN.

A chip transfer method for LED (light-emitting diode) wafer level package includes the steps: manufacturing an LED unit device array on an LED epitaxial wafer, manufacturing metal layers on parts of unit devices of the unit device array to serve as middle metal layers in bonding, and forming a unit device array to be bonded; manufacturing metal patterns corresponding to electrodes of the unit device array to be bonded on the front surface of a base plate, forming heat conduction channels and electric conduction channels below the metal patterns, and connecting electrodes of an LED unit device with a metal bonding pad on the back surface of the base plate through the electric conduction channels; conversely mounting the unit device array to be bonded on the base plate in a bonding mode; finally, sequentially stripping the unit devices to be bonded in a laser stripping mode, separating the epitaxial layers of the unit devices to be bonded from a substrate, and forming a whole film LED array by the separated epitaxial layers and the base plate. The chip transfer method can be used for wafer level package of the LED devices, package efficiency is improved, and cost is reduced.

The invention relates to a thermal resistance measuring method for a semiconductor device. The thermal resistance measuring method includes the following steps that (1) according to the structure of the semiconductor device, a main heat conduction channel is determined, and a constant temperature plane good in contact is arranged on the surface of a shell of the main heat conduction channel; (2) certain power is loaded to the semiconductor device, after the semiconductor device reaches heat balance, it is switched to the situation that measuring power is loaded to the semiconductor device, temperature-sensitive parameters of the semiconductor device are measured in real time to obtain the junction temperature for measuring the semiconductor device, and accordingly a transient thermal response curve of the semiconductor device is obtained; (3) according to the transient thermal response curve, the thermal resistance from a junction of the semiconductor device to the shell is determined. According to the thermal resistance measuring method for the semiconductor device, heating power is loaded through a P zone and an N zone of a substrate of the semiconductor device, the junction temperature is measured by the utilization of a PN junction assembly existing in the semiconductor device, and therefore the transient thermal resistance of integrated circuit products without temperature-sensitive diodes and the transient thermal resistance of non-power integrated circuit products can be measured accurately.

The invention relates to a sull transistor with an etching barrier layer, which comprises a substrate, a grid, an insulating barrier, an electric conduction channel, a source electrode and a drain electrode; the electric conduction channel is arranged on the surface of the insulating barrier far from the grid and is corresponding to the grid; the etching barrier layer wholly covers the electric conduction channel and the surface of the insulating layer and is provided with a through hole on a position corresponding to the surface of the electric conduction channel; the source electrode and the drain electrode are connected with the electric conduction channel by the through hole in the etching barrier layer. The invention also provides a method for preparing the transistor. The invention has the advantages that the etching barrier layer is adopted for wholly covering the insulating layer and the surface of the electric conduction channel, the through hole is only manufactured on a position needing the connection forming, thus avoiding the influence of a plasma etching technique on the insulating layer and the electric conduction channel and ensuring the stability of the electrical property of the sull transistor.

By aiming at the characteristics of high crystallization of a main polymer and low lithium-ion conductivity of the current lithium-ion battery polymer electrolyte, the invention provides an ethyoxyl-containing ionic type compound grafted inorganic nanometer particle modified polymer electrolyte and a preparation method thereof. The preparation method comprises the steps of: firstly activating nanometer particles; then reacting the activated nanometer particles with silane coupling agent having one end per se as quaternary ammonium salt; then performing ion exchange with sulfonate containing an ethyoxyl chain so as to obtain ionic type compound modified nanometer particles; and finally adding the obtained nanometer particles into a polymer electrolyte. For one aspect, the ionic type compound modified nanometer particles can inhibit crystallization of the polymer; and for the other aspect, the grafted ethyoxyl-containing compound also can serve as a new ion conduction channel to improve ionic conductivity. The prepared polymer electrolyte can be applied to preparation of high-performance solid lithium-ion polymer batteries.

The invention relates to a magneto-electric spin-FET including a gate film of chromia and a thin film of a conductive channel material which may be graphene, InP, GaAs, GaSb, PbS, MoS₂, WS₂, MoSe₂, WSe₂ and mixtures thereof. The chromia, or other magneto-electric, and conduction channel material are in intimate contact along an interface there between. The resulting magneto-electric device may be voltage-controlled and provide non-volatile memory.

A normally-off type field-controlled channel GaN heterojunction diode belongs to the technical field of semiconductor devices. The invention adopts the technology of combining insulating layer-groove, modulation doping and groove-modulation doping to change the conductive channel structure of the existing GaN heterojunction diode, and convert the original normally-on spontaneously polarized GaN heterojunction The junction conductive channel is changed into a normally-off field-controlled conductive channel combining spontaneous polarization and piezoelectric polarization in the present invention, which realizes the field-controlled characteristics of the GaN heterojunction diode conductive channel and reduces the forward conduction resistance and enhanced reverse cut-off capability. The invention has lower forward conduction resistance and power consumption, stronger reverse cut-off ability, and is compatible with AlGaN/GaN HEMT power switching device technology, which is beneficial to the application of the device.

The invention discloses a thermal resistance testing method and a thermal resistance testing device. The method comprises the following steps that: a thermal insulation part is arranged at one side of a first test surface of a to-be-tested piece; a heating part which is fixed above the to-be-tested piece is arranged between the thermal insulation part and the to-be-tested piece; a radiating part is arranged at one side of a second test surface of the to-be-tested piece; in the thermal resistance testing process, heat generated by the heating part passes through the to-be-tested piece and then is transferred to the radiating part by a one-way heat conduction channel formed by the thermal insulation part; the temperature values of the first test surface and the second test surface of the to-be-tested piece are tested respectively; the absolute temperature difference value DeltaT is calculated; the power dissipation value P of the heating part is obtained; the thermal resistance value R of the to-be-tested piece can be obtained according to a mathematic expression, namely R is equal to DeltaT/P. According to the thermal resistance testing method and the thermal resistance testing device, as the thermal insulation part which can be used for leading all the heat generated by the heating part to a tested composite heat conduction material, the problem that the thermal resistance testing is not accurate as the heat generated by the heating part is lost in the environment in the thermal resistance testing process can be solved.

A heat-exchanging mat to cool livestock provides for elastic water conduction channels displaced toward an upper surface of the mat and provides for cushioning placed below those elastic channels. In this way, a high degree of cushioning may be obtained without sacrificing an efficient transfer of heat into the upper surface of the mat.