37 results about "Heterojunction diode" patented technology

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

The invention discloses a Ga2O3 heterojunction beta irradiation battery with a multi-groove radioactive source, relates to the technical field of microelectronics, and solves the problems of low energy utilization rate and low energy conversion efficiency of a Ga2O3 nuclear battery radioactive source in the prior art. The battery comprises a filling type multi-groove radioactive source; the Ga2O3 heterojunction diode unit sequentially comprises a P-type ohmic contact electrode, a P-type NiO ion implantation region, an N-type Ga2O3 low-doped epitaxial layer, an N-type Ga2O3 high-doped substrate and an N-type ohmic contact electrode from top to bottom; a multi-T-type radioactive isotope source layer in the filling type multi-groove radioactive source is arranged above the P-type NiO ion implantation region and forms radiation energy coupling with the Ga2O3 heterojunction diode unit; the groove type structure is filled with the radioactive source, the energy deposition of the radioactive source entering the semiconductor conversion device is greatly increased, and the energy conversion efficiency of the Ga2O3 beta irradiation battery is improved.

The invention discloses a trench gate silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The top surface of a second conductive type doped first buried layer formed in a first conductive type doped silicon carbide epitaxial layer is lower than the bottom surface of a gate trench; and a heterojunction polycrystalline silicon layer filled in the second groove is formed on the outer side of the first side surface of the channel region. A lateral current path is made up of the silicon carbide epitaxial layer located over the top surface of the first buried layer, and a longitudinal current path is made up of the silicon carbide epitaxial layer located between the second side of the first buried layer and the bottom of the gate trench and forms a current path of the heterojunction diode together with the lateral current path. A plurality of first connecting layers are formed in a partial region where the first buried layer and the channel region are overlapped, intervals are formed between the first connecting layers in the length direction of the first buried layer, and interval regions are constituent parts of a transverse current path. The invention further discloses a manufacturing method of the trench gate silicon carbide MOSFET. According to the invention, the heterojunction diode can be integrated.

The invention relates to a semiconductor power device and a preparation method thereof. The semiconductor power device comprises a substrate, an epitaxial layer, a first grid electrode, a second grid electrode, a first dielectric layer, a second dielectric layer, a polycrystalline silicon region and a source electrode, wherein the material of the substrate comprises silicon carbide; the epitaxial layer comprises a drift region, a well layer, a first groove, a source region and a source contact region; the first groove extends into the drift region from the surface, far away from the substrate, of the epitaxial layer and penetrates through the well layer; the first grid electrode and the second grid electrode are located in the first groove, and the first grid electrode and the second grid electrode are arranged in an isolated mode. The first dielectric layer wraps the first grid electrode, the second dielectric layer wraps the second grid electrode, and the polycrystalline silicon region of the second conduction type is located between the first dielectric layer and the second dielectric layer and is in contact with the drift region to form a heterojunction diode; the source electrode is electrically connected with the second grid electrode to form a transistor of which the local grid electrode and the drain electrode are short-circuited, and the source electrode is also electrically connected with the polycrystalline silicon region. According to the invention, the conduction loss of the third quadrant can be reduced and the switching loss can be significantly reduced.

The invention relates to a semiconductor device (10) with an integrated heterojunc- tion diode (12) comprising: - a substrate (14) of a first conductive type acting as drain region, - a first crystalline layer (16) of a second conductivity type formed on the sub- strate (14) and acting as drift region, and - a source structure (18) provided on the first crystalline layer (16), the source structure (18) comprising a p-well region (20), an n+source region (22), and a p+short region (24), wherein a recess (26) comprising a bottom crystalline layer (28) is formed in the source structure (18), the recess (26) extending vertically through the p+short region (24) such that for forming the integrated heterojunction diode (12) the bottom crys- talline layer (28) of the recess (26) is in contact with a) the first crystalline layer (16), or b) an additional semiconductor layer (42) being formed on the first crystalline layer (16), and wherein the additional semiconductor layer (42) is of the same conductivity type as the first crystalline layer (16). Furthermore, the invention relates to a method for manufacturing the above semi- conductor device (10).

The application relates to a trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection, which comprises a drain, a substrate, an epitaxial layer and a source arranged in sequence from the lower right to the upper; a plurality of first grooves and a second groove formed on the surface of the epitaxial layer, all the first grooves are distributed in the source region, and the second groove is located in the gate welding area; the surface of the epitaxial layer is formed with a P well area, a P+ area and an N+ area, the P well area is located below the P+ area and the N+ area, and the P+ area and the N+ area are in contact with the source. The application makes full use of the structural characteristics of the trench gate MOSFET device, constructs the n-polySi / p-SiC heterojunction diode and the p-SiC / n-SiCPN junction diode with asymmetric breakdown voltage between the gate and the source of the device, connects the two voltage stabilizing diodes in series, simply and efficiently realizes the ESD protection structure integrated between the gate and the source, and meets the asymmetric requirement of the SiC MOSFET device opening and closing driving protection voltage.

The invention relates to a gallium oxide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure with a p-type buried layer and a preparation method of the gallium oxide MOSFET structure. The gallium oxide MOSFET structure consists of MOSFET regions and heterojunction diode regions which are alternately arranged along the transverse direction, the MOSFET region comprises a drain metal layer, a highly-doped n-type gallium oxide substrate, a lightly-doped n-type gallium oxide epitaxial layer, a current barrier layer, a highly-doped n-type gallium oxide epitaxial layer, a p-type semiconductor layer, a gate dielectric layer, a gate metal layer, an oxide dielectric layer and a source metal layer; a drain electrode metal layer, a highly-doped n-type gallium oxide substrate, a lightly-doped n-type gallium oxide epitaxial layer, a p-type semiconductor layer and a source electrode metal layer are expanded on the left side and the right side of the MOSFET region to form a drain electrode metal layer, a highly-doped n-type gallium oxide substrate, a lightly-doped n-type gallium oxide epitaxial layer, a p-type semiconductor layer and a source electrode metal layer of the heterojunction diode region. According to the gallium oxide vertical field effect transistor, advanced breakdown of a gate medium of a device can be improved, the blocking characteristic of the gallium oxide vertical field effect transistor is enhanced, and higher voltage resistance and lower reverse power consumption are achieved.

A semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate can have an upper surface and a bottom surface. The semiconductor substrate can be made of polycrystalline silicon carbide. The semiconductor structure can further include a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The semiconductor structure can further include a first region of the upper surface of the semiconductor substrate including a formation region of a transistor, and a second region of the upper surface of the semiconductor substrate, adjacent to the first region, including a formation region of a Schottky barrier diode.

The present invention discloses a three-dimensional Ga2O3 heterojunction diode and a method for preparing the same, comprising: providing a substrate, sequentially growing a p+-type NiO epitaxial layer and an alkaline-earth-doped silicon oxide layer on its surface; windowing the alkaline-earth-doped silicon oxide layer to form multiple spaced windows, and then reflowing the remaining alkaline-earth-doped silicon oxide layer using a rapid thermal annealing process to form a hemispherical mask; etching the p+-type NiO epitaxial layer using the hemispherical mask to form multiple hemispherical structures; growing an n+-type Ga2O3 epitaxial layer on the device's upper surface, and performing ion implantation into multiple sub-regions therein to form an n+-type electron transport layer; windowing the source electrode region of the n+-type Ga2O3 epitaxial layer on the surface of the hemispherical structure in the source region, and growing a field oxygen passivation layer on the device's upper surface; removing the field oxygen passivation layer in the source region to window the source electrode region, forming a front electrode on the upper surface of the source region and a back electrode on the lower surface of the substrate. The diode has excellent voltage-resistance balance.

The invention provides a split-gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a heterojunction diode, relates to the technical field of MOSFET devices, and aims to more easily form an MOSFET device which is high in quality, low in conduction voltage drop and low in switching loss. The polycrystalline silicon region is deposited in the groove, and the split gate structure is arranged in the left upper groove and the right upper groove of the polycrystalline silicon region; a first doped region is arranged at the bottom of the groove, and the bottom of the polycrystalline silicon region is in contact with the first doped region; the split gate structure comprises a first gate oxide layer, a second gate oxide layer, a first polycrystalline silicon gate and a second polycrystalline silicon gate; the outer layers of the left side, the bottom and the right side of the first polycrystalline silicon gate are wrapped with first gate oxide layers, and the outer layers of the left side, the bottom and the right side of the second polycrystalline silicon gate are wrapped with second gate oxide layers. The invention has the advantages of low third quadrant turn-on voltage and low switching loss.

The invention particularly relates to a semiconductor device structure and a forming method thereof. According to the method, a part of a gate oxide layer is removed, and a first material epitaxial layer is exposed to serve as a cathode material of a heterojunction diode structure; a second material layer is formed, the part, formed on the exposed first material epitaxial layer, of the second material layer serves as an anode material of the heterojunction diode structure, and the part, formed on the gate oxide layer, of the second material layer serves as a gate electrode medium; and carrying out graphical processing on the second material layer to respectively form an anode electrode and a gate electrode. According to the embodiment of the invention, the heterojunction diode structure can be introduced into a part of cells in the semiconductor device structure under the condition that the cell structure and the size are not changed.

The application relates to a P-type gallium nitride-based heterojunction PIN diode and a manufacturing method thereof, which comprises an N-type Ga2O3 substrate, an N-type Ga2O3 epitaxial layer, a P-type GaN layer, a plurality of P-type GaN regions, an N-region ohmic contact region and a P-region ohmic contact region, wherein the N-region ohmic contact region, the N-type Ga2O3 substrate, the N-type Ga2O3 epitaxial layer and the P-type GaN layer are stacked in sequence; the plurality of P-type GaN regions are distributed on the P-type GaN layer, and the doping concentration of the plurality of P-type GaN regions is greater than that of the P-type GaN layer; and the P-region ohmic contact region covers the P-type GaN layer and the surfaces of the plurality of P-type GaN regions. The PIN diode is provided with a plurality of P-type GaN regions with relatively high doping concentration on the P-type GaN layer, the P-type GaN regions with high doping concentration increase the contact area between the P-region ohmic contact region and the P-type GaN, the on-resistance of the PIN diode can be reduced, the power consumption of the device is reduced, the performance of the device is improved, and the difficulty in preparing P-type Ga2O3 is avoided.

This invention provides a method for manufacturing a planar gate silicon carbide MOSFET with integrated heterojunction diode. A barrier layer is formed on a drift layer of a silicon carbide substrate, and vias are etched into the barrier layer. Ion implantation is performed through the vias to form a first base region, a second base region, a third base region, and a fourth base region, forming a source region. The barrier layer is then reformed and etched again to form vias. Oxidation is performed through the vias to form a first gate dielectric isolation layer and a second gate dielectric isolation layer. The barrier layer is reformed again and etched again to form vias. A first source metal layer, a second source metal layer, a first gate metal layer, a second gate metal layer, and a source heterojunction are deposited through the vias. All barrier layers are removed, and metal is deposited on the silicon carbide substrate to form a drain metal layer. This method distributes the MOSFET current across the left and right sides of the device, avoiding current concentration, reducing thermal management issues, and improving device reliability.

The invention discloses a gallium oxide heterojunction diode with a vertical structure and a preparation method. The gallium oxide heterojunction diode comprises a gallium oxide epitaxial wafer; the P-type oxide is located in the middle area of the upper surface of the gallium oxide epitaxial wafer; the two sides of the P-type oxide are of an arc-shaped structure, and the curvature radius of the arc-shaped structure is smaller than 3 microns. The SiO2 field plates are located on the two sides of the P-type oxide and make contact with the P-type oxide; the anode electrode is located on the P-type oxide and part of the SiO2 field plate; and the cathode electrode is positioned on the lower surface of the gallium oxide epitaxial wafer. According to the device structure designed by the invention, reverse leakage current is effectively inhibited, the breakdown voltage of the device is effectively improved, and the performance and reliability of the device are greatly improved.

The invention relates to the technical field of power semiconductors, in particular to a SiC trench gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a heterojunction diode and a preparation method thereof. According to the invention, heavily-doped P-type polycrystalline silicon or NiO penetrating into the heavily-doped N-type current enhancement layer in the SiC body is respectively arranged at the four corners in the cell, and each surface of the heavily-doped P-type polycrystalline silicon or NiO and the N-type current enhancement layer form a heterojunction diode with low turn-on voltage drop; and the N-type current enhancement layer and the surface metal between the two heterojunction columns on each side of the groove form a Schottky diode. According to the invention, by adopting the scheme that the cylindrical heterojunction goes deep into the SiC body to form the heterojunction diode, the current path during forward and reverse conduction can be obviously increased, so that the forward specific on-resistance and reverse conduction voltage drop are reduced.

The invention relates to a silicon carbide MOSFET with an integrated polysilicon silicon carbide heterojunction diode. A semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate may have an upper surface and a bottom surface. The semiconductor substrate may be made of polycrystalline silicon carbide. The semiconductor structure may also include a drift region of the first conductivity type on the upper surface of the semiconductor substrate. The semiconductor structure may further include a first region of an upper surface of the semiconductor substrate, the first region including a formation region of a transistor, and a second region of the upper surface of the semiconductor substrate, the second region being adjacent to the first region and including a formation region of a Schottky barrier diode.

The invention relates to a gallium oxide heterojunction diode with high voltage resistance. The JBS comprises an active region and at least one JBS unit, and the JBS unit comprises a cellular groove prepared in the N-type gallium oxide drift layer and anode metal located in the cellular groove and electrically connected with a gallium oxide heterojunction of the active region; the source region gallium oxide heterojunction comprises a source region first doped p-type nickel oxide region which is at least distributed below the groove bottom of the cellular groove and is in contact with the N-type gallium oxide drift layer; and a source region protection unit which at least covers a corner region of the first doped p-type nickel oxide region of the source region and forms a gradient JTE effect with the first doped p-type nickel oxide region of the source region is arranged on the cross section of the diode. According to the gallium oxide heterojunction diode, the electric field distribution of the gallium oxide heterojunction diode can be optimized, the breakdown voltage of the gallium oxide heterojunction diode is improved, and the requirement of a high-voltage power electronic application scene for the voltage resistance performance of the diode is met.

The application relates to a SiC UMOSFET device integrated with an HJD and a preparation method thereof, which comprises a metalized drain, an N+ substrate region, an N-epitaxial region, an N-csl region, a P-base region, a P+ buried layer, two P+ injection regions, an N+ injection region, a P+ PolySi region, a gate dielectric layer, an N-PolySi gate and a metalized source. The depth of the N-PolySi gate is greater than that of the P-base region, the depth of the P+ buried layer and the second P+ injection region is the same and greater than the trench depth. The contact interface between the source and the first P+ injection region and the N+ injection region is ohmic contact, and the interface between the P+ PolySi region and the N-epitaxial region is heterojunction contact. The application integrates a heterojunction diode structure in the device, improves the utilization rate of the cell area, further reduces the opening voltage, reduces the switching loss of the device, and improves the withstand voltage capacity of the device through the P+ buried layer and the P+ injection region.

The invention discloses a high-voltage-resistant gallium oxide heterojunction diode based on nickel oxide grown through nickel thermal oxidation magnetron sputtering and a preparation method of the high-voltage-resistant gallium oxide heterojunction diode. The gallium oxide heterojunction diode provided by the invention can be applied to a scene with high withstand voltage and low conduction loss. The preparation method comprises the following steps: cleaning a gallium oxide single crystal substrate; forming a back metal electrode layer on the back surface of the cleaned gallium oxide single crystal substrate; rapid annealing is carried out in a nitrogen atmosphere, so that ohmic contact is formed between the back metal electrode and the gallium oxide single crystal substrate; growing a nickel oxide semiconductor layer on the front surface of the gallium oxide single crystal substrate through nickel thermal oxidation magnetron sputtering, wherein the material in the nickel oxide semiconductor layer is NiOx; and forming a top electrode layer on the surface of the nickel oxide semiconductor layer. According to the invention, the nickel oxide thin film is grown through a metal nickel thermal oxidation magnetron sputtering method, and the NiOx-Ga2O3 heterojunction power diode device with a 2kV withstand voltage level is prepared under the condition of keeping low specific on-resistance.

The application discloses a preparation method of a heterojunction diode light-emitting rod driven by a button cell, and belongs to the field of photoelectric and lighting devices. The preparation method comprises the following stages: coating of a light-emitting layer; taking an aluminum rod, coating the surface of the aluminum rod with conductive silver paste or lithium fluoride film, placing the aluminum rod on the zinc oxide nanoparticle coating in the length direction of the light-emitting film, and winding the light-emitting film into a barrel shape in the width direction; using a cover plate to seal the end of the cylindrical structure, plugging a button cell into the beginning end of the barrel-shaped structure, and using a second cover plate to seal the end of the cylindrical structure; the negative electrode of the button cell is connected with the aluminum electrode, and the positive electrode of the button cell is connected with the linear silver electrode. The method overcomes the shortcomings of the lack of P type of inorganic semiconductor materials and the lack of N type of organic semiconductor materials, utilizes transfer printing and coating processes, has low production cost, and the product is flexible, bendable and convenient to carry.

The utility model discloses a SiC MOSFET device capable of reducing bipolar degradation risk, and relates to the technical field of semiconductors. Source polycrystalline silicon and a P-shield region form a heterojunction diode in an N-epitaxial layer, so that current flowing through a body diode during reverse conduction of the device is shared, and the risk of degradation of a PW region of the device is reduced. And meanwhile, the P-shield region is arranged below the gate oxide layer, so that the impact of gate oxide of a peak electric field can be inhibited, and the reliability problem of the gate oxide layer of the trench SiC MOSFET is improved. The overlapping area of the grid electrode and the drain electrode is reduced in structural design, so that the purpose of reducing the grid-drain capacitance is achieved, the Miller plateau time is shortened, the switching performance of the device is improved, and the switching loss is reduced.

The present invention belongs to the field of power semiconductor technology and specifically provides a heterojunction-type wide-bandgap and ultra-wide-bandgap trench-gate MOSFET device with an integrated heterojunction diode. The device is used to address the technical bottleneck of the ultra-wide-bandgap semiconductor Ga2O3, which is unable to produce high-power normally-off inversion-layer trench MOSFET devices due to the lack of P-type doping. The device also addresses the low channel mobility and high process requirements of existing Ga2O3 Fin-gate technology, as well as the low channel mobility of existing 4H-SiC MOSFET devices and MOSFETs composed of GaN, AlGaN, and even AlN. Furthermore, the device addresses the technical difficulty of the high reverse conduction voltage drop of the aforementioned MOSFETs. By utilizing easily fabricated, low-cost, wide-bandgap semiconductors such as heavily doped heterogeneous P-type NiO or SnO2, or P-type semiconductor materials of the same material as the voltage-suppressing layer, to form electric field protection for the inversion layer channel region and gate oxide layer composed of the heterogeneous semiconductor material with a lower breakdown electric field, this ensures that breakdown occurs in the voltage-suppressing layer rather than the P-type channel region of the heterogeneous semiconductor material. This allows for the realization of various normally-off inversion layer MOSFET devices with low channel resistance without compromising the high breakdown characteristics of the material. Furthermore, the heterojunction diode formed by the heavily doped heterogeneous P-type NiO or SnO2 material and the voltage-suppressing layer, or the heterojunction diode formed by the heterogeneous P-type channel region and the voltage-suppressing layer, exhibits low reverse voltage drop and unipolar conduction characteristics, contributing to reduced static and dynamic losses.

This invention belongs to the field of semiconductor device technology and discloses an amorphous inorganic / organic vertical heterojunction diode and its fabrication method. The diode provided by this invention comprises a substrate, an anode, a cathode, and an organic-inorganic heterojunction. The anode covers a P-type semiconductor layer of the heterojunction, which is composed of a DPPT-TT thin film formed by spin-coating an undoped intrinsic DPPT-TT solution. The cathode covers an N-type semiconductor layer of the heterojunction, which is an a-IGZO thin film grown by magnetron sputtering. Molybdenum is used as the contact material for the anode. The cathode is composed of a glass substrate, a copper sheet, and conductive silver paste. By introducing the amorphous metal oxide semiconductor a-IGZO, the charge transport capability is enhanced. This novel heterojunction structure effectively improves carrier separation and transport efficiency and significantly reduces contact resistance.

The invention provides a beta-Ga2O3 heterojunction diode structure. The beta-Ga2O3 heterojunction diode structure sequentially comprises cathode metal, an N + substrate region and an N-drift region from bottom to top, the P-well region is divided into a left part and a right part which are located on the upper surface of the N-drift region, and the P-plus region is divided into a left part and a right part which are located on the upper surfaces of the P-well region and part of the N-drift region; and an anode metal. According to the beta-Ga2O3 heterojunction diode structure and the P-NiO structure, a depletion region can be expanded, the distribution of an electric field at the edge of a main junction can be optimized, the distribution of the electric field is smoother and more uniform, the negative influence caused by an electric field concentration effect is eliminated, the reverse breakdown voltage is increased, and the reverse characteristic is greatly improved compared with that of a traditional structure.

This invention discloses a Bi₂O₂Se / PbS quantum dot heterojunction short-wave infrared photodetector for broadband imaging and its fabrication method, belonging to the field of photoelectric detection and imaging technology. The detector is a vertically stacked heterojunction diode structure, consisting of, from top to bottom, an ITO top electrode layer, a SnO₂ electron transport layer, a PbS quantum dot light absorption layer, a Bi₂O₂Se hole transport layer, an Au bottom electrode layer, and a SiO₂ / Si support substrate. The fabrication method includes: ultrasonic cleaning of the substrate, Au bottom electrode deposition, Bi₂Se₃ sputtering and oxidation annealing, PbS quantum dot ink spin coating and annealing, SnO₂ nanocrystal spin coating, SnO₂ thin film sputtering, and ITO top electrode sputtering. This device achieves a broadband spectral response of 550–2000 nm at zero bias, with a responsivity of 0.879 A / W and a detectivity of 4.27 × 10¹² cm·Hz¹ / ²·W. – ¹ The rise / fall times are 1.58 μs and 1.65 μs, respectively. The performance is stable after 80 days of air exposure and can be applied to self-powered visible to short-wave infrared broadband imaging.

The invention discloses a heterojunction diode based on a P-type diamond-n-type gallium oxide nanorod. The heterojunction diode comprises a diamond ohmic contact metal layer, a p-type diamond substrate layer, a p-type diamond nanorod, an n-type gallium oxide buffer layer, a first n-type gallium oxide nanorod, a second n-type gallium oxide nanorod and a gallium oxide ohmic contact metal layer which are sequentially laminated. The diamond and the gallium oxide of the heterojunction diode are arranged in a nano column shape, so that the heterojunction diode has excellent carrier transmission and separation efficiency and excellent heat conduction performance.

The invention belongs to the technical field of semiconductors, and provides an epsilon-Ga2O3 / diamond heterojunction diode. The epitaxial wafer comprises an anode metal layer, a p-type diamond substrate, an n-type epsilon-Ga2O3 epitaxial layer and a cathode metal layer which are stacked from bottom to top, when the substrate is composed of p-or p- / p + diamond, the epitaxial layer is composed of n-, n + or n- / n + type epsilon-Ga2O3, and the thickness of the layer composed of p-diamond is greater than or equal to 10 [mu] m; when the substrate is composed of p + diamond, the epitaxial layer is composed of n-or n- / n + type epsilon-Ga2O3, and the thickness of the layer composed of the n-type epsilon-Ga2O3 is 5-20 [mu] m. The epsilon-Ga2O3 disclosed by the invention can be directly subjected to heteroepitaxy on the diamond substrate, so that the size and the thickness of the thin film can be conveniently and directly regulated and controlled, and the manufacturing process is simplified; and the interface quality of the diode is relatively high, good rectification characteristics and kilovolt-level breakdown voltage are presented, and high interface thermal conductivity can be realized.

This application provides a silicon carbide trench MOSFET with integrated heterojunction diode and its fabrication method. Applied to the field of power semiconductor technology, it includes: an N+ type SiC substrate; an N- type SiC drift layer disposed above the N+ type SiC substrate; a P-type base region disposed above the N- type SiC drift layer; an N+ type source region disposed above the P-type base region; a trench gate structure including: a gate trench, a gate oxide layer, and a gate conductive material, the gate oxide layer being disposed on the inner wall of the gate trench, and the gate conductive material filling the gate trench; a source metal electrically connected to both the N+ type source region and the P-type base region; and a drain metal disposed below the N+ type SiC substrate. This invention reduces on-resistance, gate-drain capacitance, and switching losses, and fundamentally eliminates the risk of bipolar degradation.

The invention relates to the technical field of power semiconductor devices, and discloses a silicon carbide trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which comprises an N-type substrate, the N-type drift region is arranged on the N-type substrate; the trench is arranged in the N-type drift region and extends downwards from the upper surface of the device; the gate structure is accommodated in the groove and comprises a polysilicon gate medium and a polysilicon gate; a P-well region disposed in the N-type drift region and adjacent to the trench; the N + contact region is arranged in the P-well region; the shielding structure is located below the P-well region, the shielding structure comprises a P-shield 1 region and a P-shield 2 region, the P-shield 1 region and the P-shield 2 region are transversely arranged at an interval, and a CSL region is arranged between the P-shield region and the P-shield region. The heterojunction diode formed by the P + poly region and the N + contact region is integrated in the device, so that the energy efficiency and the working reliability of the device in high-frequency application are improved.

A SiC trench MOS device structure with built-in polysilicon heterojunction diode relates to the field of power semiconductor, comprising source metal, drain metal, substrate, N-drift region, P-shielding region, isolation oxide layer, gate oxide layer, polysilicon source, polysilicon gate, current spreading layer, P-base region, N-source region, P-plus region. One end of the substrate is in contact with the drain metal, and the other end is in contact with the drift layer; the current spreading layer is arranged on the N-drift region; the P-base region is arranged on the current spreading layer; the N-source region and the P-plus region are arranged side by side on the P-base region; a plurality of trenches are formed in the base region and extend vertically into the drift layer; the left side of the trench is filled with polysilicon gate, and the right side is filled with polysilicon source; the left side, the right side and the bottom of the polysilicon gate are in contact with the gate oxide layer; the left side of the polysilicon source is in contact with the gate oxide layer; the polysilicon source is in contact with the N-drift region to form a heterojunction. The isolation oxide layer is in contact with the source metal, the trench and the N-source region; the trench is in contact with the N-source region. The application improves the switching speed and improves the reverse recovery charge.