48 results about "Cmos chip" patented technology

The invention discloses an edge end large language model inference system. The system comprises a main computing chip, an LPDDR interconnection resource and a vertically stacked and packaged storage chip stack, the storage chip stack comprises an NAND flash memory chip and a DRAM (Dynamic Random Access Memory) chip, and the NAND flash memory chip and the DRAM chip are paired and share an LPDDR interconnection resource; the NAND flash memory chip comprises a flash memory chip bare chip and a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip bare chip which are three-dimensionally interconnected based on hybrid bonding; a flash memory array is arranged on the flash memory chip bare chip; a logic block is arranged on the CMOS chip bare chip; the main calculation chip reads a parameter matrix of a model full connection layer from the NAND flash memory chip and reads other parameters from the DRAM chip for calculation in a pre-filling stage of large language model reasoning; and the NAND flash memory chip performs full connection layer calculation in a decoding stage. The system provided by the invention can improve the external transmission and internal reading bandwidth.

The invention relates to the technical field of image exposure, in particular to an image exposure system of code scanning equipment. The system comprises a CMOS chip which is internally provided with an automatic exposure unit and is used for collecting images and counting the brightness mean value of each frame of image; wherein the CMOS chip acquires an image in a first mode in a stop stream state, and acquires an image in a second mode in a start stream state; and the processor is used for executing an automatic exposure algorithm on the brightness mean value corresponding to the last frame of image in the stop stream state to generate a corresponding exposure parameter, and then transmitting the exposure parameter to the CMOS chip as an initial exposure parameter when the CMOS chip exposes the first frame of image in the start stream state. In the stop stream state, the brightness statistics is performed through the low-resolution image, and the brightness mean value of the last frame of image is used as the exposure basis of the first frame of image in the start stream state, so that the number of image frames required by image convergence to exposure stability is remarkably reduced, and the code scanning response speed is improved.

The invention discloses a method for eliminating bias signals during stress measurement of a piezoresistor and a CMOS chip, and belongs to the field of signal processing. According to the invention, at least one piezoresistive element in the Wheatstone bridge circuit is an adjustable resistor; if the piezoresistor generates a bias signal during stress measurement, the bias signal generated due to various conditions is eliminated by adjusting an adjustable resistor in the Wheatstone bridge circuit, so that when the pressure-sensitive chip is normally used, the measurement requirement can be met by externally connecting a microvolt-level power supply voltage and a small-range electric terminal, and the measurement precision is improved; and the power consumption of the pressure-sensitive chip is also greatly reduced by using the microvolt-level power supply voltage.

An integrated CMOS chip (1) with a time-to-digital converter (TDC) circuit (2) for light detection and ranging (LIDAR) applications comprises a start channel (10) with an input (11) for a start signal (ST) and at least one stop channel (20, 30) with an input (21, 31) for a stop signal (SP). It further comprises a TDC element (40) for each of the start and stop channels (10, 20, 30), wherein the TDC element (40) is configured to store corresponding counts when triggered by the start signal (ST) or the stop signal (SP), respectively. It further comprises a calculation unit (50) coupled to each TDC element (40) and configured to determine a time difference (ΔT) associated with the start signal (ST) and the stop signal (ΔSP) on the basis of the counts, and a command-controlled communication interface (60) comprising at least two bidirectional data pins (63, 64).Furthermore, a time-of-flight measurement system and a method for operating the integrated CMOS chip (1) are provided.

The application discloses an online proton imaging ion spectrometer diagnosis system, relates to the fields of plasma physics and nuclear detection, and comprises an online proton imaging module, an online Thomson ion spectrometer module and a shielding aiming module; the shielding aiming module comprises a shielding cavity and an aiming laser pen; the online proton imaging module comprises a metal filter, a first scintillator and two proton imaging acquisition assemblies; the proton imaging acquisition assembly comprises a first optical fiber panel attached to the first scintillator and a first CMOS sensor attached to the first optical fiber panel; the online Thomson ion spectrometer module comprises an ion beam deflection mechanism and an ion spectrum diagnosis acquisition assembly; the ion spectrum diagnosis acquisition assembly comprises a light-proof aluminum film, a second scintillator, a second optical fiber panel and a second CMOS sensor which are sequentially and superposedly arranged. The application reduces the size of the whole system, can simultaneously carry out online proton imaging and ion energy spectrum diagnosis, and can effectively prevent radiation damage to the CMOS chip.

The invention relates to a large-size CMOS chip mounting flatness control device and method, the device comprises a cross-shaped sliding table, a bottom plate, a grounding corner connector, two supports and a cross beam, the cross-shaped sliding table is fixed on the bottom plate, the two supports are fixed on the bottom plate through the grounding corner connector, the cross beam stretches across the two supports and is fixed with the two supports, the cross beam is located right above the cross-shaped sliding table, and the cross beam is fixed on the cross-shaped sliding table through the grounding corner connector. Multiple through holes and multiple threaded holes are formed in the middle of the beam. According to the method, an image measuring instrument with a laser ranging function is adopted to measure the planeness of the chip, the position of the chip is adjusted through a cross-shaped sliding table, pressure is applied to a designated area of the chip through a pressing nail, and the mounting planeness of the chip is iteratively adjusted. The surface mounting device is used for surface mounting of the large-size CMOS chip, and surface mounting flatness control can be achieved.

An advanced integrated optical transceiver enables super high-speed communication between chips such as GPUs and HBM. Designs for such a transceiver may be based on an array of GaN micro-LEDs and an array of Si photodetectors (PDs) which are hybrid bonded (i.e. via “direct bond interconnect”) to a CMOS chip. Hybrid bonding makes the integrated optical transceiver very small and highly reliable.

The invention discloses contact type imaging equipment, which comprises a shell, a CMOS (Complementary Metal Oxide Semiconductor) chip detector and an optical fiber panel, a darkroom space is arranged in the shell; the CMOS chip detector is located in the shell, the CMOS chip detector comprises a pixel array, the pixel array comprises a plurality of pixels distributed in an array mode, and the pixel array is used for converting optical signals into images of detected samples; the optical fiber panel is attached to the top surface of the CMOS chip detector, and a detected sample is arranged on the optical fiber panel. The optical fiber panel is arranged on the CMOS chip detector, so that the imaging effect is not affected while the detector is protected.

The application discloses a manufacturing method of a piezoresistive chip of a monolithic integrated CMOS circuit, and belongs to the field of MEMS sensor and CMOS chip manufacturing. In order to solve the problems of high manufacturing complexity and high cost in the process of monolithic integration of the piezoresistive chip and the CMOS circuit, the application mainly adopts a combination of multiple ion implantation processes in a standard CMOS process, and generates a mask layout pattern of a piezoresistive sensitive unit accurately by modifying a layout generation rule, so that multiple doping concentration distribution designs of the piezoresistive sensitive unit are realized. The method can manufacture the piezoresistive chip of the monolithic integrated CMOS circuit with different performance indexes, adapt to diversified application requirements, and is compatible with the standard CMOS process, has the advantages of low research and development cost and large-scale production, is widely applicable to the production of commercial CMOS foundries, and can meet the rapidly growing market demand of the piezoresistive chip.

The embodiment of the application discloses a memory and a detection method, and belongs to the technical field of storage. The memory comprises a storage array chip and a CMOS chip. The storage array chip comprises a first dielectric layer and a first electrode plate, the first electrode plate is located in the first dielectric layer, the CMOS chip comprises a second dielectric layer and a second electrode plate, and the second electrode plate is located in the second dielectric layer. The first dielectric layer and the second dielectric layer are bonded, and the first electrode plate and the second electrode plate form a capacitor at a bonding interface. Through the capacitor formed by the first electrode plate and the second electrode plate at the bonding interface, potential defects of the bonding interface can be detected.

The invention relates to the technical field of vacuum-solid mixed digital low-light-level devices, and particularly discloses a novel digital low-light-level imaging device and a manufacturing method of the novel digital low-light-level imaging device, and the novel digital low-light-level imaging device is characterized in that a photoelectric cathode is arranged below an input window; the micro-channel plate is arranged below the photoelectric cathode; the anode assembly is arranged below the microchannel plate, the anode assembly comprises a multilayer ceramic base, a chip heat dissipation assembly, a CMOS chip, a fluorescent screen and a getter, the chip heat dissipation assembly is arranged on the multilayer ceramic base, the CMOS chip is arranged on the chip heat dissipation assembly, the fluorescent screen is arranged on the CMOS chip, the CMOS chip is used for receiving optical signals output by the fluorescent screen, and the getter is arranged on the fluorescent screen. The signal is converted into a digital signal to be output; the input window, the photoelectric cathode, the front-end tube shell and the anode assembly are packaged together from top to bottom to form a vacuum cavity; and the high-voltage power supply provides working voltage for the digital low-light imaging device and realizes self-adaptive control of the output brightness of the device along with the working illumination according to a rear-end signal, and the high-voltage power supply comprises three paths of high-voltage outputs, namely cathode voltage, micro-channel plate voltage and anode voltage.

There is a method for making a substrate by providing a Si top surface in a plane, and providing a GaN top surface in the plane adjacent the Si top surface, wherein a substrate is formed having a top surface comprising the Si top surface and the GaN top surface. There is a substrate having a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface. There is a package having a substrate with a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface, a CMOS chip attached to the Si top surface, a GaN transistor attached to the GaN top surface, and a metal layer connecting the CMOS chip and the GaN transistor.

The invention discloses a preparation method of an indium arsenide colloidal quantum dot infrared imaging chip and the chip, and the preparation method provided by the invention comprises the steps: firstly, carrying out the pretreatment of a chip silicon substrate; sequentially depositing a top incident transparent electrode layer and a hole transport layer on the silicon substrate of the silicon chip; then, depositing a first InAs quantum dot thin layer and a second InAs quantum dot thick layer on the silicon hole transport layer; an electron transport layer is formed on the second silicon InAs quantum dot thick layer; forming a metal bottom electrode on the silicon electron transport layer; connecting the silicon metal bottom electrode with a reading terminal of the CMOS chip to form an interconnection structure; and then, exposing a pixel port of the silicon interconnection structure by using a photoetching mask and a wet etching mode, and carrying out nitrogen sealing packaging. By adopting the double-layer quantum dot structure, the spatial separation of charge collection and light absorption functions is realized, and the response rate and the detection uniformity of the device are further improved.

This application relates to a light cone coupling method for an ICMOS chip, an ICMOS chip, a microprocessor, and a solar-blind ultraviolet light detection device, and relates to the field of solar-blind ultraviolet light detection technology. This method can effectively improve the utilization rate of light signals. The method comprises: using analytical-grade alcohol to clean the photosensitive surface of the CMOS chip; cutting the small facet of the light cone, and leaving two rows of pixel cells at the edge of the pixel area of ​​the photosensitive surface of the CMOS chip when the light cone is coupled and bonded; cleaning the surface of the light cone with analytical-grade alcohol; vapor-depositing an ITO film between the small end face of the light cone and the CMOS chip as a grounding conductive layer; after aligning the CMOS chip, light cone, and image intensifier, separating them horizontally, applying epoxy glue with a 3:1 glue ratio to the surface of the photosensitive surface, placing the CMOS chip on a three-dimensional precision translation stage, and adjusting while observing the other plane of the light cone. Simultaneously, gently pressing the light cone to ensure that the epoxy glue is evenly coated on the photosensitive surface without generating bubbles.

An advanced integrated optical transceiver enables super high-speed communication between chips such as GPUs and HBM. Designs for such a transceiver may be based on an array of GaN micro-LEDs and an array of Si photodetectors (PDs) which are hybrid bonded (i.e. via "direct bond interconnect") to a CMOS chip. Hybrid bonding makes the integrated optical transceiver very small and highly reliable.

Power converter that features: a FET or SFET chip (22) comprising at least one FET or SFET switch (30) coupled to a circuit node (18) of a power stage (34); and a CMOS chip (20) which features: at least one CMOS switch (32) coupled to the circuit node (18) of the power stage (34), at least one measuring line (16B) configured to transmit a current measurement signal containing information about a current level of a current through the at least one CMOS switch (32), and a controller unit (24) configured to control the at least one FET or SFET switch (30) and the at least one CMOS switch (32) of the power stage (34) at least partially based on the current measurement signal transmitted through the at least one measuring line (16B) in order to generate an output power at the circuit node (18) of the power stage (34).

The application discloses a MEMS-based in-plane three-axis large displacement actuating platform and a manufacturing method thereof, mainly comprising an outer frame, a cross island frame, a bidirectional comb-shaped driving unit, a long spring beam and a short spring beam, and manufacturing steps comprise: using magnetic neutral loop discharge plasma (NLD) to anisotropically etch a cavity structure on a glass substrate, using an anode bonding process to bond a BF33 glass wafer with the cavity structure and a low-resistance silicon wafer, thinning the low-resistance silicon wafer, deep silicon etching (DRIE) the low-resistance silicon wafer to form an electrically isolated channel and fill BCB material, using a chemical mechanical polishing (CMP) process to remove the BCB on the surface of the low-resistance silicon wafer, sputtering a metal layer and using a lift-off process to form a wire layer, and deep silicon etching (DRIE) the low-resistance silicon wafer to form a final device. The application has the beneficial effects of improving device filling rate, reducing size, improving structural stiffness, response speed, resonance frequency and heat dissipation performance, and simultaneously providing a wire bonding method for heterogeneously integrating a micro moving platform and a CMOS chip.

The utility model relates to turn-back type camera module alignment assembly equipment which comprises a rack, a collimator assembly is arranged at the rear end of the top of the rack, a white field function assembly is arranged at the top of the rack and located at the right front end of the collimator assembly, and an active alignment module is arranged at the top of the rack and located at the front end of the collimator assembly. A chip feeding assembly is arranged on the right side of the top of the rack, a lens feeding assembly is arranged on the left side of the top of the rack, and a material taking and placing assembly is arranged at the front end of the top of the rack. According to the camera module, the parallel light pipe assembly is vertically placed, the included angle between the parallel light pipe assembly and the CMOS chip is 90 degrees, the parallel light pipe assembly and the CMOS chip are placed downwards and are different from downward placement of a traditional module, the CMOS chip of the product keeps horizontal placement consistent with that of the traditional camera module, glue drawing operation is facilitated, the camera lens and the CMOS chip are fed through the clips, the clips containing multiple discs of materials only need to be manually placed into equipment, and the camera lens and the CMOS chip are fed through the clips. According to the equipment, material taking, placing and assembling and finished product discharging are fully automatically completed, the labor cost is reduced, and the production efficiency is improved.

A CMOS chip includes a signal converting circuit configured to convert a baseband signal and an RF signal, a plurality of ports through which the RF signal is transmitted or received, the plurality of ports being respectively included in a first transmission path, a second transmission path, and a reception path, and a plurality of matching networks connected to the signal converting circuit, the plurality of matching networks being respectively connected to the plurality of ports, a first matching network among the plurality of matching networks including an external matching network, and the external matching network being configured to perform an impedance matching of a compound semiconductor device.

The invention discloses a rectification antenna and array suitable for long-distance microwave energy transmission. The rectification antenna comprises four rectification antenna units, a power synthesis network and a DC load. The four rectification antenna units are the same in structure, each rectification antenna unit comprises a rectifier chip and an antipode linear tapered slot antenna which are connected, the antipode linear tapered slot antenna is used for receiving microwave energy from a free space and inputting the microwave energy to the rectifier chip, and the rectifier chip is used for converting the microwave energy into a direct current signal; the four rectification antenna units are connected with a direct current load through a power synthesis network to supply power to the direct current load; the power synthesis network is used for adjusting the series-parallel connection relation of the four rectification antenna units so as to adjust the output voltage and current for supplying power to the direct current load. Through an innovative PCB antenna-CMOS chip cascade and array scheme, the contradiction between efficiency and scale in long-distance transmission is solved, and the effects of low cost and high integration are achieved.

The invention provides a CMOS chip imaging defect-to-defect source automatic analysis system and method. The CMOS chip imaging defect-to-defect source automatic analysis system comprises a chip container module used for accommodating different types of CMOS chips; the configuration file module is used for storing pixel pitch of the CMOS chip and origin coordinate information of the chip container; the data importing module is used for importing imaging defect coordinate data of the CMOS chip; the coordinate conversion module is used for converting the defect coordinate data into space coordinates of the microscopic analysis equipment according to the configuration file module and the data import module; and the microscopic analysis equipment is used for analyzing the defect source according to the space coordinates of the microscopic analysis equipment. According to the invention, the coordinate conversion module adopts parameters such as a pixel pitch and an original point position to carry out calculation, so that the accuracy of coordinate conversion is ensured, and the precision of defect source positioning is improved. Through the configuration file module and the coordinate conversion module, automation from defect coordinate reading to microscopic analysis equipment coordinate conversion is realized, manual intervention is reduced, and analysis efficiency is improved.

The embodiment of the invention provides a grating filter, a chip module and computer equipment, which are used for reducing the alignment precision requirement between a CMOS (Complementary Metal Oxide Semiconductor) chip and normal-temperature equipment. The grating filter provided by the embodiment of the invention comprises at least one metal layer. The metal layer comprises a plurality of first rectangular structures periodically arranged in the first direction and a plurality of second rectangular structures periodically arranged in the second direction, and the first direction is perpendicular to the second direction. In the multiple first rectangular structures and the multiple second rectangular structures, the adjacent first rectangular structures and the adjacent second rectangular structures form rectangular cavities. The arrangement period of the first rectangular structures is 2C1, and the arrangement period of the second rectangular structures is 2C1. The metal layer further comprises a plurality of first square structures, the first square structures are located in the center of the rectangular cavity, and the first square structures are squares with the side length of C1 * D1.

The present invention discloses a method and system for detecting surface defects of CMOS chips, wherein the detection method includes the following steps: dividing the image area in the image data of the product to be tested to form multiple detection blocks; binarizing each of the detection blocks according to the grayscale value; extracting defects in each of the detection blocks according to the results of the binarization; and performing pixel and / or size analysis on the defects to further extract effective defects. The method of the present invention can accurately, quickly, and stably detect dirt defects on the surface of the product before the CMOS chip is filmed. The requirements for the grayscale consistency and uniformity of the overall image are reduced, the installation and debugging of the hardware light source consistency are facilitated, the consistency of the grayscale of local areas in the product is ensured, and it is compatible with the overall grayscale changes caused by material and processing differences of different products. The detection accuracy of defects with small grayscale contrast differences and subtle defects is higher.

The invention discloses a column-level fixed-mode noise correction method for a large-area-array CMOS sensor, and belongs to the technical field of CMOS image sensors. The method comprises the steps of collecting an original image, collecting the original image of the large-area-array CMOS sensor under uniform illumination, calculating the mean ratio of each column of the upper part and the lower part of the image, fitting a correction curve method, fitting a smooth curve according to the change trend of the mean ratio of each column, and correcting the lower half part of the image column by column by utilizing the fitted curve. According to the method, the ratio fitting curve is used for correcting the column-level noise of the large-area-array CMOS, so that when a large-area-array CMOS chip is purchased, the chip does not need to be screened, all the column-level noise caused by slope errors can be corrected, the production cost is greatly saved, after correction through the method, the column-level fixed noise of the CMOS is corrected, and the product quality is improved. Pixels of the whole area array are consistent in response under the same illumination, brightness mutation of adjacent columns is avoided through fitting curve smoothing processing, and the image quality is greatly improved.

a kind of nC 60+ Fullerene meteorite-based radar and communication antenna technology solution, nC 60+ This approach utilizes focused ion beam electromagnetic field technology, which leverages shared ionic bonds and large π-bonded covalent bonds; micro / nano electronic grid resonant cavities formed by laser direct writing and sintering of large π-bonded electron clouds; and selective terahertz wave propagation technology using metal, semiconductor, and CMOS chips directly written onto micro / nano electronic grid resonant arrays and phased arrays. This scheme enables antennas to become superconducting tools for transmitting and receiving optical and electromagnetic waves. Applications include long-distance terahertz weak signal communication, radar, "black holes" and "light boxes" for optical and electromagnetic waves (such as terahertz wave absorption or submersion – used for stealth), imaging detection, sensitive wave identification, and selective sensing. 60+ Fullerene meteorite-like materials, including laboratory-produced nC60. + and having nC 60+ Mineral or synthetic polymer substitutes with a particular strength or complementarity.

The method of the present disclosure is related to the assembly of two components on two opposite sides of a substrate, enabled by the embedding of one of the components in a stress-compensated SiO2 layer applied at low temperatures, i.e. lower than any temperature that could compromise the functionality of the embedded component. Example embodiments are related to heterogeneous integration schemes, i.e. the assembly of components of different types, in particular a CMOS chip and a III-V chip, which are otherwise difficult to integrate in a 3D package. The stress-compensated film embeds the component at least laterally, i.e. the layer surrounds and is in direct contact with the sides of the component and the thickness of the film is at least equal to the thickness of the component.

The invention provides an image exposure method based on a CMOS built-in automatic exposure unit, and belongs to the technical field of image exposure. The method comprises the steps that in a stop flow state, a CMOS chip collects an image in a first mode; the automatic exposure unit performs brightness statistics on each frame of image to obtain a brightness mean value of each frame of image; in the start stream state, the CMOS chip transmits a brightness mean value corresponding to the last frame of image in the stop stream state to an upper computer, and the upper computer executes an automatic exposure algorithm according to the brightness mean value to generate a corresponding exposure parameter; the upper computer transmits the exposure parameter to the CMOS chip as an initial exposure parameter when the CMOS chip exposes the first frame of image in the start stream state; the CMOS chip collects images in a second mode. According to the method, the number of image frames required by convergence of the code scanning equipment to stable exposure is remarkably reduced, the code scanning response speed is improved, the power consumption is remarkably reduced, the method is suitable for an application scene with frequent start and stop, the endurance time of the equipment is prolonged, and the energy efficiency ratio of the equipment is improved.

The invention discloses a multi-channel radio frequency transceiver chip based on a three-dimensional stacking process, and belongs to the technical field of microwave integrated circuits. The chip comprises a GaAs radio frequency bottom plate, a GaAs adapter plate and a CMOS chip cover plate which are sequentially arranged from bottom to top, a multi-channel radio frequency circuit is integrated on the GaAs radio frequency bottom plate, a control circuit and a power supply modulation circuit are integrated on the lower surface of the CMOS chip cover plate, and the GaAs adapter plate is provided with a plurality of metal wires. The two layers of chips are electrically interconnected through gold bumps, and the upper layer metal and the lower layer metal of the GaAs adapter plate are electrically interconnected through ground holes; meanwhile, ground hole-gold ball-ground hole shielding structures are arranged among the channels of the radio frequency circuit. Through an innovative vertical interconnection structure and a ground hole-gold ball-ground hole shielding structure, the problems of electromagnetic coupling, large interconnection loss and the like in the prior art are solved, and high-power output, high phase shift precision and compact packaging are realized.

The invention discloses a backside illuminated CMOS chip processing method for electron bombardment imaging, which comprises the following steps of: S1, removing a glass cover plate of a commercial CMOS chip by using an engraving and milling machine to expose the surface of the CMOS chip, and cleaning and drying the surface of the CMOS chip; s2, EDS is used for element analysis and size measurement of the area A of the CMOS chip located on the outer side of the CMOS internal circuit wiring layer and the outer side of the MOS tube structure, and a back-illuminated CMOS chip surface structure and a back-illuminated CMOS chip surface structure are obtained; and S3, after the purple tantalum oxide layer is exposed, cleaning and drying are performed to obtain the backside illuminated CMOS chip for electron bombardment imaging. The passivation layer on the surface of the CMOS chip processed by the method is comprehensively removed, and the processed CMOS chip has an electron sensitive characteristic and can be used for producing EBAPS.

The invention discloses a method for realizing a stress sensitive element on a CMOS (Complementary Metal Oxide Semiconductor) chip, and belongs to the field of signal processing. The stress sensitive element measures stress through a Wheatstone bridge circuit, the Wheatstone bridge circuit is a quadrangle formed by four bridge arms, one group of opposite angles of the quadrangle are driving ends, and the other group of opposite angles generate differential voltage. A resistor is connected to the driving end of the Wheatstone bridge circuit, and / or the driving voltage of the driving end in the Wheatstone bridge circuit is adjusted, and the stress sensitive element measuring sensitivity can be adjusted. Furthermore, if resistors are connected to the two driving ends of the Wheatstone bridge circuit, the measurement sensitivity of the stress sensitive element can be adjusted on the basis of not changing the common-mode voltage of the output end of the Wheatstone bridge circuit.