23 results about "Cmos chip" patented technology

The application discloses an online proton imaging ion spectrometer diagnosis system, relates to the fields of plasma physics and nuclear detection, and comprises an online proton imaging module, an online Thomson ion spectrometer module and a shielding aiming module; the shielding aiming module comprises a shielding cavity and an aiming laser pen; the online proton imaging module comprises a metal filter, a first scintillator and two proton imaging acquisition assemblies; the proton imaging acquisition assembly comprises a first optical fiber panel attached to the first scintillator and a first CMOS sensor attached to the first optical fiber panel; the online Thomson ion spectrometer module comprises an ion beam deflection mechanism and an ion spectrum diagnosis acquisition assembly; the ion spectrum diagnosis acquisition assembly comprises a light-proof aluminum film, a second scintillator, a second optical fiber panel and a second CMOS sensor which are sequentially and superposedly arranged. The application reduces the size of the whole system, can simultaneously carry out online proton imaging and ion energy spectrum diagnosis, and can effectively prevent radiation damage to the CMOS chip.

An advanced integrated optical transceiver enables super high-speed communication between chips such as GPUs and HBM. Designs for such a transceiver may be based on an array of GaN micro-LEDs and an array of Si photodetectors (PDs) which are hybrid bonded (i.e. via “direct bond interconnect”) to a CMOS chip. Hybrid bonding makes the integrated optical transceiver very small and highly reliable.

The embodiment of the application discloses a memory and a detection method, and belongs to the technical field of storage. The memory comprises a storage array chip and a CMOS chip. The storage array chip comprises a first dielectric layer and a first electrode plate, the first electrode plate is located in the first dielectric layer, the CMOS chip comprises a second dielectric layer and a second electrode plate, and the second electrode plate is located in the second dielectric layer. The first dielectric layer and the second dielectric layer are bonded, and the first electrode plate and the second electrode plate form a capacitor at a bonding interface. Through the capacitor formed by the first electrode plate and the second electrode plate at the bonding interface, potential defects of the bonding interface can be detected.

There is a method for making a substrate by providing a Si top surface in a plane, and providing a GaN top surface in the plane adjacent the Si top surface, wherein a substrate is formed having a top surface comprising the Si top surface and the GaN top surface. There is a substrate having a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface. There is a package having a substrate with a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface, a CMOS chip attached to the Si top surface, a GaN transistor attached to the GaN top surface, and a metal layer connecting the CMOS chip and the GaN transistor.

The invention discloses a preparation method of an indium arsenide colloidal quantum dot infrared imaging chip and the chip, and the preparation method provided by the invention comprises the steps: firstly, carrying out the pretreatment of a chip silicon substrate; sequentially depositing a top incident transparent electrode layer and a hole transport layer on the silicon substrate of the silicon chip; then, depositing a first InAs quantum dot thin layer and a second InAs quantum dot thick layer on the silicon hole transport layer; an electron transport layer is formed on the second silicon InAs quantum dot thick layer; forming a metal bottom electrode on the silicon electron transport layer; connecting the silicon metal bottom electrode with a reading terminal of the CMOS chip to form an interconnection structure; and then, exposing a pixel port of the silicon interconnection structure by using a photoetching mask and a wet etching mode, and carrying out nitrogen sealing packaging. By adopting the double-layer quantum dot structure, the spatial separation of charge collection and light absorption functions is realized, and the response rate and the detection uniformity of the device are further improved.

An advanced integrated optical transceiver enables super high-speed communication between chips such as GPUs and HBM. Designs for such a transceiver may be based on an array of GaN micro-LEDs and an array of Si photodetectors (PDs) which are hybrid bonded (i.e. via "direct bond interconnect") to a CMOS chip. Hybrid bonding makes the integrated optical transceiver very small and highly reliable.

The utility model relates to turn-back type camera module alignment assembly equipment which comprises a rack, a collimator assembly is arranged at the rear end of the top of the rack, a white field function assembly is arranged at the top of the rack and located at the right front end of the collimator assembly, and an active alignment module is arranged at the top of the rack and located at the front end of the collimator assembly. A chip feeding assembly is arranged on the right side of the top of the rack, a lens feeding assembly is arranged on the left side of the top of the rack, and a material taking and placing assembly is arranged at the front end of the top of the rack. According to the camera module, the parallel light pipe assembly is vertically placed, the included angle between the parallel light pipe assembly and the CMOS chip is 90 degrees, the parallel light pipe assembly and the CMOS chip are placed downwards and are different from downward placement of a traditional module, the CMOS chip of the product keeps horizontal placement consistent with that of the traditional camera module, glue drawing operation is facilitated, the camera lens and the CMOS chip are fed through the clips, the clips containing multiple discs of materials only need to be manually placed into equipment, and the camera lens and the CMOS chip are fed through the clips. According to the equipment, material taking, placing and assembling and finished product discharging are fully automatically completed, the labor cost is reduced, and the production efficiency is improved.

A CMOS chip includes a signal converting circuit configured to convert a baseband signal and an RF signal, a plurality of ports through which the RF signal is transmitted or received, the plurality of ports being respectively included in a first transmission path, a second transmission path, and a reception path, and a plurality of matching networks connected to the signal converting circuit, the plurality of matching networks being respectively connected to the plurality of ports, a first matching network among the plurality of matching networks including an external matching network, and the external matching network being configured to perform an impedance matching of a compound semiconductor device.

The invention discloses a rectification antenna and array suitable for long-distance microwave energy transmission. The rectification antenna comprises four rectification antenna units, a power synthesis network and a DC load. The four rectification antenna units are the same in structure, each rectification antenna unit comprises a rectifier chip and an antipode linear tapered slot antenna which are connected, the antipode linear tapered slot antenna is used for receiving microwave energy from a free space and inputting the microwave energy to the rectifier chip, and the rectifier chip is used for converting the microwave energy into a direct current signal; the four rectification antenna units are connected with a direct current load through a power synthesis network to supply power to the direct current load; the power synthesis network is used for adjusting the series-parallel connection relation of the four rectification antenna units so as to adjust the output voltage and current for supplying power to the direct current load. Through an innovative PCB antenna-CMOS chip cascade and array scheme, the contradiction between efficiency and scale in long-distance transmission is solved, and the effects of low cost and high integration are achieved.

The embodiment of the invention provides a grating filter, a chip module and computer equipment, which are used for reducing the alignment precision requirement between a CMOS (Complementary Metal Oxide Semiconductor) chip and normal-temperature equipment. The grating filter provided by the embodiment of the invention comprises at least one metal layer. The metal layer comprises a plurality of first rectangular structures periodically arranged in the first direction and a plurality of second rectangular structures periodically arranged in the second direction, and the first direction is perpendicular to the second direction. In the multiple first rectangular structures and the multiple second rectangular structures, the adjacent first rectangular structures and the adjacent second rectangular structures form rectangular cavities. The arrangement period of the first rectangular structures is 2C1, and the arrangement period of the second rectangular structures is 2C1. The metal layer further comprises a plurality of first square structures, the first square structures are located in the center of the rectangular cavity, and the first square structures are squares with the side length of C1 * D1.

a kind of nC 60+ Fullerene meteorite-based radar and communication antenna technology solution, nC 60+ This approach utilizes focused ion beam electromagnetic field technology, which leverages shared ionic bonds and large π-bonded covalent bonds; micro / nano electronic grid resonant cavities formed by laser direct writing and sintering of large π-bonded electron clouds; and selective terahertz wave propagation technology using metal, semiconductor, and CMOS chips directly written onto micro / nano electronic grid resonant arrays and phased arrays. This scheme enables antennas to become superconducting tools for transmitting and receiving optical and electromagnetic waves. Applications include long-distance terahertz weak signal communication, radar, "black holes" and "light boxes" for optical and electromagnetic waves (such as terahertz wave absorption or submersion – used for stealth), imaging detection, sensitive wave identification, and selective sensing. 60+ Fullerene meteorite-like materials, including laboratory-produced nC60. + and having nC 60+ Mineral or synthetic polymer substitutes with a particular strength or complementarity.

The method of the present disclosure is related to the assembly of two components on two opposite sides of a substrate, enabled by the embedding of one of the components in a stress-compensated SiO2 layer applied at low temperatures, i.e. lower than any temperature that could compromise the functionality of the embedded component. Example embodiments are related to heterogeneous integration schemes, i.e. the assembly of components of different types, in particular a CMOS chip and a III-V chip, which are otherwise difficult to integrate in a 3D package. The stress-compensated film embeds the component at least laterally, i.e. the layer surrounds and is in direct contact with the sides of the component and the thickness of the film is at least equal to the thickness of the component.

The invention discloses a backside illuminated CMOS chip processing method for electron bombardment imaging, which comprises the following steps of: S1, removing a glass cover plate of a commercial CMOS chip by using an engraving and milling machine to expose the surface of the CMOS chip, and cleaning and drying the surface of the CMOS chip; s2, EDS is used for element analysis and size measurement of the area A of the CMOS chip located on the outer side of the CMOS internal circuit wiring layer and the outer side of the MOS tube structure, and a back-illuminated CMOS chip surface structure and a back-illuminated CMOS chip surface structure are obtained; and S3, after the purple tantalum oxide layer is exposed, cleaning and drying are performed to obtain the backside illuminated CMOS chip for electron bombardment imaging. The passivation layer on the surface of the CMOS chip processed by the method is comprehensively removed, and the processed CMOS chip has an electron sensitive characteristic and can be used for producing EBAPS.

This invention relates to the technical field of terahertz wave detection, and more specifically, to a CMOS-graphene-based terahertz wave detector and its fabrication method. The fabrication method includes: sequentially depositing zinc, nickel, and gold on an aluminum electrode layer on a CMOS chip to obtain a source electrode and a drain electrode; transferring graphene onto the source electrode and drain electrode; patterning the graphene; and annealing the chip sample with the patterned graphene layer to obtain the CMOS-graphene-based terahertz wave detector. The terahertz wave detector includes a substrate layer, a patterned graphene layer, a source electrode, and a drain electrode, wherein both the source electrode and drain electrode consist of an aluminum electrode layer, a zinc layer, a nickel layer, and a gold layer stacked from bottom to top. This invention exhibits stability, supports identifiable and repeatable terahertz responses, and possesses broad-spectrum absorption capabilities. The terahertz wave detector can rapidly generate a significant photocurrent response, and the detection results are intuitive and clear.

The utility model discloses a handheld digital magnifier with adjustable focal length, which is characterized in that a rotatable adjusting bracket is fixedly matched with an outer roller, and the adjusting bracket is rotated to enable a lens frame in an inner roller to slide along a threaded chute of the outer roller, so that the focal length of a lens is adjusted, and the axial distance between the lens and a CMOS (complementary metal oxide semiconductor) chip is controlled; the product is simple in structure, the axial position of the lens is accurately adjusted through a physical structure, full-focal-length clear imaging is achieved, zooming-in and zooming-out can be carried out while the definition of an image is kept, and therefore the user experience is improved, and the application scene is expanded.

A DNA synthesis and sensing system is proposed for high-throughput DNA synthesis and real-time, full-frame pH sensing. This system includes a CMOS chip with an electrode array fabricated on top and an underlying CMOS control and sensing circuit, along with a microfluidic delivery subsystem for reagent delivery. The method for fabricating the electrode array is detailed. The system operates to synthesize DNA by regulating local pH and sense pH by voltage sensing on an electrode array which contains a plurality of working electrodes arranged in rows and columns and at least one counter electrode. The underlying CMOS circuit is electrically coupled to the working electrodes, controlling DNA synthesis selectively and individually in synthesis mode and sensing pH across the electrode array with a full-frame readout.

There is a method for making a substrate by providing a Si top surface in a plane, and providing a GaN top surface in the plane adjacent the Si top surface, wherein a substrate is formed having a top surface comprising the Si top surface and the GaN top surface. There is a substrate having a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface. There is a package having a substrate with a Si top surface in a plane, and a GaN top surface in the plane adjacent the Si top surface, a CMOS chip attached to the Si top surface, a GaN transistor attached to the GaN top surface, and a metal layer connecting the CMOS chip and the GaN transistor.

This application provides a display module, a method for fabricating the display module, and a display device, solving the technical problem of low bonding yield between the display module and the CMOS chip, and avoiding the cumbersome process and yield loss caused by the three-time bonding and three-time substrate removal required for the three-color light-emitting layer. In this display module, a filler layer surrounds and forms a pixel window; multiple light-emitting structures within the pixel window are stacked vertically, and the epitaxial buffer layer and the side of each light-emitting structure facing away from the substrate have connection areas; a bonding layer is disposed on the side of the filler layer facing away from the substrate; multiple electrodes penetrate the bonding layer and are connected to the corresponding connection areas; the side of the bonding layer facing away from the substrate has a bonding surface, and the ends of the multiple electrodes facing away from the substrate are flush with the bonding surface. This application uses a filler layer to achieve selective growth of the light-emitting region, realizing etching-free formation of the light-emitting structure, reducing sidewall damage of the light-emitting structure, and improving luminous efficiency; in addition, it improves the bonding yield between the display module and the CMOS chip.

This disclosure introduces a “Super-LLM” architecture integrating multiple interconnected “daughter” Large Language Models (LLMs). By sharing internal layer information and utilizing multi-input, multi-output ports, the system processes simultaneous prompts with enhanced accuracy and reduced hallucinations. The design emphasizes hardware implementation, proposing identical neural networks fabricated on single CMOS chips using precision analog matching. This enables direct state sharing and dynamic layer reconfiguration via caches. Optimized for agentic systems, the Super-LLM facilitates autonomous communication and complex task orchestration by allowing internal models to share awareness and feedback loops within a unified, high-performance computational framework.

The invention belongs to the technical field of rapid detection of pesticide residues in tea leaves, and relates to a circuit for rapid detection of pesticide residues in tea leaves. The circuit comprises a relay, a 12V light source driving circuit, a 12V halogen lamp, a 3.3 V voltage reducing and stabilizing circuit, a spectral data acquisition circuit, an STM32 microcontroller, a touch screen interaction circuit, a USB (Universal Serial Bus) to serial port circuit, a key input circuit and a WIFI (Wireless Fidelity) wireless transmission module. The STM32 microcontroller controls the 12V light source driving circuit to drive the 12V halogen lamp to work through the relay; and after the light source is stabilized, the spectral data acquisition circuit is controlled to acquire spectral information. According to the STM32 microcontroller, an STM32H750VBT6 is adopted as a core controller, and the STM32H750VBT6 is The spectrum data acquisition circuit adopts three AS7265x series sensors, CMOS chips integrated with Gaussian optical filters are arranged in the sensors, and stray light interference is effectively inhibited by combining a precise optical hole design. The system has the advantages of low cost, fast detection, support of wireless transmission and the like, and is suitable for online real-time monitoring of tea pesticide residues.

The application discloses a medical magnification endoscope optical system, comprising a first lens group, a second lens group, a third lens group, a fourth lens group, a filter and a CMOS chip arranged in sequence from an object plane side, the object plane and the CMOS chip are mutually object image conjugate relationship, the first lens group is a negative refractive index lens group, the second lens group, the third lens group and the fourth lens group are all positive refractive index lens groups, a system diaphragm is arranged between the first lens group and the second lens group, the third lens group is used for moving along the optical axis of the endoscope system to zoom and switch a low magnification state and a high magnification state, and the first lens group is provided with a first concave lens towards the object plane side. Compared with the prior art, the application simplifies the zooming mode, the image quality is excellent and stable in the zooming process, the magnification and F number are higher in the high magnification, and the resolution is also higher.

An advanced integrated optical transceiver enables super high-speed communication between chips such as GPUs and HBM. Designs for such a transceiver may be based on an array of GaN micro-LEDs and an array of Si photodetectors (PDs) which are hybrid bonded (i.e. via “direct bond interconnect”) to a CMOS chip. Hybrid bonding makes the integrated optical transceiver very small and highly reliable.

The present disclosure provides a terahertz wave imaging system and method, the system comprising: a terahertz detector (A) for detecting a terahertz modulated light signal and sampling the terahertz modulated light signal by using a demodulation signal to obtain a sampling signal; a CSA integration module (B) for sequentially integrating and amplifying the sampling signal to obtain a photocurrent signal; a signal processing module (C) for processing the photocurrent signal to obtain a sampling value, calculating the time of flight and depth information of the terahertz modulated light signal according to the sampling value, and imaging by using the time of flight and depth information; wherein the demodulation signal has a phase offset with the terahertz modulated light signal. The terahertz wave imaging system of the present disclosure can be made on the same CMOS chip, has simple design principle, high precision, low cost, and is easy to mass integrate.