The invention belongs to the field of
integrated circuit design, particularly relates to a fractional
frequency divider circuit based on a digital time converter, and aims to solve the performance
bottleneck caused by quantization errors in a fractional frequency division phase-locked loop. The circuit comprises three core modules, namely a differential integral modulator, a pulse
swallowing multi-modulus
frequency divider and a constant-slope digital time converter, wherein the differential integral modulator generates a multi-modulus
frequency divider control word and a digital time converter control word according to integer and fractional frequency control words; the pulse
swallowing multimode frequency divider receives an output
signal of the
voltage-controlled oscillator, and outputs a
signal D1 and a
time sequence control signal after frequency division
processing; the constant slope digital-to-time converter time-converts D1 based on a control word and a timing
signal, and outputs a delayed
clock signal to counteract a quantization error. The
femtosecond-level time
delay circuit adopts an optimized
circuit architecture design, has the characteristics of simple structure and low
power consumption, realizes
femtosecond-level time
delay precision and high
linearity, effectively inhibits
phase noise and stray, is adaptive to various analog fractional frequency division phase-locked loop structures, remarkably improves the
frequency spectrum purity and the
system suitability of a
clock generator, and has a wide application prospect. And the application requirements of the high-performance fractional frequency division phase-locked loop in the fields of
wireless communication,
radar and the like are met.