216 results about "Nanowire" patented technology

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Integrated circuit structures having deep via structures, and methods of fabricating integrated circuit structures having deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends into the conductive trench contact structure. The conductive via has a first width beneath the epitaxial source or drain structure less than a second width laterally adjacent to the epitaxial source or drain structure.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

This invention discloses a method for fabricating a highly sensitive long-wavelength infrared superconducting single-photon detector. It fully utilizes and amplifies the acoustic mismatch effect between the superconducting thin film and the substrate to achieve phonon localization enhancement on the superconducting nanowires. The effect of this innovative design is to increase the energy utilization rate of long-wavelength infrared photons on the superconducting nanowires, thereby improving the response sensitivity of the superconducting nanowires to long-wavelength infrared photon signals. Compared to existing designs that reduce the cross-sectional size of the superconducting nanowires, create holes beneath the nanowires, or increase the buffer layer, this invention is easier to implement and has higher scalability.

The application provides a high-flexibility dielectric positive electrode binder and a preparation method thereof and a solid-state battery positive electrode. The high-flexibility dielectric positive electrode binder comprises a fluoropolymer matrix and a fast ion conductor; the fluoropolymer matrix is a copolymer of vinylidene fluoride (VDF) and a fluorine-containing comonomer, the fast ion conductor is in a one-dimensional nanowire shape and is dispersed in the fluoropolymer matrix; and the mass fraction of the fast ion conductor is 1% to 20% based on the fluoropolymer matrix. The application can simultaneously solve three core problems of physical continuity of an ion conduction path in the positive electrode, inhibition of a space charge layer at an interface and mechanical coating of active particles, thereby significantly improving the rate performance, cycle stability and actual energy density of the solid-state battery.

This application discloses a cathode catalyst for aluminum-air batteries and its preparation method. The cathode catalyst comprises a carbon support and at least one platinum-containing multi-element alloy nanowire supported on the carbon support. The platinum-containing multi-element alloy nanowire contains Pt and at least two other transition metal elements, and the aspect ratio of the platinum-containing multi-element alloy nanowire is at least 10. The cathode catalyst of this application exhibits long-term durability under harsh electrochemical environments, higher catalytic activity of the active components, and is less prone to migration and aggregation, thereby solving the technical problems of high cost and poor stability of traditional Pt / C catalysts for aluminum-air batteries.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

Gate-all-around integrated circuit structures having three-dimensional (3D) conductive contact structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires. A first epitaxial source or drain structure is at an end of the first vertical stack of horizontal nanowires. A second epitaxial source or drain structure is at an end of the second vertical stack of horizontal nanowires. The second epitaxial source or drain structure is vertically beneath the first epitaxial source or drain structure. A conductive contact structure is through the first epitaxial source or drain structure and extending only partially into the second epitaxial source or drain structure.

The application provides a nanomaterial integrated structure and a preparation method thereof. The method sequentially prepares a first device layer and a second device layer. The first device layer comprises a first nanowire and a first ring gate structure. The extending direction of the first nanowire is perpendicular to the plane where the first device layer is located. The first ring gate structure surrounds the first nanowire. The second device layer is parallel to the plane where the first device layer is located. The second device layer comprises a second nanowire and a second ring gate structure. The extending direction of the second nanowire is the same as that of the first nanowire and the second nanowire is aligned with the first nanowire. The second ring gate structure surrounds the second nanowire. At least one section of the second nanowire is grown at one end of the first nanowire by a lengthening method. The preparation method of the application realizes three-dimensional integration of vertical ring gate devices, is compatible with CMOS technology, and has high controllability, high reliability, high yield and high uniformity. The nanomaterial integrated structure of the application has the advantage of compact structure and is beneficial to improving circuit integration.

This section describes integrated circuit structures with standard mixed-height cells, providing power delivery on both odd and even traces. In one example, an integrated circuit structure includes a first vertical stack of horizontal nanowires or a first fin, a second vertical stack of horizontal nanowires or a second fin spaced laterally from the first vertical stack or fin, and a third vertical stack of horizontal nanowires or a third fin spaced laterally from the second vertical stack or fin. A first pair of gate lines is located above the first and second vertical stacks of horizontal nanowires or fins.A second pair of gate lines is located above the third vertical stack of horizontal nanowires or the third fin, and not above any additional vertical stacks of horizontal nanowires or fins. The second pair of gate lines runs in the same direction and is aligned with the first pair of gate lines. Multiple conductive lines are located above and along a direction orthogonal to the first and second pairs of gate lines. The multiple conductive lines can include supply traces on both odd and even lines. The multiple conductive lines can include wide lines and narrow lines, and the supply traces can include narrow lines, wide lines, or both.

The present invention relates to a μLED display design method based on nanowire. The method comprises: first, growing different nanowire materials capable of generating three primary colors: red, green and blue on a substrate; then, respectively dissolving the different nanowire materials in insulated photocuring adhesives and injecting the mixtures into different grids of a grid pool, and performing curing; and finally, arranging electrodes on upper and lower surfaces of the grid pool. The method provided by the present invention can simplify the structure and enhance the industrial efficiency of the μLED.

The invention relates to an optoelectronic device (1) comprising an assembly (10) of photonic crystals (100, 200, 300, 400) intended to emit a light beam mainly having a wavelength λ. This assembly comprises at least one first elementary photonic crystal (100) that comprises an assembly of first nanowires (101) and is configured to emit a first elementary light beam mainly having the wavelength λ, and a second elementary photonic crystal (200) that comprises an assembly of second nanowires (201) and is configured to emit a second elementary light beam mainly having the wavelength λ. The elementary photonic crystals (100, 200) have distinct structures, so as to give the elementary light beams at least one distinct optical characteristic. The light beam emitted by the photonic crystal assembly can be formed by the first elementary light beam and / or the second elementary light beam.

The application discloses an antioxidant composite ceramic aerogel and a preparation method thereof, and belongs to the technical field of composite ceramic aerogels.The main body of the antioxidant composite ceramic aerogel is a silicon nitride aerogel, the nanostructure of the silicon nitride aerogel is one of one-dimensional silicon nitride nanowires and two-dimensional silicon nitride nanobands or a combination of the two nanostructures, and a mullite coating and a copper-nickel metal coating are sequentially coated on the nanostructure of the silicon nitride aerogel from inside to outside.The application can solve the technical problem that the prior art cannot prepare silicon nitride ceramic aerogels which can stably serve in a high-temperature oxygen environment at low cost and in batches.

Devices, integrated circuit transistor structures, systems, and techniques are described herein related to gate all around field effect transistor circuits having an n-type transistor integrated with a p-type transistor such that each has stress engineering in the channel material thereof. The nanowires of the p-type transistor are released and surrounded by a sacrificial flowable oxide structure during source and drain material growth to apply compressive stress to the channel material. The n-type transistor source and drain are grown in the presence of a sacrificial lattice matched material to apply tensile stress to the channel material, and the nanowires are subsequently released. After removal of the sacrificial flowable oxide structure, gate structures are coupled to the n-type and p-type transistors.

Title: Optoelectronic Device with Controlled Light Emission Profile The invention relates to an optoelectronic device (1) comprising an assembly (10) of photonic crystals (100, 200, 300, 400) for emitting a light beam having predominantly a wavelength λ. This assembly comprises at least one first elementary photonic crystal (100) comprising an assembly of first nanowires (101) and configured to emit a first elementary light beam having predominantly the wavelength λ, and a second elementary photonic crystal (200) comprising an assembly of second nanowires (201) and configured to emit a second elementary light beam having predominantly the wavelength λ. The elementary photonic crystals (100, 200) have distinct structures, so as to impart to the elementary light beams at least one distinct optical characteristic.The light beam emitted by the set of photonic crystals can be formed by the first elementary light beam and / or the second elementary light beam. Figure for the abbreviation: Fig. 2A.

The application belongs to the technical field of water electrolysis catalysts, and discloses a NiFe-based bifunctional water decomposition electrocatalyst, a preparation method and application thereof, the catalyst is a core-shell heterostructure, a three-dimensional self-supporting NiFe-based OER / HER bifunctional electrocatalyst, specifically, a coral spherical NiFe-LDH coated basic cobalt carbonate nanowire nanomaterial NiFe-LDH@Co-CH / NF with a three-dimensional hierarchical porous core-shell heterostructure; the catalyst is prepared by a two-step method of hydrothermal and solvothermal, and the foam nickel is used as a conductive substrate, the inner layer is the basic cobalt carbonate nanowire, and the outer layer is the NiFe-LDH nanosheet. The catalyst has excellent OER and HER performance, significantly accelerates the diffusion and transfer of the electrolyte solution, excites the synergistic effect and electron transfer, and improves the catalytic activity of the catalyst. The water electrolysis system assembled by the catalyst has excellent water electrolysis performance, and has a wide application prospect.

Semiconductor arrangement (1) comprising: at least one semiconductor component (10) with a functional layer stack (2), wherein the functional layer stack (2) comprises a first layer (4) of a first conductivity type, a second layer (5) of a second conductivity type arranged on the first layer (4), an active zone located between the first and the second layer (4, 5), and an electrically conductive nanowire layer (9), and wherein the electrically conductive nanowire layer (9) is arranged at least partially on one side of the second layer (5) facing away from the first layer (4); and a retaining layer (14) with at least one protrusion (23); wherein the at least one semiconductor component (10) is arranged on the at least one protrusion (23) such that a cavity is formed between the at least one semiconductor component (10) and the retaining layer (14) and the nanowire layer (9) is at least partially exposed.

Devices, integrated circuit transistor structures, systems, and techniques are described herein related to gate all around field effect transistor circuits having an n-type transistor integrated with a p-type transistor. Each have a stack of nanowires contacted by source and drain structures at opposite ends of the nanowires. The nanowires of the n-type transistor have a layer including lanthanum on the nanowires, and the nanowires of the p-type transistors are absent the layer including lanthanum. The gate structures of the n-type transistor and the p-type transistor have the same gate dielectric, work function metal, and bulk metal.

This invention discloses a method based on Ti3C2T x The fabrication method of MXene's flexible pressure sensor includes the preparation of carbon nanotube coils, Ti3C2Tx powder preparation, and Ti3C2T... x The process involves steps such as MXene fabrication, PDMS solution preparation, mold selection, and thin film coating. This invention utilizes Ti3C2T, which exhibits good responsiveness and high sensitivity. x MXene is incorporated into PDMS to improve the shortcomings of traditional sensors with insignificant response. The porous nature of the composite structure makes the material compressible, improves the contact of the conductive layer, and enhances the resistance change. Through the conversion of "pressure → deformation → resistance change", it can be used to sensitively capture strain signals such as motion.

The application discloses a kind of based on silicon oxide nanowire polyelectrolyte membrane preparation method and high-efficiency adsorption to heavy metal ions, and its technical scheme main points are: a kind of polyelectrolyte membrane preparation method based on silicon oxide nanowire SiO2 NWs, and polyelectrolyte composite membrane can effectively adsorb heavy metal ions.The application is successfully synthesized by using layer-by-layer assembly method (LBL) by suction filtration device, three-dimensional self-supporting membrane with high efficiency, large capacity and controllable morphology.The specific steps include preparation of SiO2 NWs, amination of SiO2 NWs, and suction filtration to form SiO2 NWs membrane combined layer-by-layer self-assembly technology to finally prepare three-dimensional self-supporting polyelectrolyte composite membrane.The application has simple process, safe operation, and certain practical application prospect.The porosity of polyelectrolyte membrane is high, and it has good heavy metal adsorption and desorption capacity, so it is an ideal membrane adsorption material.

Integrated circuit structures having pre-epitaxial deep via structures, and methods of fabricating integrated circuit structures having pre-epitaxial deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends to the conductive trench contact structure. The conductive via has an uppermost surface above an uppermost surface of the epitaxial source or drain structure.

An AgCuTe nanowire composite material, its preparation method, and its application in medical antibacterial gauze are disclosed. The material consists of two phases: Cu7Te4 and Ag2Te, exhibiting a one-dimensional nanowire morphology with uniform silver distribution and nanowire diameters ranging from 7 to 9 nm. This material is prepared via a tellurium nanowire template combined with a two-step liquid-phase displacement reaction. First, tellurium nanowires are synthesized hydrothermally, followed by sequential reactions with copper and silver sources at room temperature to obtain the product. The AgCuTe nanowires exhibit concentration-dependent and power-dependent photothermal heating effects under 808 nm near-infrared light irradiation, with good photothermal stability. Under near-infrared light irradiation, the material demonstrates significant synergistic antibacterial activity against Staphylococcus aureus and Escherichia coli. Loading this material onto medical gauze can produce a near-infrared responsive photothermal antibacterial dressing for wound care and infection control, without antibiotic dependence, thus helping to reduce the risk of bacterial resistance.

Integrated circuit structures with a uniform grid-metal gate and trench contact interface for cFET architectures are described. In one example, a structure comprises a first vertical stack of horizontal nanowires above a second vertical stack of horizontal nanowires, with an intermediate insulator structure positioned vertically between the first and second vertical stacks. A gate structure is located above the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires, and the intermediate insulator structure. A conductive trench contact is adjacent to the gate structure. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact.The first and second dielectric cut plug structures extend through the gate structure, through the dielectric sidewall spacer, and through the conductive trench contact.

This invention discloses a method and application for in-situ decarburization of SiC nanowires to reinforce dental all-ceramic materials, belonging to the field of biomedical ceramics technology. The method includes the following steps: first, SiC nanowires are prepared by polycondensation and carbothermal reduction using organosilicon and carbon sources as raw materials; then, they are mixed with a dispersion medium, dispersant, PVA solution, and 5Y-PSZ ceramic powder to prepare a composite powder; subsequently, a green body is prepared by spray granulation and dry pressing; finally, the finished product is obtained through atmospheric pressure sintering, decarburization treatment, and secondary sintering. This invention uses SiC nanowires as a precursor, doping and decarburizing 5Y-PSZ to in-situ transform the SiC nanowires into SiO2 nanowires. This achieves crack deflection, bridging, and pull-out strengthening of the nanowires themselves, while simultaneously forming synergistic strengthening with the compressive stress generated by decarburization, significantly improving the mechanical properties of the material. This solves the problems of insufficient strength and mismatch between the nano-reinforcing phase and the matrix interface in materials prepared by existing technologies.

Integrated circuit structures having uniform grid metal gate and trench contact cut for cFET architectures are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires, with an intervening insulator structure vertically between the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires. A gate structure is over the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires, and the intervening insulator structure. A conductive trench contact is adjacent to the gate structure. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. First and second dielectric cut plug structures are extending through the gate structure, through the dielectric sidewall spacer, and through the conductive trench contact.

This invention relates to the field of sensing technology, providing a method for preparing and applying a conductive nanofiber membrane. The preparation method includes: preparing a polycaprolactone / β-cyclodextrin / graphene composite nanofiber membrane by electrospinning; after amination treatment, sequentially constructing a conductive catalytic interface on its surface through gold seed adsorption and in-situ growth of gold nanowires; integrating the resulting functionalized membrane into the working electrode region of a three-electrode chip, and further bonding it with PDMS microfluidic channels to construct a biomimetic chamber. This invention combines a cell culture interface with an electrochemical sensing interface, enabling in-situ, real-time, and dynamic electrochemical monitoring of nitric oxide released by vascular endothelial cells in a microfluidic system simulating a physiological environment, providing an innovative technical means for real-time assessment of vascular endothelial function and related pathological research.

This invention discloses a method for synthesizing a bifunctional PdCu catalyst for electrocatalytic hydrogenation-coupled oxidation of HMF. The method involves chemically oxidizing a copper foam framework to induce in-situ growth of nanowire structures on the surface of the copper foam nanowire substrate. A palladium salt is used as the palladium source and loaded onto the copper foam nanowire substrate in a cluster form. The prepared catalyst possesses a nanowire structure that facilitates the loading of Pd clusters, generating more active sites. The Pd clusters provide active hydrogen (H*) to accelerate electron transport, thereby achieving efficient hydrogenation of high-concentration HMF to BHMF at the cathode. Simultaneously, when applied to the anode, it enables efficient HMF conversion to FDCA. This material is suitable for the continuous production of high-value-added products FDCA and BHMF through electrocatalytic hydrogenation-coupled oxidation. The catalyst exhibits high activity, high stability, and high electron utilization, demonstrating significant potential for industrial application.

The application relates to a porous SiCN nw composite wave-absorbing ceramic and a preparation method thereof, and belongs to the field of ceramic-based wave-absorbing materials. The porous SiCN nw composite wave-absorbing ceramic comprises a porous Si3N4 ceramic matrix, a carbon layer uniformly wrapped on the pore wall surface of the porous Si3N4 ceramic matrix, and SiCN nanowires uniformly grown in the pores of the porous Si3N4 ceramic matrix; wherein the total mass of the carbon layer and the SiCN nanowires is 1-10 wt% of the porous Si3N4 ceramic matrix. By introducing the carbon layer and the SiCN nanowires with different structures into the pore structure of the Si3N4 matrix ceramic, the two components of the wave-absorbing phase can synergistically exert the advantages of each component, optimize the impedance matching degree of the material, and broaden the absorption bandwidth of the material. Moreover, the process is simple, the proportion of the two wave-absorbing phases can be regulated by changing the heat treatment temperature, the impedance matching degree of the material is optimized, and the prepared porous SiCN nw composite ceramic has good wave-absorbing performance.