2955 results about "Thermal oxidation" patented technology

There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.

A water blocking gel which is compatible with polyolefin optical fiber cable buffer tubes is disclosed. The water blocking gel comprises a polyolefin oil, wherein only a very small fraction of the polyolefin species have a molecular weight below about 2000. The gel also includes a thixotropic agent, and a thermal oxidation stabilizer. The gel is relatively low cost, does not cause substantially swelling of the polyolefin buffer tubes in contact therewith and does not degrade the buffer tube's physical properties.

Gate electrodes with selectively tuned channel thicknesses are formed by selective epitaxial growth. Embodiments include forming shallow trench isolation regions in an SOI substrate, selectively removing the nitride stop layer and pad oxide layer in an exposed particular active region, and implementing selective epitaxial growth to increase the thickness of the semiconductor layer in the particular active region. Subsequently, the remaining nitride stop and pad oxide layers in other active regions are removed, gate dielectric layers formed, as by thermal oxidation, and the transistors completed.

An on-line sensing system and method for monitoring in real-time thermal-oxidative breakdown, water contamination, and/or fuel dilution conditions in operational engine lubricating oils. The method of the invention includes an electrochemical impedance analysis technique specific to the particular oil to be monitored. Sensing devices having of at least two electrodes are configured for direct installation in an existing access port, or drain port, of a lubricating oil reservoir. An AC voltage waveform is applied to the sensing device (preferably less than 100 Hz) to produce voltage and current responses between the appropriate electrodes contacting the oil. The magnitude impedance |Z| and phase angle components of the complex impedance are used to characterize the quality and/or condition of the engine oil under test. The system also provides an electrical indication indicative of the percentage remaining useful life of the oil.

The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

The invention discloses a polydopamine-based biofunction modification method. The method comprises the following steps of: soaking clean inorganic/metal materials in dopamine alkaline aqueous solution with a pH value of 7.2 to 10, introducing oxygen to fully oxidize the clean inorganic/metal materials to obtain a monolayer polydopamine modification layer, drying, placing the material in the air atmosphere at 50 to 200 DEG C, performing thermal oxidation to obtain a multi-layer firmly-combined high-reactivity polydopamine layer, and soaking the treated material into the amino-containing and sulfydryl-containing biofunctional molecular solution to obtain a firmly combined biofunction simulate modification layer on the surface of the materials. The polydopamine modification layer obtained bythe method has excellent anti-deformation performance, stability and reactivity, can directly react with amino or the sulfydryl in the biomolecule to immobilize the bioactive molecule on the surface by covalent bonds; moreover, the process is simple, the condition is mild, and the method is easy to implement.

A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.

An embedded semiconductor memory is fabricated by: forming diffusion bit line regions in a semiconductor substrate; then thermally oxidizing the upper surface of the substrate, thereby forming a bottom oxide layer over the substrate and simultaneously forming bit line oxide regions over each of the diffusion bit line regions; and then forming an intermediate dielectric layer (e.g., silicon nitride), over the bottom oxide layer and the bit line oxide regions. CMOS well implants are then performed in a CMOS section of the device through the silicon nitride layer and bottom oxide layer. The silicon nitride layer and bottom oxide layer are then removed in the CMOS section, and a top dielectric layer, such as a high-temperature oxide or a high-k dielectric, is deposited. The top dielectric layer completes a memory stack of the memory device, and forms a gate dielectric layer of a high voltage transistor in the CMOS section.

Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin.

A semiconductor process and apparatus provide a planarized hybrid substrate (15) by thermally oxidizing SOI sidewalls (90) in a trench opening (93) to form SOI sidewall oxide spacers (94) which are trimmed while etching through a buried oxide layer (80) to expose the underlying bulk substrate (70) for subsequent epitaxial growth of an epitaxial semiconductor layer (96). In this way, SOI sidewall oxide spacers (94) are formed that prevent epitaxial SOI sidewalls from being formed in the trench opening (93) during the epitaxial growth step, and that can be readily removed during any subsequent STI etch process

A method for manufacturing an optical micro-mirror including a fixed part and a moveable part, with a reflection device connected to the fixed part by an articulation mechanism. This method realizes a stack including a mechanical substrate, a first layer of thermal oxidation material, and at least one second layer of material for forming the moveable part, realizes the articulation mechanism, realizes the reflection device on the second layer, realizes the moveable part by etching of at least the second layer of material, and eliminates the thermal oxidation layer to liberate the moveable part. Such an optical micro-mirror may find possible applications to optical routing or image projection systems.

The invention concerns a method for oxidizing a surface region of a SiGe layer that includes an oxidizing thermal treatment of the SiGe layer for oxidizing the surface region. The method includes two phases—a first phase of oxidizing thermal treatment, carried out directly on the SiGe layer, so as to obtain an oxidized region which is thick enough for forming a capping oxide which can protect the underlying SiGe from pitting during the subsequent second phase, but thin enough for keeping the thickness of the oxidized surface region under a threshold thickness range, corresponding to the generation of dislocations within the SiGe layer; and—a second phase of high temperature annealing in an inert atmosphere which is carried out on the SiGe layer after the first phase. The SiGe layer is capped with the oxidized region created during the first phase, and the high temperature annealing allows the diffusion of Ge from a Ge-enriched region into the underlying part of the SiGe layer.

A high dielectric film is formed by utilizing atom injection into a film through ion implantation or the like, and heat treatment. For example, an SiO2 film 102 which is a thermal oxide film is formed on a silicon substrate 101, and then Zr ions (Zr+) are injected from a plasma 105 into the SiO2 film 102. Thereafter, by annealing the SiO2 film 102 and a Zr injected layer 103, injected Zr is diffused in the Zr injected layer 103 and then the SiO2 film 102 and the Zr injected layer 103 are as a whole changed into a high dielectric film 106 of a high dielectric constant formed of Zr-Si-O (silicate). By using the high dielectric film 106 as an insulating film for an MISFET, an MISFET having excellent gate leakage properties can be achieved.

The invention provides an extreme pressure antiwear additive and a preparation method and application thereof; the extreme pressure antiwear additive has a general formula structure as shown in the specification, wherein R1, R2 and R3 in the formula is respectively alkyl groups, aryl groups or aralkyl of a C4-C20 linear chain or branched chain. The extreme pressure antiwear additive provided by the invention is formed by reacting phosphorus oxychloride, C1-C20 alcohols, organic amine and benzotriazole. The extreme pressure antiwear additive provided by the invention can be applied to lubrication oil and lubricating grease with 0.1-2.0wt% of recommended dosage. The extreme pressure antiwear additive provided by the invention has moderate chemical activity, good oil solubility, very good compatibility with other addition agents, no peculiar smell and good thermal oxidation stability, and can effectively reduce the abrasion of devices and oil sedimentation as well as generation of oil sludge. After applied to gear oil, the extreme pressure antiwear additive has excellent antiwear performance and thermal oxidation stability; and simultaneously the extreme pressure antiwear additive can be applied to a lubricating grease and automatic transmission liquid and hydraulic oil of automobiles.

An embodiment of a phase change TIM of this invention comprises a polyester matrix with melting temperature near or below operating temperature (typically less than about 130° C.), thermally conductive filler with bulk thermal conductivity greater than about 50 W/mK, and optionally other additives. The polyester resin has improved thermo-oxidative stability compared to the polyolefin resins, thereby providing improved reliability performance during test.

A thermal oxidizer is provided in which off-gases in a process stream are thermally oxidized within substantially the entire interior volume of an oxidation chamber. The thermal oxidation is conducted without the presence of a flame or with only a minor portion of the fuel being combusted in a flame.

A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800.degree. C.