36 results about "Smart Cut" patented technology

There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.

A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

The invention provides a semiconductor structure on an insulation layer with low dielectric constant material as the insulation buried layer and the preparation method thereof, which belongs to the microelectronic semiconductor material and the preparation craft thereof. The invention is characterized in that the structure comprises three layers: a semiconductor layer at the top, an insulation buried layer with the relative dielectric constant being smaller than 4.2 in the middle and a silicon substrate on the lower layer. The preparation is characterized in that low dielectric constant film is prepared on a silicon wafer by utilizing methods such as a chemical vapor deposition method or a sol gel method, then linked with the silicon wafer containing the semiconductor layer, and the transfer of the semiconductor layer at the top is realized by adopting a smart-cut technology or a back grinding technology. The low dielectric constant material is adopted to replace the prior SiO2 buried layer in the silicon (SOI) on the insulation layer, in order to reduce the capacitance of the insulation buried layer, thus increasing the equivalent impedance (1/2 Pi fC) of the buried layer under high frequency, therefore, compared with the prior SOI substrate material, the invention can reduce the signal crosstalk via the substrate under high frequency, thereby being more suitable for the requirement of a low-noise SOI circuit.

Disclosed are devices and methods for chemical and mechanical polishing of the edge of a semiconductor substrate that includes a protruding residual topography in a peripheral region of the substrate resulting from a layer transfer process based on an ion implantation step, a bonding step and a detachment step, such as Smart-Cut™. To be able to remove this step-like region, exemplary devices include a polishing pad, wherein the polishing pad is arranged and configured such that its cross section in a plane perpendicular to the surface of a substrate holder is curved. The disclosure furthermore relates to a pad holder used certain exemplary devices and methods for polishing a semiconductor substrate that has a protruding residual topography.

In the process of fabricating an SOI wafer based on the Smart Cut® Process, a stack 34 of an SOI wafer 39 and a residual wafer 38 are separated into the individual wafers using a wafer separation jig 1 of this invention. The wafer separation jig 1 comprises a supporting plane 1p on which the stack 34 is supported in the thickness-wise direction, and a stepped portion 2 disposed on the supporting plane 1p, and having a height adjusted so as to stop movement-by-sliding of the lower wafer of the stack, but so as to allow movement-by-sliding of the upper wafer relative to the lower wafer. Both wafers are separated from each other by inclining the supporting plane 1p with the stack 34 placed thereon, so as to allow the upper wafer to move by sliding as being driven by its own weight in the in-plane direction relative to the lower wafer. This method is successful in effectively suppressing friction between the wafers, and thus in preventing the wafer surface from being scratched.

The invention provides a graphical silicon-on-insulator (SOI) substrate material and a preparation method thereof. The preparation method comprises the steps of 1) providing an SOI substrate comprising bottom silicon, a buried oxide layer and top silicon, and forming an insulating layer on the surface of the top silicon; 2) forming an etching window corresponding to a position for preparing a transistor channel; 3) etching the insulating layer to form a groove penetrating through the top silicon; 4) providing a silicon substrate, and bonding the silicon substrate and the insulating layer; 5) removing the bottom silicon; and 6) removing the buried oxide layer. The groove is formed in the insulating layer corresponding to the position for preparing the transistor channel, and the groove completely penetrates through the space between the top silicon and the bottom silicon, so that a hollowed area is formed below the transistor channel prepared later. In the substrate preparation process, annealing and peeling steps in a Smart-cut method are avoided while the quality of the material is guaranteed, so that the problem of breakage of the top silicon in the graphical area due to high stress is solved.

There is provided a process for producing an SOI wafer in which, when producing an SOI wafer using Smart Cut technology, the surface can be smoothed after cleaving, the thickness of the SOI layer can be reduced, and the film thickness of the SOI wafer can be made uniform. In this process for producing an SOI wafer, hydrogen gas ions are implanted via an oxide film in a silicon wafer that is to be used for an active layer, so that an ion implanted layer is formed in the silicon bulk. Next, this active layer silicon wafer is bonded via an insulating film to a base wafer. By heating this base wafer, a portion thereof can be cleaved using the ion implanted layer as a boundary, thereby forming an SOI wafer. After the cleaving has been performed using the ion implanted layer as a boundary, the SOI wafer undergoes oxidization processing in an oxidizing atmosphere. This oxide film is then removed by, for example, HF solution. Thereafter, the SOI wafer undergoes heat processing for approximately three hours in an argon gas atmosphere at 1100° C. or more. As a result, the root mean square roughness of the SOI wafer surface is improved to 0.1 nm or less.

The invention provides a preparation method of a gate oxide integrity (GOI) wafer structure, which comprises the following steps that firstly, a SiGe-on-insulator (SGOI) wafer structure is prepared through a Smart-Cut technology, then germanium concentration is carried out on the SGOI wafer structure, and the GOI wafer structure is obtained. Because the SGOI which is prepared through the Smart-Cut technology basically is not mismatched or dislocated on an SGOI/BOX interface, the penetrated dislocation of the GOI is finally reduced. According to the preparation method of the GOI wafer structure, the process is simple, the high-quality GOI wafer structure can be realized, a germanium concentration technology is greatly improved, an ion injection technology and an annealing technology are very mature processes in the current semi-conductor industry, and the preparation method greatly improves the wide application possibility of germanium concentration in the semi-conductor industry.

The invention provides a method for preparing a semiconductor material through ion injection and fixed-point adsorption technologies. The method comprises the steps of firstly extending at least one period of an SixGe1-x/Si superlattice structure (x is greater than or equal to 0 and smaller than 1) on an Si substrate, sequentially growing an Si buffer layer and an SizGe1-z layer on the superlattice structure, then injecting H or He ions into the Si substrate and performing rapid annealing treatment, so as to ensure that the superlattice structure is adsorbed to the ions, and finally obtaining an SizGe1-z layer with low defect concentration and high relaxation. By bonding with the Si substrate with an oxidation layer, SGOI with low defect concentration and high relaxation can be prepared through smart cut, strained silicon with the thickness being smaller than the critical thickness is expanded on the obtained relaxation SizGe1-z layer, and strained silicon (sSOI) with high relaxation and low defect concentration on insulators can be prepared through smart cut. The method improves the stability of relaxation SiGe material prepared through ion injection through superlattice adion, obtains SiGe material with low defect concentration and high relaxation, reduces the technology difficulty, and is applicable to industrial production.

The invention provides a manufacturing method of a multilayer nanowire structure. The manufacturing method comprises the following steps: a. providing a first silicon matrix and forming a first oxide layer on the first silicon matrix, b. providing a second silicon matrix, injecting hydrogen ions into the second silicon matrix, forming a position mark on the second silicon matrix, c. cutting the first silicon matrix intelligently and forming an insulator upper silicon structure on the first silicon matrix, d. forming a second oxide layer on the insulator upper silicon structure, e. repeating step b and step d, forming a multilayer insulator upper silicon structure on the first silicon matrix, f. defining the graph of the multilayer nanowire structure, g. etching the multilayer isolator upper silicon structure to form a multilayer nanowire structure on the first silicon matrix, and h. removing the second oxide layer under the nanowires in the multilayer nanowire structure. By means of the manufacturing method of the multilayer nanowire structure, the crystal orientations of the nanowires are different.

The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a Smart-Cut technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.

The invention discloses an intelligent device for cutting photovoltaic cells in the technical field of cutting intelligence. The placement plate is movably connected to the fixed block through a rotating shaft. The front end of the hydraulic device is provided with a lifting rod. The inner cavity of the collection bin is uniformly provided with three sets of partitions from left to right. The inner wall is provided with a protective layer, and the left and right sides of the rear end surface of the collection bin are provided with connecting blocks, and the end of the connecting block away from the collection bin is provided with a fixed plate, and the fixed plate is rollingly connected to the wheel through a fixed bearing. , Add a telescopic rod and a placement tray on the conveyor belt, and the placement tray reaches a certain angle through the lifting of the telescopic rod and then falls to the workbench, and a collection bin is set up to effectively collect the cut batteries.

The present invention provides a method for manufacturing a thin film on a substrate. The method comprises the following steps that: an original substrate is provided; an ion separation layer is formed in the original substrate by using an ion implantation method, so that a thin film layer and a remaining medium layer can be formed on the original substrate through the ion separation layer, wherein the thin film layer is a region for bearing ion implantation in the original substrate, and the remaining medium layer is a region where no ions are implanted; a target substrate is bonded to the original substrate through a wafer bonding method, so that the target substrate and the original substrate can be bonded to a bonded structural body; and the bonded structural body is heated, and laseris adopted to irradiate the bonded structural body, so that the thin film layer and the remaining medium layer can be separated from each other, and the thin film layer can be transferred from the original substrate to the target substrate, and the heating temperature of the bonded structural body is higher than room temperature and conversion temperature that enables the dielectric constant and loss factor of the bonded structural body to be converted, and is lower than temperature that activates a smart cut method.

The invention discloses an ultrasonic composite cotton intelligent slitting and cutting machine and a subsequent slitting mechanism. The material is discharged in the discharging mechanism, embossed through the ultrasonic composite structure, and then passes through the inspection platform, the material storage mechanism, and the material cutting mechanism, and finally from the Discharge table, novel structure, easy to use, short embossing time, strong adhesion, clear embossing, three-dimensional embossing effect on the surface, no pinholes and no water seepage in the finished product, with waterproof and warming effect; the embossing roller adjustment is simple and convenient , It is easy to change the roll, and can stitch out ever-changing and complex discontinuous and symmetrical patterns according to customer needs. The processing loss is low, the product is more flat and stable, and the cutting process does not stop, and the work efficiency is high.

The invention discloses a surface acoustic wave resonator with a double-layer POI structure and a manufacturing method. The resonator includes a substrate, a bottom POI structure over the substrate, an electrode over the bottom POI structure, and a top POI structure over the electrode. The bottom POI structure comprises a bottom high sound velocity layer, a bottom oxide layer and a piezoelectric film; the top POI structure comprises a top oxide layer and a top high-sound-velocity layer. The resonator manufacturing method comprises the following steps: sequentially depositing a bottom high-sound-velocity layer and a bottom oxide layer on a substrate, performing low-temperature bonding with one surface of a LiTaO3 piezoelectric film obtained by a smart cut method, depositing an electrode on the other surface of the piezoelectric film, and sequentially depositing a top oxide layer and a top high-sound-velocity layer on the electrode. The comprehensive performance of the surface acoustic wave resonator is greatly improved.