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23 results about "Stacking fault" patented technology
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In crystallography, a stacking fault is a type of defect which characterizes the disordering of crystallographic planes. It is thus considered a planar defect. The most common example of stacking faults is found in close-packed crystal structures. Face-centered cubic (fcc) structures differ from hexagonal close packed (hcp) structures only in stacking order: both structures have close-packed atomic planes with sixfold symmetry — the atoms form equilateral triangles. When stacking one of these layers on top of another, the atoms are not directly on top of one another. The first two layers are identical for hcp and fcc, and labelled AB. If the third layer is placed so that its atoms are directly above those of the first layer, the stacking will be ABA — this is the hcp structure, and it continues ABABABAB. However, there is another possible location for the third layer, such that its atoms are not above the first layer. Instead, it is the atoms in the fourth layer that are directly above the first layer. This produces the stacking ABCABCABC, which is actually along the [111] direction of a cubic crystal structure. In this context, a stacking fault is a local deviation from one of the close-packed stacking sequences to the other one. Usually, only one- two- or three-layer interruptions in the stacking sequence are referred to as stacking faults. An example for the fcc structure is the sequence ABCABABCAB.
Method for eliminating silicon carbide small stacking fault based on high-temperature oxidation
The invention belongs to the technical field of third-generation semiconductor material defect control. According to the method for eliminating the silicon carbide small stacking fault based on high-temperature oxidation, a silicon carbide substrate is scanned and represented in a photoluminescence mode, and the target small stacking fault is accurately recognized and positioned; cleaning the substrate to remove surface impurities, performing high-temperature oxidation treatment in a dry oxygen atmosphere, and growing an oxide layer under control; constructing a composite interface stress field at an interface by utilizing thermal expansion coefficient mismatch and reaction molar volume expansion between the oxide layer and the substrate, and driving target stacking fault atom arrangement to generate directional reconstruction, so that the target stacking fault atom arrangement is converted into a matrix standard sequence; and finally, nitric oxide auxiliary annealing is carried out, and the reconstructed lattice configuration is solidified by utilizing a nitrogen passivation effect. The method is simple in process and high in compatibility, small stacking fault can be efficiently and stably eliminated, the silicon carbide substrate crystal quality is remarkably improved, and a guarantee is provided for preparation of a high-reliability power device.
Owner:SHANDONG UNIV
One-dimensional zigzag ultrathin Pt-based nanoshell catalyst coated on carbon nanotube and having rich defects and preparation method of one-dimensional zigzag ultrathin Pt-based nanoshell catalyst
The invention relates to the field of carbon-loaded nano-catalysts, in particular to a one-dimensional zigzag ultrathin Pt-based nano-shell catalyst which is coated on a carbon nanotube and has abundant defects and a preparation method of the one-dimensional zigzag ultrathin Pt-based nano-shell catalyst. According to the catalyst, a carbon nanotube film is used as a substrate, magnetron sputtering is carried out at room temperature, then rapid annealing is carried out, and finally a one-dimensional zigzag ultrathin Pt-based nano shell is formed and uniformly coats a carbon nanotube bundle. The ultrathin Pt-based nano shell has abundant surface structures (high-index edge steps) and a large number of crystal defects such as twin crystals and stacking faults, the electronic structure of surface atoms is adjusted, and the adsorption / desorption strength of an intermediate is optimized, so that the catalytic activity is influenced. According to the method, efficient and controllable preparation of the defect type Pt-based nanowire catalyst is achieved, the activity and stability of the catalyst are improved, the method can be suitable for various catalytic reactions related to fuel cells, and the method is expected to be a practical method for large-scale preparation and application of the catalyst.
Owner:INST OF METAL RESEARCH - CHINESE ACAD OF SCI
A method for preparing a low surface defect epitaxial wafer on a high COP silicon single crystal substrate
This invention relates to a method for preparing low-surface-defect epitaxial wafers on high-COP silicon single-crystal substrates, comprising the following steps: S1, substrate preparation: selecting a high-COP silicon single-crystal substrate; S2, single-sided polishing: polishing the high-COP silicon single-crystal substrate using conventional single-sided polishing equipment to remove the mechanical damage layer on the substrate surface and obtain a preliminarily planarized surface; S3, improved polishing and cleaning process; S4, epitaxial growth of qualified substrate: performing epitaxial growth on the qualified substrate to prepare a low-surface-defect epitaxial wafer. This invention improves the polishing and cleaning processes, thoroughly removing residues within COP voids and suppressing the generation of epitaxial stacking faults, thereby achieving the preparation of high-quality, low-surface-defect epitaxial wafers.
Owner:QL ELECTRONICS (QUZHOU) CO LTD
Method for detecting stacking fault defect of heavily doped silicon wafer
PendingCN121830710APreparing sample for investigationOptically investigating flaws/contaminationStacking faultPhysical chemistry
The invention provides a method for detecting stacking fault defects of heavily doped silicon wafers, which belongs to the technical field of silicon wafer detection, and comprises the following steps of: cleaning dirt and impurities on the surfaces of the silicon wafers in advance to remove interference factors on the surfaces of the silicon wafers, and then carrying out chemical corrosion to gradually expose the stacking fault defects of the silicon wafers. The method comprises the following steps of: coating CuSO4. 5H2O, carrying out heat treatment to carry out copper decoration to enhance the contrast ratio of the defect and a substrate, and finally carrying out preferred corrosion to expose the enhanced defect, so that the macroscopic detection of the stacking fault defect can be carried out in a darkroom, the detection cost is low, the result is accurate, and the detection efficiency is improved.
Owner:FERROTEC (NINGXIA) SEMICON TECH CO LTD
Silicon carbide crystal growth device
PendingCN122082104APolycrystalline material growthFrom condensed vaporsCarbide siliconStacking fault
This invention discloses a silicon carbide crystal growth apparatus, comprising: a crucible, a seed crystal holder, silicon carbide powder, a filter plate, and a crucible lid. The crucible has a mouth; the seed crystal holder is disposed inside the crucible, with a seed crystal disposed on the side of the seed crystal holder facing away from the mouth; the silicon carbide powder is disposed inside the crucible and located below the seed crystal, with a powder evaporation zone formed on the side of the silicon carbide powder facing the seed crystal, the diameter ratio of the powder evaporation zone to the seed crystal being D, wherein 1.4 ≤ D ≤ 1.6; the filter plate is disposed inside the crucible and located between the silicon carbide powder and the seed crystal; and the crucible lid is disposed on the mouth of the crucible. This silicon carbide crystal growth apparatus can improve the growth rate of large-size silicon carbide single crystals and control defects such as dislocation density and stacking faults to a low level, thereby meeting the demand for large-size and high-quality silicon carbide single crystals in high-end applications.
Owner:JIANG SU JI XIN XIAN JIN CAI LIAO YOU XIAN GONG SI
Low-fault-energy high-entropy alloy and preparation method thereof
PendingCN121988751AHigh Al+Ti contentImprove plasticityAdditive manufacturing apparatusHigh entropy alloysSurface oxidation
The invention discloses a preparation method of a low-fault-energy high-entropy alloy, which comprises the following steps: (1) weighing spherical CoCrNiAl alloy, Co powder, Cr powder, Ni powder and Ti powder according to a stoichiometric equation AlaTibNicCodCre, (2) putting the weighed powder into a ball milling tank for ball milling, uniformly mixing the powder, and then drying, sieving and drying for storage; (3) 304L stainless steel is selected as a base material, and a sand mill is used for polishing the surface of the base material to remove surface oxide skin until a bright surface is exposed; and (4) a laser directional energy deposition method is adopted, the dried powder is placed in a powder feeding tank in a laser system, high-purity Ar gas is used for feeding the powder to a round spot laser head for melting and stacking, and layer-by-layer continuous deposition is conducted. The generation and expansion of cracks in laser additive manufacturing can be inhibited by reducing the stacking fault of a high-entropy alloy system, a large number of coherent L12 phases can be separated out in situ, and the excellent mechanical property is achieved at the normal temperature.
Owner:GUIZHOU UNIV +2
An apparatus and method for reducing the density of threading dislocation defects in silicon carbide crystals
PendingCN122235835APolycrystalline material growthFrom condensed vaporsCarbide siliconThreading dislocations
This application provides an apparatus and method for reducing the density of through-type dislocation defects in silicon carbide crystals. The apparatus includes an insulation component formed by an upper insulation layer, a first outer insulation layer, and a lower insulation layer. The insulation component is provided with gas exchange channels. By placing a crucible containing a silicon carbide seed crystal and silicon carbide raw material into the insulation component and placing them together into a single crystal growth furnace, silicon carbide crystal is grown according to the parameters set for each growth stage to obtain an N-type silicon carbide crystal. When in the isothermal section, N2 is introduced into the single crystal growth furnace in a cycle of n periods according to a first flow rate state and a second flow rate state. Nitrogen is intentionally doped into the silicon carbide crystal during the growth process through the gas exchange channels to increase the conversion probability and ejection probability of through-type dislocations to basal plane dislocations and stacking faults in the N-type silicon carbide crystal. This solves the problem of high dislocation density in SiC single crystals grown by the current PVT method.
Owner:GUANGZHOU SUMMIT CRYSTAL SEMICON CO LTD
Method for determining the silicon and carbon faces of 3c-sic single crystal wafers
ActiveCN121207971BPreparing sample for investigationMaterial analysis by optical meansWaferingStacking fault
The application provides a method for determining the silicon face and carbon face of a 3C-SiC single crystal wafer, comprising the following steps: (1) immersing the 3C-SiC single crystal wafer into molten alkali for etching treatment; (2) taking out the etched 3C-SiC single crystal wafer and observing the surface morphology; if the surface only presents stacking fault characteristics, it is determined that the face is the () C face; if the surface simultaneously presents stacking fault and dislocation etching pit characteristics, it is determined that the face is the (111) Si face. The application first discovers and utilizes the inherent difference between the (111) Si face and the () C face of the 3C-SiC single crystal in the molten alkali etching morphology: the (111) Si face simultaneously presents stacking fault and dislocation etching pit, while the () C face only presents stacking fault. By observing the significant morphology contrast, the rapid and accurate discrimination of the two crystal faces can be realized.
Owner:INSTITUTE OF PHYSICS CHINESE ACADEMY OF SCIENCES
An ultrahigh-strength pure metal and a method for producing the same
ActiveCN119973103BTransportation and packagingMetal-working apparatusGrain Boundary SlidingStacking fault
The application provides an ultrahigh-strength pure metal and a preparation method thereof, and relates to the technical field of high-performance metal materials. The preparation method of the ultrahigh-strength pure metal provided by the application takes a nano pure metal powder as an initial raw material, and then forms a small block with a size of dozens of microns through high-pressure welding to form a dense pure metal without adding any alloy element. The pressure is a very pure regulation and control means, which can realize extreme strengthening of the nano metal without introducing any impurities. The pressure can effectively inhibit the grain boundary sliding of the nanocrystalline, can compact the nano metal powder to a certain extent, and can avoid grain coarsening, so that the deformation mechanism of the metal itself is activated, including various crystal defects such as full dislocation, partial dislocation, twinning, stacking fault and the like. The multiple types of defects interact with each other, generate strain fields and superimpose on each other, hinder the movement of dislocations, and then bring about strong work hardening and extreme strengthening, so that the pure metal finally realizes ultrahigh strength.
Owner:HARBIN INSTITUTE OF TECHNOLOGY (SHENZHEN) (INSTITUTE OF SCIENCE AND TECHNOLOGY INNOVATION HARBIN INSTITUTE OF TECHNOLOGY SHENZHEN) +1
Method for eliminating small stacking faults of silicon carbide based on high temperature oxidation
The application belongs to the technical field of third-generation semiconductor material defect control. A method for eliminating small-scale stacking faults of silicon carbide based on high-temperature oxidation is proposed. The silicon carbide substrate is scanned and characterized by photoluminescence, and the target small-scale stacking fault is accurately identified and positioned. Then, the substrate is cleaned to remove surface impurities, and high-temperature oxidation treatment is carried out in a dry oxygen atmosphere, and an oxidation layer is controlled to grow. The mismatch of the thermal expansion coefficient between the oxidation layer and the substrate and the reaction molar volume expansion are used to construct a composite interface stress field at the interface, drive the directional reconstruction of the atomic arrangement of the target stacking fault, and convert it into the standard sequence of the matrix. Finally, nitric oxide assisted annealing is carried out, and the nitrogen passivation effect is used to solidify the lattice configuration after reconstruction. The application has the advantages of simple process, strong compatibility, efficient and stable elimination of small-scale stacking faults, and significantly improved crystal quality of silicon carbide substrate, which provides a guarantee for the preparation of high-reliability power devices.
Owner:SHANDONG UNIV
Core / shell-type semiconductor nanoparticle and method for manufacturing same
These core / shell-type semiconductor nanoparticles each comprise: a core containing at least indium (In) and phosphorus (P); and a shell containing zinc (Zn) and sulfur (S) and / or selenium (Se). The core / shell-type semiconductor nanoparticles are characterized by: having stacking faults; containing a halogen; having a molar ratio of halogen to indium (In) of more than 15 but no more than 500 on an atomic basis; and having an average circularity of 0.820-1.000, which is found in a STEM image obtained by observation with a scanning transmission electron microscope. The present invention provides: core / shell-type semiconductor nanoparticles each comprising a core containing indium (In) and phosphorus (P) and a shell containing zinc (Zn) and sulfur (S) and / or selenium (Se); and a method for producing the same. With shells formed with high uniformity and having highly consistent shapes, the core / shell-type semiconductor nanoparticles exhibit a high luminous efficiency and a narrow FWHM even if stacking faults are present.
Owner:SHOEI CHEM IND CO LTD
Seed substrate for epitaxial growth use and method for manufacturing same, and semiconductor substrate and method for manufacturing same
ActiveUS12618172B2Polycrystalline material growthAfter-treatment detailsStacking faultSolid substrate
A seed substrate for epitaxial growth has a support substrate, a planarizing layer of 0.5 to 3 μm provided on the top surface of the support substrate, and a seed crystal layer provided on the top surface of the planarizing layer. The support substrate includes a core of group III nitride polycrystalline ceramics and a 0.05 to 1.5 μm encapsulating layer that encapsulates the core. The seed crystal layer is provided by thin-film transfer of 0.1 to 1.5 μm of the surface layer of Si<111> single crystal with oxidation-induced stacking faults (OSF) of 10 defects / cm2 or less. High-quality, inexpensive seed substrates with few crystal defects for epitaxial growth of epitaxial substrates and solid substrates of group III nitrides such as AlN, AlxGa1-xN (0<X<1) and GaN are obtained.
Owner:SHIN ETSU CHEMICAL CO LTD +1
Calibration bodies and methods for their manufacture
The invention relates to the fields of materials science and measurement technology and concerns calibration objects, such as those that can be used in analytical spectroscopy. The object of the present invention is therefore to produce electrically conductive calibration blocks, in particular for the calibration of hydrogen measuring instruments. The calibration blocks can be provided in large quantities, simply and cost-effectively. The problem is solved by calibration bodies, in particular for the calibration of hydrogen measuring instruments, consisting at least of an electrically conductive, porous sintered body with a substantially homogeneous distribution of pores and / or defects, such as dislocations, stacking faults and / or twins, in the sintered body, in which an adjustable hydrogen concentration is present depending on the number and size of the pores and / or defects in the sintered body, wherein the hydrogen is physically and / or chemically bound in and / or on the surface of the pores and / or defects, and wherein the set hydrogen concentration in the calibration body decreases in a specified amount over time.
Owner:TECH UNIV BERGAKADEMIE FREIBERG KORPERSCHAFT DES OFFENTLICHEN RECHTS
Silicon carbide semiconductor substrate, silicon carbide semiconductor device, method for inspecting a silicon carbide semiconductor substrate, and method for manufacturing a silicon carbide semiconductor device.
PendingJP2026068825ASemiconductor/solid-state device testing/measurementDevice materialStacking fault
This invention provides a silicon carbide semiconductor substrate, a silicon carbide semiconductor device, a silicon carbide semiconductor substrate inspection method, and a silicon carbide semiconductor device manufacturing method that can improve product yield by enabling the detection of crystal defects that do not affect device operation. [Solution] The silicon carbide semiconductor substrate inspection method is a method for inspecting a silicon carbide semiconductor substrate having an epitaxial layer. By differential interference contrast observation of the silicon carbide semiconductor substrate, it is determined whether the crystal defects of the silicon carbide semiconductor substrate are defects that have grown obliquely within the epitaxial layer. From the photoluminescence image of the silicon carbide semiconductor substrate, it is determined whether the defects are stacking faults that have grown trapezoidally within the epitaxial layer. By transmission polarization observation of the silicon carbide semiconductor substrate, it is determined whether the stacking faults are associated with through-helical dislocations.
Owner:FUJI ELECTRIC CO LTD +1
A NiAl alloy full-lamellar microstructure and its preparation method
This invention belongs to the field of non-equilibrium solidification technology, specifically relating to a NiAl alloy full-lamellar microstructure and its preparation method. The method includes the following steps: (1) preparing a NiAl-based alloy ingot; (2) constructing the NiAl-based alloy ingot into a high-pressure assembly; (3) placing the high-pressure assembly in a heating chamber and performing high-pressure solidification treatment using a press to obtain a NiAl alloy full-lamellar microstructure containing high-density twins and stacking faults; the pressure of the high-pressure solidification treatment is 6-8 GPa, and the temperature of the high-pressure solidification treatment is 1500-1650℃. This invention achieves the construction of a full-lamellar microstructure and the introduction of high-density crystal defects simultaneously in a one-step process through high-pressure solidification. The resulting lamellar structure is rich in nanotwins and stacking faults at the interior and interface. These substructures can effectively hinder dislocation movement, passivate crack propagation, and significantly improve the toughness and deformation capacity of NiAl alloy while enhancing the material strength.
Owner:QUZHOU UNIV
A high-performance magnesium alloy suitable for stirred additive manufacturing and a preparation and processing method thereof
This invention discloses a high-performance magnesium alloy suitable for stir additive manufacturing and its preparation and processing method. The magnesium alloy has the following composition: Gd 8.5-9.5wt%; Y 2.8-3.2wt%; Zn 1.3-1.7wt%; Ca 0.9-1.3wt%; Mn 0.4-0.8wt%; Sn 1.8-2.2wt%; with the balance being Mg and unavoidable impurities. The preparation and processing method of this magnesium alloy adopts a full-sequence processing technology of "melting → filtration → casting → ingot heating → extrusion blanking → solution treatment → cooling to build stacking faults → secondary extrusion molding → combined residual stress elimination → finishing". This invention achieves the synergistic goals of "eliminating LPSO structural phases, building stacking fault structures, reducing residual stress, controlling intragranular precipitates, and improving oxidation resistance" by precisely controlling the alloy composition range and element ratios and optimizing the entire process, thus obtaining soft raw material bars suitable for solid-state additive manufacturing.
Owner:GRIMAT ENG INST CO LTD
A lattice interlocking type lithium-rich manganese-based positive electrode material, a preparation method and application thereof
This invention provides a lattice-interlocked lithium-rich manganese-based cathode material, its preparation method, and its application, relating to the field of battery cathode material preparation technology. By introducing a certain amount of sodium ions during the synthesis process, highly stacked stacking faults are induced in a high-temperature chamber, further inducing the growth and fusion of surface defects to form a lattice-interlocked twin structure. This requires only one high-temperature sintering and one water washing process, improving the TM migration barrier and oxygen diffusion barrier, interrupting phase transition diffusion, solving the problem of cyclic instability in lithium-rich material structures, reducing stress and strain in layered materials during charge and discharge, greatly eliminating lattice stress, suppressing expansion and crystal plane slip during charge and discharge, and improving interface stability.
Owner:CHINA AUTOMOTIVE BATTERY RES INST CO LTD
Defect classification method, analysis method, and inspection device
The present invention relates to a defect classification method comprising: a step for projecting an illumination beam onto a silicon carbide substrate and scanning the position of the silicon carbide substrate with the illumination beam; a step for detecting the reflected light emitted from the silicon carbide substrate and photoluminescence including a visible region; and a step for classifying defects on the basis of the detection results of the reflected light and the detection results of photoluminescence including the visible region, the step for classifying defects including: classifying the defects as 3C-SF (3C-Stacking Fault), i.e., 3C-stacking fault, on the basis of the detection of a first defect image using the reflected light, and classifying the defects as 3C-SF (3C-Stacking Fault), i.e., 3C-stacking fault, on the basis of the detection of a second defect image using the reflected light. And a step for classifying the defect as a portrait-type stacking fault, which is an SSF (Sockley-type Stacking Fault), on the basis of the detection of a second defect image by means of photoluminescence including the visible region.
Owner:LASERTEC CORP
Drawing method of vacancy type heavily phosphorus-doped silicon single crystal for inhibiting epitaxial stacking fault
ActiveCN122039202APolycrystalline material growthBy pulling from meltCzochralski methodStacking fault
The invention discloses a drawing method of a vacancy type heavily phosphorus-doped silicon single crystal for inhibiting epitaxial stacking fault, the drawing method is a czochralski method, and in a crystal equal-diameter growth stage of the czochralski method, a ratio v / G is controlled, so that the v / G and a critical value xi meet a set relationship; wherein v is the crystal growth speed, and G is the average axial temperature gradient at a solid-liquid interface in the single crystal furnace; the critical value xi is a v / G critical value for drawing the heavily phosphorus-doped silicon single crystal, the value range of the critical value xi is [ximin, ximax], ximin is equal to 0.05 mm < 2 > / (DEG C * min), and ximax is equal to 0.06 mm < 2 > / (DEG C * min); the set relation is that v / G / ximax is greater than or equal to 1, and v / G / ximin is less than or equal to 1.8. According to the drawing method disclosed by the invention, the heavily phosphorus-doped silicon single crystal with the COP characteristic on the surface is stably obtained, the BMD distribution is uniform, the epitaxial layer grows on the prepared substrate, and the fault density is lower than 10 pieces / cm < 2 >.
Owner:QL ELECTRONICS (QUZHOU) CO LTD
Defect classification method, analysis method, and inspection apparatus
PendingUS20260098815A1Optically investigating flaws/contaminationFluorescence/phosphorescenceCarbide siliconPhotoluminescence
A defect classification method includes: projecting an illumination beam toward the silicon carbide substrate and scanning a position at which the silicon carbide substrate is illuminated with the illumination beam; detecting reflected light and photoluminescence light including light in a visible region, emitted from the silicon carbide substrate; and classifying the defects based on a result of the detection of the reflected light and a result of the detection of the photoluminescence light including the light in the visible region, in which the classifying the defects includes classifying the defect as a 3C-SF (Stacking Fault) based on detection of a first defect image by the reflected light and classifying the defect as an SSF (Shockley-type Stacking Fault) based on detection of a second defect image by the photoluminescence light including the light in the visible region.
Owner:LASERTEC CORP
A method for predicting steady-state creep rate of multi-element precious metal-based high-temperature alloy based on multi-scale integrated calculation
PendingCN122117133AChemical property predictionComputational theoretical chemistryShear modulusStacking fault
The present application relates to the technical field of multi-element precious metal-based high-temperature alloy, and discloses a multi-element precious metal-based high-temperature alloy steady-state creep rate prediction method based on multi-scale integrated calculation, which comprises the following steps: S1: crystal structures of the multi-element precious metal-based high-temperature alloy and intermetallic compounds are respectively constructed to obtain thermal physical properties of lattice constants, shear moduli, Poisson's ratios, stacking fault energies, diffusion activation energies and diffusion pre-exponential factors; S2: according to the CALPHAD method, the composition-dependent elastic moduli, stacking fault energies and lattice constant thermal physical properties of the multi-element precious metal-based high-temperature alloy are calculated; S3: the thermal physical properties of the multi-element precious metal-based high-temperature alloy single-phase fixed component in S1 and the composition-dependent thermal physical properties in S2 are respectively substituted into a steady-state creep rate model to respectively predict the steady-state creep rates of the multi-element precious metal-based high-temperature alloy changing with temperature and changing with composition. The present application can shorten the research and development cycle of the alloy and reduce experimental costs.
Owner:KUNMING UNIV OF SCI & TECH +1
Method for suppressing formation of stacking fault, structure produced by this method, and method for evaluating affected layer
PendingEP4484618A4Polycrystalline material growthSemiconductor/solid-state device testing/measurementStacking faultComputational physics
The problem to be solved is to provide a new technology capable of suppressing the formation of stacking faults. The problem to be solved is to provide a new technology capable of suppressing stacking defects formed during epitaxial growth on a semiconductor substrate. The present invention is a method for suppressing formation of stacking faults, comprising a subsurface damaged layer removal step S10 of removing a subsurface damaged layer 11 of a semiconductor substrate 10, a crystal growth step S20 of performing crystal growth on a surface from which the subsurface damaged layer11 is removed.
Owner:KWANSEI GAKUIN EDUCTIONAL FOUND +1