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43 results about "Stacking fault" patented technology
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In crystallography, a stacking fault is a type of defect which characterizes the disordering of crystallographic planes. It is thus considered a planar defect. The most common example of stacking faults is found in close-packed crystal structures. Face-centered cubic (fcc) structures differ from hexagonal close packed (hcp) structures only in stacking order: both structures have close-packed atomic planes with sixfold symmetry — the atoms form equilateral triangles. When stacking one of these layers on top of another, the atoms are not directly on top of one another. The first two layers are identical for hcp and fcc, and labelled AB. If the third layer is placed so that its atoms are directly above those of the first layer, the stacking will be ABA — this is the hcp structure, and it continues ABABABAB. However, there is another possible location for the third layer, such that its atoms are not above the first layer. Instead, it is the atoms in the fourth layer that are directly above the first layer. This produces the stacking ABCABCABC, which is actually along the [111] direction of a cubic crystal structure. In this context, a stacking fault is a local deviation from one of the close-packed stacking sequences to the other one. Usually, only one- two- or three-layer interruptions in the stacking sequence are referred to as stacking faults. An example for the fcc structure is the sequence ABCABABCAB.
Multi-mode detection method for small and medium-sized stacking fault defects of silicon carbide substrate
The invention belongs to the technical field of silicon carbide defect detection, and particularly relates to a multi-mode detection method for small and medium-sized stacking fault defects of a silicon carbide substrate, which comprises the following steps of: performing photoluminescence imaging on a silicon carbide substrate to be detected to obtain a candidate area of the small-sized stacking fault defects; performing microscopic photoluminescence spectrum two-dimensional mapping scanning on the candidate area to obtain a spectrum intensity mapping image in the candidate area; constructing a multi-modal matching model, performing spatial registration on a spectral intensity mapping image and a photoluminescence image, and determining a single small stacking fault defect by calculating a weighted pixel overlapping rate; microscopic photoluminescence spectrum two-dimensional mapping scanning is carried out on a single small stacking fault defect, and the morphology and size of the defect are determined. The method has the advantages of high sensitivity and high resolution, is suitable for rapid detection and online quality control of defects of the large-size silicon carbide substrate, and has a good industrial application prospect.
Owner:SHANDONG UNIV
Method for eliminating silicon carbide small stacking fault based on high-temperature oxidation
The invention belongs to the technical field of third-generation semiconductor material defect control. According to the method for eliminating the silicon carbide small stacking fault based on high-temperature oxidation, a silicon carbide substrate is scanned and represented in a photoluminescence mode, and the target small stacking fault is accurately recognized and positioned; cleaning the substrate to remove surface impurities, performing high-temperature oxidation treatment in a dry oxygen atmosphere, and growing an oxide layer under control; constructing a composite interface stress field at an interface by utilizing thermal expansion coefficient mismatch and reaction molar volume expansion between the oxide layer and the substrate, and driving target stacking fault atom arrangement to generate directional reconstruction, so that the target stacking fault atom arrangement is converted into a matrix standard sequence; and finally, nitric oxide auxiliary annealing is carried out, and the reconstructed lattice configuration is solidified by utilizing a nitrogen passivation effect. The method is simple in process and high in compatibility, small stacking fault can be efficiently and stably eliminated, the silicon carbide substrate crystal quality is remarkably improved, and a guarantee is provided for preparation of a high-reliability power device.
Owner:SHANDONG UNIV
Method for determining silicon surface and carbon surface of 3C-SiC single crystal wafer
ActiveCN121207971APreparing sample for investigationMaterial analysis by optical meansWaferingStacking fault
The invention provides a method for determining a silicon surface and a carbon surface of a 3C-SiC single crystal wafer, which comprises the following steps of: (1) immersing the 3C-SiC single crystal wafer into molten alkali for corrosion treatment; (2) taking out the corroded 3C-SiC single crystal wafer and observing the surface appearance of the 3C-SiC single crystal wafer; if the surface only shows the stacking fault characteristic, judging that the surface is a (C) surface; and if the surface has the characteristics of stacking fault and dislocation corrosion pits at the same time, determining that the surface is a (111) Si surface. According to the invention, the inherent difference of molten alkali on the corrosion morphology of the (111) Si surface and the (C) surface of the 3C-SiC single crystal is found and utilized for the first time: the (111) Si surface can present stacking fault and dislocation corrosion pits at the same time, and only the (C) surface has stacking fault. By observing the obvious morphology comparison, the two crystal faces can be quickly and accurately distinguished.
Owner:INSTITUTE OF PHYSICS CHINESE ACADEMY OF SCIENCES
One-dimensional zigzag ultrathin Pt-based nanoshell catalyst coated on carbon nanotube and having rich defects and preparation method of one-dimensional zigzag ultrathin Pt-based nanoshell catalyst
The invention relates to the field of carbon-loaded nano-catalysts, in particular to a one-dimensional zigzag ultrathin Pt-based nano-shell catalyst which is coated on a carbon nanotube and has abundant defects and a preparation method of the one-dimensional zigzag ultrathin Pt-based nano-shell catalyst. According to the catalyst, a carbon nanotube film is used as a substrate, magnetron sputtering is carried out at room temperature, then rapid annealing is carried out, and finally a one-dimensional zigzag ultrathin Pt-based nano shell is formed and uniformly coats a carbon nanotube bundle. The ultrathin Pt-based nano shell has abundant surface structures (high-index edge steps) and a large number of crystal defects such as twin crystals and stacking faults, the electronic structure of surface atoms is adjusted, and the adsorption / desorption strength of an intermediate is optimized, so that the catalytic activity is influenced. According to the method, efficient and controllable preparation of the defect type Pt-based nanowire catalyst is achieved, the activity and stability of the catalyst are improved, the method can be suitable for various catalytic reactions related to fuel cells, and the method is expected to be a practical method for large-scale preparation and application of the catalyst.
Owner:INST OF METAL RESEARCH - CHINESE ACAD OF SCI
N-type silicon carbide single crystal, n-type silicon carbide substrate, and semiconductor device
PCT designated stageWO2025227621A1Polycrystalline material growthFrom condensed vaporsSemiconductor materialsWafering
An n-type silicon carbide single crystal, an n-type silicon carbide substrate, and a semiconductor device, belonging to the technical field of semiconductor materials. In a part of the n-type silicon carbide single crystal within ≤10 mm from a seed crystal surface, in a 10 mm annular range at a substrate edge, the threading screw dislocation density is <300 -2, in a central range with a diameter of 130 mm, the threading screw dislocation density is <500 -2, and the number of stripe-like stacking faults is <100; and in a part of the n-type silicon carbide single crystal more than 10 mm from the seed crystal surface, in a 40 mm annular range at the substrate edge, the threading screw dislocation density is <100 -2, in a central range with a diameter of 130 mm, the threading screw dislocation density is <300 -2, and the number of stripe-like stacking faults is <5. The n-type silicon carbide single crystal has low threading screw dislocation density and low stacking fault density, which, compared with other n-type silicon carbide single crystals, significantly improves the resistivity uniformity of wafers prepared from the crystal. The n-type silicon carbide single crystal and the n-type silicon carbide substrate prepared therefrom both have high quality and high uniformity.
Owner:SICC CO LTD
Silicon carbide epitaxial structure and preparation method thereof
PendingCN120797204APolycrystalline material growthSemiconductor/solid-state device manufacturingCarbide siliconStacking fault
The invention provides a silicon carbide epitaxial structure and a preparation method thereof, and belongs to the technical field of semiconductors, and the silicon carbide epitaxial structure comprises a silicon carbide substrate, a gradient buffer layer, a growth interruption region, a conventional buffer layer and a drift layer which are sequentially arranged from bottom to top; the gradient buffer layer and the growth interruption region generate lattice strain by means of a doping concentration gradient change to reduce base plane dislocation and stacking fault density. According to the silicon carbide epitaxial structure provided by the invention, a gradual change buffer layer formed by interface modulation doping is arranged on a silicon carbide substrate, and a growth interruption region is formed on the gradual change buffer layer by a growth interruption process; the gradient buffer layer is formed in a doping concentration gradient mode, lattice strain and lattice stress between the substrate and the drift layer are modulated, the base plane dislocation density and stacking fault density of an epitaxial wafer are effectively reduced, and the quality of a silicon carbide epitaxial structure is remarkably improved.
Owner:THE 13TH RES INST OF CHINA ELECTRONICS TECH GRP CORP
A method for preparing a low surface defect epitaxial wafer on a high COP silicon single crystal substrate
This invention relates to a method for preparing low-surface-defect epitaxial wafers on high-COP silicon single-crystal substrates, comprising the following steps: S1, substrate preparation: selecting a high-COP silicon single-crystal substrate; S2, single-sided polishing: polishing the high-COP silicon single-crystal substrate using conventional single-sided polishing equipment to remove the mechanical damage layer on the substrate surface and obtain a preliminarily planarized surface; S3, improved polishing and cleaning process; S4, epitaxial growth of qualified substrate: performing epitaxial growth on the qualified substrate to prepare a low-surface-defect epitaxial wafer. This invention improves the polishing and cleaning processes, thoroughly removing residues within COP voids and suppressing the generation of epitaxial stacking faults, thereby achieving the preparation of high-quality, low-surface-defect epitaxial wafers.
Owner:QL ELECTRONICS (QUZHOU) CO LTD
Method for detecting stacking fault defect of heavily doped silicon wafer
PendingCN121830710APreparing sample for investigationOptically investigating flaws/contaminationStacking faultPhysical chemistry
The invention provides a method for detecting stacking fault defects of heavily doped silicon wafers, which belongs to the technical field of silicon wafer detection, and comprises the following steps of: cleaning dirt and impurities on the surfaces of the silicon wafers in advance to remove interference factors on the surfaces of the silicon wafers, and then carrying out chemical corrosion to gradually expose the stacking fault defects of the silicon wafers. The method comprises the following steps of: coating CuSO4. 5H2O, carrying out heat treatment to carry out copper decoration to enhance the contrast ratio of the defect and a substrate, and finally carrying out preferred corrosion to expose the enhanced defect, so that the macroscopic detection of the stacking fault defect can be carried out in a darkroom, the detection cost is low, the result is accurate, and the detection efficiency is improved.
Owner:FERROTEC (NINGXIA) SEMICON TECH CO LTD
Silicon carbide crystal growth device
PendingCN122082104APolycrystalline material growthFrom condensed vaporsCarbide siliconStacking fault
This invention discloses a silicon carbide crystal growth apparatus, comprising: a crucible, a seed crystal holder, silicon carbide powder, a filter plate, and a crucible lid. The crucible has a mouth; the seed crystal holder is disposed inside the crucible, with a seed crystal disposed on the side of the seed crystal holder facing away from the mouth; the silicon carbide powder is disposed inside the crucible and located below the seed crystal, with a powder evaporation zone formed on the side of the silicon carbide powder facing the seed crystal, the diameter ratio of the powder evaporation zone to the seed crystal being D, wherein 1.4 ≤ D ≤ 1.6; the filter plate is disposed inside the crucible and located between the silicon carbide powder and the seed crystal; and the crucible lid is disposed on the mouth of the crucible. This silicon carbide crystal growth apparatus can improve the growth rate of large-size silicon carbide single crystals and control defects such as dislocation density and stacking faults to a low level, thereby meeting the demand for large-size and high-quality silicon carbide single crystals in high-end applications.
Owner:JIANG SU JI XIN XIAN JIN CAI LIAO YOU XIAN GONG SI
A phase field model of complex phase structure transformation based on dislocation theory
ActiveCN114626214BDesign optimisation/simulationSpecial data processing applicationsFree energiesStacking fault
The application is a phase field model of complex phase structure transformation based on the theory of stacking fault, comprising the following steps: establishing a sublattice free energy model of complex phase structure according to the thermodynamic parameters of the alloy, and thermodynamically describing the alloy system; establishing a stress-strain model of phase transformation according to the stacking fault theory and the phase structure transformation in the alloy, and solving the elastic strain energy of the alloy system; establishing a phase field evolution equation related to the composition and order parameter; setting appropriate initial parameters, solving the phase field equation to obtain the evolution results of the composition field and the order parameter field of the alloy with time and space, and drawing visual images; and analyzing the microstructure evolution diagram of each precipitated phase of the alloy with time. The application provides a phase field model of complex phase structure transformation based on the theory of stacking fault, and the method can predict the process of phase transformation or decomposition of the alloy strengthening phase at high temperature for a long time.
Owner:NANJING UNIV OF SCI & TECH
Low-fault-energy high-entropy alloy and preparation method thereof
PendingCN121988751AHigh Al+Ti contentImprove plasticityAdditive manufacturing apparatusHigh entropy alloysSurface oxidation
The invention discloses a preparation method of a low-fault-energy high-entropy alloy, which comprises the following steps: (1) weighing spherical CoCrNiAl alloy, Co powder, Cr powder, Ni powder and Ti powder according to a stoichiometric equation AlaTibNicCodCre, (2) putting the weighed powder into a ball milling tank for ball milling, uniformly mixing the powder, and then drying, sieving and drying for storage; (3) 304L stainless steel is selected as a base material, and a sand mill is used for polishing the surface of the base material to remove surface oxide skin until a bright surface is exposed; and (4) a laser directional energy deposition method is adopted, the dried powder is placed in a powder feeding tank in a laser system, high-purity Ar gas is used for feeding the powder to a round spot laser head for melting and stacking, and layer-by-layer continuous deposition is conducted. The generation and expansion of cracks in laser additive manufacturing can be inhibited by reducing the stacking fault of a high-entropy alloy system, a large number of coherent L12 phases can be separated out in situ, and the excellent mechanical property is achieved at the normal temperature.
Owner:GUIZHOU UNIV +2
An apparatus and method for reducing the density of threading dislocation defects in silicon carbide crystals
PendingCN122235835APolycrystalline material growthFrom condensed vaporsCarbide siliconThreading dislocations
This application provides an apparatus and method for reducing the density of through-type dislocation defects in silicon carbide crystals. The apparatus includes an insulation component formed by an upper insulation layer, a first outer insulation layer, and a lower insulation layer. The insulation component is provided with gas exchange channels. By placing a crucible containing a silicon carbide seed crystal and silicon carbide raw material into the insulation component and placing them together into a single crystal growth furnace, silicon carbide crystal is grown according to the parameters set for each growth stage to obtain an N-type silicon carbide crystal. When in the isothermal section, N2 is introduced into the single crystal growth furnace in a cycle of n periods according to a first flow rate state and a second flow rate state. Nitrogen is intentionally doped into the silicon carbide crystal during the growth process through the gas exchange channels to increase the conversion probability and ejection probability of through-type dislocations to basal plane dislocations and stacking faults in the N-type silicon carbide crystal. This solves the problem of high dislocation density in SiC single crystals grown by the current PVT method.
Owner:GUANGZHOU SUMMIT CRYSTAL SEMICON CO LTD
Method of manufacturing semiconductor device and semiconductor device
To prevent a lamination defect in an SiC semiconductor device from expanding during current application.SOLUTION: A method of manufacturing a semiconductor device 10 comprises irradiating the semiconductor device 10 with helium ions to form a point defect in a buffer layer 14, where the semiconductor device comprises a substrate 12 made of silicon carbide, the buffer layer 14 of a first conductivity type on a first surface 12a of the substrate 12, and a drift layer 16 of the first conductivity type which is on the buffer layer 14 and has lower impurity concentration than the buffer layer 14. The maximum density of the point defect formed in the buffer layer 14 by the irradiation with the helium ions is 2×1016 / cm3 or larger, and the density of a point defect formed in the drift layer 16 by the irradiation with the helium ions is 2×1017 / cm3 or smaller.SELECTED DRAWING: Figure 2
Owner:SHI ATEX CO LTD
Method for determining the silicon and carbon faces of 3c-sic single crystal wafers
ActiveCN121207971BPreparing sample for investigationMaterial analysis by optical meansWaferingStacking fault
The application provides a method for determining the silicon face and carbon face of a 3C-SiC single crystal wafer, comprising the following steps: (1) immersing the 3C-SiC single crystal wafer into molten alkali for etching treatment; (2) taking out the etched 3C-SiC single crystal wafer and observing the surface morphology; if the surface only presents stacking fault characteristics, it is determined that the face is the () C face; if the surface simultaneously presents stacking fault and dislocation etching pit characteristics, it is determined that the face is the (111) Si face. The application first discovers and utilizes the inherent difference between the (111) Si face and the () C face of the 3C-SiC single crystal in the molten alkali etching morphology: the (111) Si face simultaneously presents stacking fault and dislocation etching pit, while the () C face only presents stacking fault. By observing the significant morphology contrast, the rapid and accurate discrimination of the two crystal faces can be realized.
Owner:INSTITUTE OF PHYSICS CHINESE ACADEMY OF SCIENCES
Method for pre-identification of stacking faults in heavily doped ph products
ActiveCN119715588BFinal product manufacturePreparing sample for investigationChemical physicsStacking fault
The present application relates to a method for pre-identifying the stacking fault of heavily doped Ph products, belonging to the technical field of semiconductor epitaxial detection, comprising the following operation steps: first step: preparing 4 groups of polished wafer samples, 2 groups of normal and abnormal batches, for participating in the experiment. Second step: selecting 1 sample from each of groups A, C and D for the first thermal oxidation and etching test. Third step: selecting another 1 sample from each of groups B, C and D for the second thermal oxidation and etching test. Fourth step: selecting 2 groups of samples from the normal and abnormal samples, and then using different thermal oxidation conditions and etching tests. Fifth step: microscope examination. Sixth step: pre-identifying the silicon wafer with stacking fault. The present application pre-identifies the phenomenon of full-surface stacking fault of silicon wafer after epitaxial processing in some positions of heavily doped Ph products caused by differences in thermal history. The present application avoids the situation of product waste caused by the need to identify abnormalities through epitaxial processing.
Owner:杭州中欣晶圆半导体股份有限公司
An ultrahigh-strength pure metal and a method for producing the same
ActiveCN119973103BTransportation and packagingMetal-working apparatusGrain Boundary SlidingStacking fault
The application provides an ultrahigh-strength pure metal and a preparation method thereof, and relates to the technical field of high-performance metal materials. The preparation method of the ultrahigh-strength pure metal provided by the application takes a nano pure metal powder as an initial raw material, and then forms a small block with a size of dozens of microns through high-pressure welding to form a dense pure metal without adding any alloy element. The pressure is a very pure regulation and control means, which can realize extreme strengthening of the nano metal without introducing any impurities. The pressure can effectively inhibit the grain boundary sliding of the nanocrystalline, can compact the nano metal powder to a certain extent, and can avoid grain coarsening, so that the deformation mechanism of the metal itself is activated, including various crystal defects such as full dislocation, partial dislocation, twinning, stacking fault and the like. The multiple types of defects interact with each other, generate strain fields and superimpose on each other, hinder the movement of dislocations, and then bring about strong work hardening and extreme strengthening, so that the pure metal finally realizes ultrahigh strength.
Owner:HARBIN INSTITUTE OF TECHNOLOGY (SHENZHEN) (INSTITUTE OF SCIENCE AND TECHNOLOGY INNOVATION HARBIN INSTITUTE OF TECHNOLOGY SHENZHEN) +1
Method for eliminating small stacking faults of silicon carbide based on high temperature oxidation
The application belongs to the technical field of third-generation semiconductor material defect control. A method for eliminating small-scale stacking faults of silicon carbide based on high-temperature oxidation is proposed. The silicon carbide substrate is scanned and characterized by photoluminescence, and the target small-scale stacking fault is accurately identified and positioned. Then, the substrate is cleaned to remove surface impurities, and high-temperature oxidation treatment is carried out in a dry oxygen atmosphere, and an oxidation layer is controlled to grow. The mismatch of the thermal expansion coefficient between the oxidation layer and the substrate and the reaction molar volume expansion are used to construct a composite interface stress field at the interface, drive the directional reconstruction of the atomic arrangement of the target stacking fault, and convert it into the standard sequence of the matrix. Finally, nitric oxide assisted annealing is carried out, and the nitrogen passivation effect is used to solidify the lattice configuration after reconstruction. The application has the advantages of simple process, strong compatibility, efficient and stable elimination of small-scale stacking faults, and significantly improved crystal quality of silicon carbide substrate, which provides a guarantee for the preparation of high-reliability power devices.
Owner:SHANDONG UNIV
SiC@BN core-shell nanowire periodic array reinforced Si3N4 high-temperature wave-absorbing ceramic coating and preparation method thereof
The application discloses a SiC@BN core-shell nanowire periodic array reinforced Si3N4 high-temperature wave-absorbing ceramic coating, which is composed of SiC nanowires, a BN shell layer and a Si3N4 ceramic matrix. The SiC nanowires and the BN shell layer are obtained through a chemical vapor infiltration process, and form a core-shell structure to obtain SiC@BN core-shell nanowires, which can avoid oxidation of the SiC nanowires and improve the dielectric constant of the SiC nanowires. The SiC@BN core-shell nanowires are arranged in a three-dimensional periodic array. The Si3N4 ceramic matrix is prepared through the chemical vapor infiltration process, and the Si3N4 ceramic matrix is uniformly filled in the pores between the SiC@BN core-shell nanowires. Through macro-micro multi-scale structure design, lattice distortion, stacking faults and interface defects are introduced in the micro scale to promote the absorption and attenuation loss of the incident electromagnetic wave, and the surface electric field coupling effect and multiple scattering loss mechanism are introduced in the macro scale to realize the widening of the effective absorption band and the synergistic improvement of the electromagnetic wave absorption characteristics.
Owner:NORTHWESTERN POLYTECHNICAL UNIV
Core / shell-type semiconductor nanoparticle and method for manufacturing same
These core / shell-type semiconductor nanoparticles each comprise: a core containing at least indium (In) and phosphorus (P); and a shell containing zinc (Zn) and sulfur (S) and / or selenium (Se). The core / shell-type semiconductor nanoparticles are characterized by: having stacking faults; containing a halogen; having a molar ratio of halogen to indium (In) of more than 15 but no more than 500 on an atomic basis; and having an average circularity of 0.820-1.000, which is found in a STEM image obtained by observation with a scanning transmission electron microscope. The present invention provides: core / shell-type semiconductor nanoparticles each comprising a core containing indium (In) and phosphorus (P) and a shell containing zinc (Zn) and sulfur (S) and / or selenium (Se); and a method for producing the same. With shells formed with high uniformity and having highly consistent shapes, the core / shell-type semiconductor nanoparticles exhibit a high luminous efficiency and a narrow FWHM even if stacking faults are present.
Owner:SHOEI CHEM IND CO LTD
SiC EPITAXIAL WAFER, METHOD FOR EVALUATING SiC EPITAXIAL WAFER, AND METHOD FOR MANUFACTURING SiC DEVICE
PCT designated stageWO2025225726A1Polycrystalline material growthFrom chemically reactive gasesCrystallographyWafering
An SiC epitaxial wafer according to the present embodiment comprises: an SiC substrate which has a micropipe; and an SiC epitaxial layer which is formed on the SiC substrate. The SiC epitaxial layer has a density of stacking faults caused by the micropipe of the SiC substrate of less than 0.067 per cm2.
Owner:RESONAC CORP
Seed substrate for epitaxial growth use and method for manufacturing same, and semiconductor substrate and method for manufacturing same
ActiveUS12618172B2Polycrystalline material growthAfter-treatment detailsStacking faultSolid substrate
A seed substrate for epitaxial growth has a support substrate, a planarizing layer of 0.5 to 3 μm provided on the top surface of the support substrate, and a seed crystal layer provided on the top surface of the planarizing layer. The support substrate includes a core of group III nitride polycrystalline ceramics and a 0.05 to 1.5 μm encapsulating layer that encapsulates the core. The seed crystal layer is provided by thin-film transfer of 0.1 to 1.5 μm of the surface layer of Si<111> single crystal with oxidation-induced stacking faults (OSF) of 10 defects / cm2 or less. High-quality, inexpensive seed substrates with few crystal defects for epitaxial growth of epitaxial substrates and solid substrates of group III nitrides such as AlN, AlxGa1-xN (0<X<1) and GaN are obtained.
Owner:SHIN ETSU CHEMICAL CO LTD +1
Calibration bodies and methods for their manufacture
The invention relates to the fields of materials science and measurement technology and concerns calibration objects, such as those that can be used in analytical spectroscopy. The object of the present invention is therefore to produce electrically conductive calibration blocks, in particular for the calibration of hydrogen measuring instruments. The calibration blocks can be provided in large quantities, simply and cost-effectively. The problem is solved by calibration bodies, in particular for the calibration of hydrogen measuring instruments, consisting at least of an electrically conductive, porous sintered body with a substantially homogeneous distribution of pores and / or defects, such as dislocations, stacking faults and / or twins, in the sintered body, in which an adjustable hydrogen concentration is present depending on the number and size of the pores and / or defects in the sintered body, wherein the hydrogen is physically and / or chemically bound in and / or on the surface of the pores and / or defects, and wherein the set hydrogen concentration in the calibration body decreases in a specified amount over time.
Owner:TECH UNIV BERGAKADEMIE FREIBERG KORPERSCHAFT DES OFFENTLICHEN RECHTS
Silicon carbide semiconductor substrate, silicon carbide semiconductor device, method for inspecting a silicon carbide semiconductor substrate, and method for manufacturing a silicon carbide semiconductor device.
PendingJP2026068825ASemiconductor/solid-state device testing/measurementDevice materialStacking fault
This invention provides a silicon carbide semiconductor substrate, a silicon carbide semiconductor device, a silicon carbide semiconductor substrate inspection method, and a silicon carbide semiconductor device manufacturing method that can improve product yield by enabling the detection of crystal defects that do not affect device operation. [Solution] The silicon carbide semiconductor substrate inspection method is a method for inspecting a silicon carbide semiconductor substrate having an epitaxial layer. By differential interference contrast observation of the silicon carbide semiconductor substrate, it is determined whether the crystal defects of the silicon carbide semiconductor substrate are defects that have grown obliquely within the epitaxial layer. From the photoluminescence image of the silicon carbide semiconductor substrate, it is determined whether the defects are stacking faults that have grown trapezoidally within the epitaxial layer. By transmission polarization observation of the silicon carbide semiconductor substrate, it is determined whether the stacking faults are associated with through-helical dislocations.
Owner:FUJI ELECTRIC CO LTD +1
Monocrystalline silicon wafer layer fault ring lossless identification method
PendingCN120895490AWeather/light/corrosion resistanceSemiconductor/solid-state device testing/measurementStacking faultPhysical chemistry
The invention relates to a monocrystalline silicon wafer layer fault ring lossless identification method, which comprises the following operation steps: step 1, preparing silicon wafer samples, and connecting a group of sample engraved numbers to form adjacent wafers; 2, carrying out laser defect detection on the silicon wafer sample, and carrying out SP7 test by adopting a Ketian particle tester; 3, after laser defect detection, analyzing a particle detection result, and judging the occurrence degree and position of the fault defect in the crystal bar body; and 3, judging whether the silicon wafer sample has the fault ring defect or not. According to the method, the stacking fault of the monocrystalline silicon wafer product is identified in advance, the method has the advantages of being convenient to operate and good in running stability, heat treatment and corrosion inspection are avoided only by adopting SP7 testing, the processing time is saved, the detection procedure is saved, and the condition of product waste is avoided; the silicon wafer of the whole crystal bar can be subjected to lossless full inspection under necessary conditions, and the method is suitable for comprehensive monitoring of the quality of the crystal bar and the quality of a product during large-scale production; the method also comprises a verification step, so that the whole method is more reliable and accurate.
Owner:ZHEJIANG QL ELECTRONICS
A multi-modal detection method for small-scale stacking fault defects in silicon carbide substrates
The present application belongs to the technical field of silicon carbide defect detection, and particularly relates to a multi-modal detection method for small-scale stacking fault defects in a silicon carbide substrate, comprising the following steps: performing photoluminescence imaging on a silicon carbide substrate to be detected to obtain a candidate region of small-scale stacking fault defects; performing two-dimensional mapping scanning of micro-photoluminescence spectrum on the candidate region to obtain a spectral intensity mapping image in the candidate region; constructing a multi-modal matching model, and performing spatial registration on the spectral intensity mapping image and the photoluminescence imaging to confirm a single small-scale stacking fault defect by calculating a weighted pixel overlap rate; and performing two-dimensional mapping scanning of micro-photoluminescence spectrum on the single small-scale stacking fault defect to determine the defect morphology and size. The method has the advantages of high sensitivity and high resolution, is suitable for rapid detection and online quality control of defects in a large-size silicon carbide substrate, and has a good industrial application prospect.
Owner:SHANDONG UNIV
High-temperature alloy part reinforced by prefabricated superlattice layer staggering in ordered phase as well as preparation method and application of high-temperature alloy part
The invention belongs to the technical field of high-temperature metal material processing, and particularly discloses a high-temperature alloy workpiece reinforced by prefabricated superlattice stacking in an ordered phase and a preparation method and application thereof.The preparation method comprises the steps that 1, according to the design size of the high-temperature alloy workpiece, size information of a blank A is determined through finite element simulation iterative calculation; 2) preparing a blank A; (3) the blank A is subjected to heat treatment; (4) the blank A is subjected to surface machining, and a blank B is obtained; (5) the blank B is subjected to pressure maintaining forging in an isothermal forging press, so that the blank B is subjected to pre-creep deformation to form a gamma'phase internal superlattice layer fault, and a blank C is obtained; and (6) the blank C is subjected to annealing treatment and then machined to the designed size, and the target high-temperature alloy workpiece is obtained. By means of the technology, the discontinuous superlattice layer fault in the ordered strengthening phase of the high-temperature alloy can be obtained, and the structure formed by the structure has higher tensile strength and creep / endurance strength and can meet the strict requirements of aerospace for mechanical properties.
Owner:SINO EURO MATERIALS TECH OF XIAN CO LTD
Growth method of 4H silicon carbide crystal and related product
PendingCN121295356APolycrystalline material growthUnder a protective fluidCarbide siliconStacking fault
The invention discloses a growth method of a 4H silicon carbide crystal and a related product, which can be applied to the technical field of silicon carbide single crystal growth, and the method comprises the following steps: firstly putting a first seed crystal and a first silicon carbide raw material into a growth furnace; the first seed crystal is a 4H-SiC single crystal. Then nitrogen with a first preset flow is introduced into the growth furnace, and heating is carried out at the same time; after the temperature rise is finished, nitrogen with a second preset flow and argon with a third preset flow are introduced into the growth furnace, and growth of the 4H silicon carbide crystals is started at the same time. Finally, in the growth process of the 4H silicon carbide crystals, the flow of the nitrogen is kept constant, and the flow of the argon is controlled to linearly increase progressively according to the first preset increase trend until the 4H silicon carbide crystals grow completely. Thus, the gas proportion of the nitrogen and the argon is dynamically regulated and controlled in the growth process of the 4H silicon carbide crystal, so that the structural defects such as stacking fault caused by too high nitrogen concentration are avoided, and the quality of the silicon carbide crystal is improved while low resistivity is considered.
Owner:SHENZHEN HEAVY INVESTMENT TIANKE SEMICON CO LTD +2
A NiAl alloy full-lamellar microstructure and its preparation method
This invention belongs to the field of non-equilibrium solidification technology, specifically relating to a NiAl alloy full-lamellar microstructure and its preparation method. The method includes the following steps: (1) preparing a NiAl-based alloy ingot; (2) constructing the NiAl-based alloy ingot into a high-pressure assembly; (3) placing the high-pressure assembly in a heating chamber and performing high-pressure solidification treatment using a press to obtain a NiAl alloy full-lamellar microstructure containing high-density twins and stacking faults; the pressure of the high-pressure solidification treatment is 6-8 GPa, and the temperature of the high-pressure solidification treatment is 1500-1650℃. This invention achieves the construction of a full-lamellar microstructure and the introduction of high-density crystal defects simultaneously in a one-step process through high-pressure solidification. The resulting lamellar structure is rich in nanotwins and stacking faults at the interior and interface. These substructures can effectively hinder dislocation movement, passivate crack propagation, and significantly improve the toughness and deformation capacity of NiAl alloy while enhancing the material strength.
Owner:QUZHOU UNIV
Method for manufacturing silicon carbide substrate, and apparatus for manufacturing silicon carbide substrate
PCT designated stageWO2026022963A1Semiconductor/solid-state device manufacturingPhoto irradiationStacking fault
Provided is a method for manufacturing a silicon carbide substrate 100 that has a substrate layer 101 and an epitaxial layer 102, the method comprising: a detection step for detecting a basal plane dislocation (BPD) present in the epitaxial layer 102 by irradiating the silicon carbide substrate 100 with inspection light L1; an expansion step for irradiating the area in which the basal plane dislocation (BPD) detected in the detection step is present with expansion light L3 for expanding a Shockley type stacking fault (SSF) from the basal plane dislocation (BPD); and a contraction step for irradiating the Shockley type stacking fault (SSF) expanded from the basal plane dislocation (BPD) in the expansion step with contraction light L4 for contracting the Shockley type stacking fault (SSF). In cases where a plurality of basal plane dislocations (BPD) are detected in the detection step, in the expansion step, after irradiating one region in which a basal plane dislocation (BPD) is present with expansion light, another region in which a basal plane dislocation (BPD) is present is irradiated with expansion light L3 concurrently with the contraction step, and this operation is repeated for all regions in which a basal plane dislocation (BPD) is present.
Owner:ITES CO LTD
Method for reducing stacking faults in silicon carbide, and structure created by means of said method
PendingEP4415024A4Polycrystalline material growthSemiconductor/solid-state device manufacturingCarbide siliconMetallurgy
An object of the present invention is to provide a novel technique for reducing stacking faults SF in silicon carbide. Another object of the present invention is to provide a novel technique capable of reducing the stacking faults SF under a small number of growth conditions. The present invention is a method for reducing stacking faults in silicon carbide including a growth step S10 of growing an epitaxial layer 20 on a bulk layer 10 of silicon carbide having stacking faults SF under a SiC-C equilibrium vapor pressure environment.
Owner:KWANSEI GAKUIN EDUCTIONAL FOUND +1