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59 results about "Stacking fault" patented technology
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In crystallography, a stacking fault is a type of defect which characterizes the disordering of crystallographic planes. It is thus considered a planar defect. The most common example of stacking faults is found in close-packed crystal structures. Face-centered cubic (fcc) structures differ from hexagonal close packed (hcp) structures only in stacking order: both structures have close-packed atomic planes with sixfold symmetry — the atoms form equilateral triangles. When stacking one of these layers on top of another, the atoms are not directly on top of one another. The first two layers are identical for hcp and fcc, and labelled AB. If the third layer is placed so that its atoms are directly above those of the first layer, the stacking will be ABA — this is the hcp structure, and it continues ABABABAB. However, there is another possible location for the third layer, such that its atoms are not above the first layer. Instead, it is the atoms in the fourth layer that are directly above the first layer. This produces the stacking ABCABCABC, which is actually along the [111] direction of a cubic crystal structure. In this context, a stacking fault is a local deviation from one of the close-packed stacking sequences to the other one. Usually, only one- two- or three-layer interruptions in the stacking sequence are referred to as stacking faults. An example for the fcc structure is the sequence ABCABABCAB.
Multi-mode detection method for small and medium-sized stacking fault defects of silicon carbide substrate
The invention belongs to the technical field of silicon carbide defect detection, and particularly relates to a multi-mode detection method for small and medium-sized stacking fault defects of a silicon carbide substrate, which comprises the following steps of: performing photoluminescence imaging on a silicon carbide substrate to be detected to obtain a candidate area of the small-sized stacking fault defects; performing microscopic photoluminescence spectrum two-dimensional mapping scanning on the candidate area to obtain a spectrum intensity mapping image in the candidate area; constructing a multi-modal matching model, performing spatial registration on a spectral intensity mapping image and a photoluminescence image, and determining a single small stacking fault defect by calculating a weighted pixel overlapping rate; microscopic photoluminescence spectrum two-dimensional mapping scanning is carried out on a single small stacking fault defect, and the morphology and size of the defect are determined. The method has the advantages of high sensitivity and high resolution, is suitable for rapid detection and online quality control of defects of the large-size silicon carbide substrate, and has a good industrial application prospect.
Owner:SHANDONG UNIV
LTO film thickness uniformity optimization method through APCVD method
The invention discloses an LTO film thickness uniformity optimization method through an APCVD method, and particularly relates to the technical field of semiconductor manufacturing, and the method comprises the following steps: S1, prefabricating a silicon wafer; s2, selecting a tungsten filament ring; s3, installing a tungsten filament ring; s4, depositing an LTO thin film; s5, measuring the thickness of the LTO thin film of the silicon wafer; and S6, confirming the service life of the tungsten filament ring. According to the LTO film thickness uniformity optimization method through the APCVD method, the silicon wafer is chamfered, stress concentration and dislocation are reduced, wafer edge breakage and inward movement of thermal stress defects are effectively prevented, a more stable substrate is provided for follow-up film deposition, a tungsten filament ring of a specific specification is selected and correctly installed, and the uniformity of the thickness of the LTO film is improved. The diffusion and transmission conditions of gas in the APCVD process can be improved, the problems of stacking faults, crystal points, self-doping and the like after epitaxy caused by non-uniform films are reduced, and the consistency and reliability of device performance are improved.
Owner:SHANGHAI SEMICON WAFER TECH CO LTD
Nickel-based superalloy with low cracking sensitivity for additive manufacturing
PCT designated stage expiredWO2025146082A1Additive manufacturing apparatusIncreasing energy efficiencyHigh densityStacking fault
Aimed at the cracking problem of nickel-based superalloys for additive manufacturing, the present invention provides a nickel-based superalloy with low cracking sensitivity for additive manufacturing. The microstructure is adjusted and controlled by means of rare-earth microalloying, thereby facilitating the formation of high-density stacking faults, a rare-earth-containing nano second phase, and refined crystal grains and a subcrystal structure in the alloy matrix, increasing the number of isometric crystals, reducing the columnar crystal proportion and the length-to-diameter ratio thereof, decreasing the cracking sensitivity, and greatly improving the strength and plasticity. The method solves the problem of cracking in an additive manufacturing, storage and heat treatment of a nickel-based superalloy, and can be used to prepare a high-performance and crack-free nickel-based superalloy. The present invention has a rational composition design and a simple preparation process, results in a product having excellent performance, and facilitates large-scale industrial production and practical application.
Owner:CENT SOUTH UNIV
Silicon carbide epitaxial substrate and method of manufacturing silicon carbide semiconductor device
PendingUS20250218771A1Polycrystalline material growthSemiconductor/solid-state device manufacturingCrystallographyCarbide silicon
A silicon carbide epitaxial substrate has a silicon carbide substrate, a silicon carbide epitaxial layer, an internal line-shaped stacking fault, and a carrot defect. The silicon carbide epitaxial layer is located on the silicon carbide substrate and has a main surface. The internal line-shaped stacking fault is located inside the silicon carbide epitaxial layer and is separated from the main surface. The carrot defect is exposed at the main surface. A value obtained by dividing a length of the internal line-shaped stacking fault by a width of the internal line-shaped stacking fault is 0.5 or less. A value obtained by dividing a length of the carrot defect by a width of the carrot defect is more than 0.5. The number of the internal line-shaped stacking faults is less than the number of the carrot defects.
Owner:MITSUMI ELECTRIC CO LTD
Method for improving imaging definition of stacking fault of silicon carbide substrate
PendingCN120522192ASemiconductor/solid-state device manufacturingOptically investigating flaws/contaminationCarbide siliconHydrofluoric acid
The invention discloses a method for improving the stacking fault imaging definition of silicon carbide substrates, which comprises the following steps of: firstly, screening out the silicon carbide substrates with unclear stacking fault imaging through stacking fault imaging detection, cleaning the screened silicon carbide substrates, and adsorbing the silicon carbide substrates on an adsorption pad of a polishing head in a polishing chamber; maintaining the polishing chamber at the temperature and pressure required by polishing, continuously introducing a silicon oxide polishing solution into the polishing pad, then controlling the polishing head and the polishing disc to rotate for 2 hours so as to enable the polishing pad to polish the silicon carbide substrate, taking out the polished silicon carbide substrate, and cleaning the silicon carbide substrate by using a hydrofluoric acid solution, therefore, the silicon carbide substrate stacking fault imaging definition is improved, stacking faults can be clearly distinguished in stacking fault imaging detection, the number and area of the stacking faults on the silicon carbide substrate can be accurately judged, and then the qualified silicon carbide substrate which can be used for epitaxial growth can be accurately screened out.
Owner:DONGGUAN TIANYU SEMICON TECH
Method for eliminating silicon carbide small stacking fault based on high-temperature oxidation
The invention belongs to the technical field of third-generation semiconductor material defect control. According to the method for eliminating the silicon carbide small stacking fault based on high-temperature oxidation, a silicon carbide substrate is scanned and represented in a photoluminescence mode, and the target small stacking fault is accurately recognized and positioned; cleaning the substrate to remove surface impurities, performing high-temperature oxidation treatment in a dry oxygen atmosphere, and growing an oxide layer under control; constructing a composite interface stress field at an interface by utilizing thermal expansion coefficient mismatch and reaction molar volume expansion between the oxide layer and the substrate, and driving target stacking fault atom arrangement to generate directional reconstruction, so that the target stacking fault atom arrangement is converted into a matrix standard sequence; and finally, nitric oxide auxiliary annealing is carried out, and the reconstructed lattice configuration is solidified by utilizing a nitrogen passivation effect. The method is simple in process and high in compatibility, small stacking fault can be efficiently and stably eliminated, the silicon carbide substrate crystal quality is remarkably improved, and a guarantee is provided for preparation of a high-reliability power device.
Owner:SHANDONG UNIV
Defect classification equipment for silicon carbide substrate using single incident light-based photoluminescence and defect classification method using the same
Stack fault inspection apparatus and method are disclosed. The apparatus includes a sample stage fixing the silicon carbide substrate and allow the incident light to scan the substrate surface; an incident light source configured to irradiate a vertical illumination light of a wavelength corresponding to an energy greater than a band gap energy of the substrate to at least a portion of a surface of the substrate in a direction substantially perpendicular to the surface of the substrate; a photomultiplier tube (PMT) configured to obtain a photoluminescence mapping image having a wavelength corresponding to the band gap energy of the substrate from the surface of the substrate; and a controller configured to process the mapping image and identify stacking faults.
Owner:HORIBA STEC KOREA LTD
Lattice interlocking type lithium-rich manganese-based positive electrode material as well as preparation method and application thereof
The invention provides a lattice interlocking type lithium-rich manganese-based positive electrode material as well as a preparation method and application thereof, and relates to the technical field of preparation of battery positive electrode materials. A certain amount of sodium ions are introduced in the synthesis process, formation of highly stacked faults is induced in a high-temperature box, then surface defect growth and fusion are induced, a lattice interlocking twin crystal structure is formed, only one-time high-temperature sintering and one-time washing processes are needed, a TM migration energy barrier and an oxygen diffusion energy barrier are improved, phase change diffusion is interrupted, and the preparation method is simple and convenient to operate. The problem of structural circulation instability of the lithium-rich material is solved, the stress strain of the layered material in the charging and discharging process is reduced, the lattice stress is greatly eliminated, the lattice stress in the charging and discharging process is reduced, the expansion and crystal face slippage are inhibited, and the interface stability is improved.
Owner:CHINA AUTOMOTIVE BATTERY RES INST CO LTD
Method for determining silicon surface and carbon surface of 3C-SiC single crystal wafer
ActiveCN121207971APreparing sample for investigationMaterial analysis by optical meansWaferingStacking fault
The invention provides a method for determining a silicon surface and a carbon surface of a 3C-SiC single crystal wafer, which comprises the following steps of: (1) immersing the 3C-SiC single crystal wafer into molten alkali for corrosion treatment; (2) taking out the corroded 3C-SiC single crystal wafer and observing the surface appearance of the 3C-SiC single crystal wafer; if the surface only shows the stacking fault characteristic, judging that the surface is a (C) surface; and if the surface has the characteristics of stacking fault and dislocation corrosion pits at the same time, determining that the surface is a (111) Si surface. According to the invention, the inherent difference of molten alkali on the corrosion morphology of the (111) Si surface and the (C) surface of the 3C-SiC single crystal is found and utilized for the first time: the (111) Si surface can present stacking fault and dislocation corrosion pits at the same time, and only the (C) surface has stacking fault. By observing the obvious morphology comparison, the two crystal faces can be quickly and accurately distinguished.
Owner:INSTITUTE OF PHYSICS CHINESE ACADEMY OF SCIENCES
One-dimensional zigzag ultrathin Pt-based nanoshell catalyst coated on carbon nanotube and having rich defects and preparation method of one-dimensional zigzag ultrathin Pt-based nanoshell catalyst
The invention relates to the field of carbon-loaded nano-catalysts, in particular to a one-dimensional zigzag ultrathin Pt-based nano-shell catalyst which is coated on a carbon nanotube and has abundant defects and a preparation method of the one-dimensional zigzag ultrathin Pt-based nano-shell catalyst. According to the catalyst, a carbon nanotube film is used as a substrate, magnetron sputtering is carried out at room temperature, then rapid annealing is carried out, and finally a one-dimensional zigzag ultrathin Pt-based nano shell is formed and uniformly coats a carbon nanotube bundle. The ultrathin Pt-based nano shell has abundant surface structures (high-index edge steps) and a large number of crystal defects such as twin crystals and stacking faults, the electronic structure of surface atoms is adjusted, and the adsorption / desorption strength of an intermediate is optimized, so that the catalytic activity is influenced. According to the method, efficient and controllable preparation of the defect type Pt-based nanowire catalyst is achieved, the activity and stability of the catalyst are improved, the method can be suitable for various catalytic reactions related to fuel cells, and the method is expected to be a practical method for large-scale preparation and application of the catalyst.
Owner:INST OF METAL RESEARCH - CHINESE ACAD OF SCI
N-type silicon carbide single crystal, n-type silicon carbide substrate, and semiconductor device
PCT designated stageWO2025227621A1Polycrystalline material growthFrom condensed vaporsSemiconductor materialsWafering
An n-type silicon carbide single crystal, an n-type silicon carbide substrate, and a semiconductor device, belonging to the technical field of semiconductor materials. In a part of the n-type silicon carbide single crystal within ≤10 mm from a seed crystal surface, in a 10 mm annular range at a substrate edge, the threading screw dislocation density is <300 -2, in a central range with a diameter of 130 mm, the threading screw dislocation density is <500 -2, and the number of stripe-like stacking faults is <100; and in a part of the n-type silicon carbide single crystal more than 10 mm from the seed crystal surface, in a 40 mm annular range at the substrate edge, the threading screw dislocation density is <100 -2, in a central range with a diameter of 130 mm, the threading screw dislocation density is <300 -2, and the number of stripe-like stacking faults is <5. The n-type silicon carbide single crystal has low threading screw dislocation density and low stacking fault density, which, compared with other n-type silicon carbide single crystals, significantly improves the resistivity uniformity of wafers prepared from the crystal. The n-type silicon carbide single crystal and the n-type silicon carbide substrate prepared therefrom both have high quality and high uniformity.
Owner:SICC CO LTD
Silicon carbide epitaxial structure and preparation method thereof
PendingCN120797204APolycrystalline material growthSemiconductor/solid-state device manufacturingCarbide siliconStacking fault
The invention provides a silicon carbide epitaxial structure and a preparation method thereof, and belongs to the technical field of semiconductors, and the silicon carbide epitaxial structure comprises a silicon carbide substrate, a gradient buffer layer, a growth interruption region, a conventional buffer layer and a drift layer which are sequentially arranged from bottom to top; the gradient buffer layer and the growth interruption region generate lattice strain by means of a doping concentration gradient change to reduce base plane dislocation and stacking fault density. According to the silicon carbide epitaxial structure provided by the invention, a gradual change buffer layer formed by interface modulation doping is arranged on a silicon carbide substrate, and a growth interruption region is formed on the gradual change buffer layer by a growth interruption process; the gradient buffer layer is formed in a doping concentration gradient mode, lattice strain and lattice stress between the substrate and the drift layer are modulated, the base plane dislocation density and stacking fault density of an epitaxial wafer are effectively reduced, and the quality of a silicon carbide epitaxial structure is remarkably improved.
Owner:THE 13TH RES INST OF CHINA ELECTRONICS TECH GRP CORP
A method for preparing a low surface defect epitaxial wafer on a high COP silicon single crystal substrate
This invention relates to a method for preparing low-surface-defect epitaxial wafers on high-COP silicon single-crystal substrates, comprising the following steps: S1, substrate preparation: selecting a high-COP silicon single-crystal substrate; S2, single-sided polishing: polishing the high-COP silicon single-crystal substrate using conventional single-sided polishing equipment to remove the mechanical damage layer on the substrate surface and obtain a preliminarily planarized surface; S3, improved polishing and cleaning process; S4, epitaxial growth of qualified substrate: performing epitaxial growth on the qualified substrate to prepare a low-surface-defect epitaxial wafer. This invention improves the polishing and cleaning processes, thoroughly removing residues within COP voids and suppressing the generation of epitaxial stacking faults, thereby achieving the preparation of high-quality, low-surface-defect epitaxial wafers.
Owner:QL ELECTRONICS (QUZHOU) CO LTD
A silicon wafer external gettering method
ActiveCN116206950BFinal product manufactureSemiconductor/solid-state device manufacturingStacking faultThin membrane
The present disclosure provides a method for external gettering of silicon wafers, the method comprising: obtaining a first silicon wafer, the first silicon wafer being obtained by performing a first pretreatment operation on an initial silicon wafer; depositing a predetermined material on the back side of the first silicon wafer to form a thin film on the back side of the first silicon wafer; performing a second pretreatment operation on the first silicon wafer with the thin film formed on the back side to obtain a second silicon wafer, wherein the second pretreatment operation includes a heat treatment, the heat treatment being used to induce stacking faults in the first silicon wafer to form gettering centers through film stress; removing the thin film from the second silicon wafer; and polishing the second silicon wafer after the thin film is removed. This method is applied to introduce an external gettering process after the silicon wafer is pretreated, so that the silicon wafer has external gettering capability while achieving high flatness, and after the gettering centers are introduced, the thin film is removed to release stress, thereby reducing warping of the silicon wafer.
Owner:HANGZHOU FULLSEMI SEMICON CO LTD
Intragranular magnetic field construction method for complex atom defect
ActiveCN120690337AQuantum computersMolecular entity identificationElectronic structureSpin magnetic moment
The invention relates to an intragranular magnetic field construction method for complex atom defects, and belongs to the field of quantum information science. Comprising the following steps: constructing initial unit cells and expanding the initial unit cells into super unit cells; carrying out natural isotope substitution in the superunit cells; carrying out stacking fault on the super unit cells and removing corresponding atom introduction defects; based on a first principle, performing structure optimization on the super-unit cell with the introduced defect until the super-unit cell with the optimized structure has a stable configuration, and obtaining the super-unit cell with the optimized structure; performing static electronic structure calculation to obtain magnetization density distribution data of the supercell after structure optimization; performing calculation according to the magnetization density distribution data to obtain spin magnetic moment distribution of the supercell after structure optimization; and according to the spin magnetic moment distribution, calculating the magnetic field induction intensity of any point in the supercell after structure optimization, and carrying out magnetic field construction. According to the method, an intragranular magnetic field is constructed, so that a basis is provided for researching the spin coherence property of a color center material with complex atom defects.
Owner:BEIJING INST OF TECH
Method for detecting stacking fault defect of heavily doped silicon wafer
PendingCN121830710APreparing sample for investigationOptically investigating flaws/contaminationStacking faultPhysical chemistry
The invention provides a method for detecting stacking fault defects of heavily doped silicon wafers, which belongs to the technical field of silicon wafer detection, and comprises the following steps of: cleaning dirt and impurities on the surfaces of the silicon wafers in advance to remove interference factors on the surfaces of the silicon wafers, and then carrying out chemical corrosion to gradually expose the stacking fault defects of the silicon wafers. The method comprises the following steps of: coating CuSO4. 5H2O, carrying out heat treatment to carry out copper decoration to enhance the contrast ratio of the defect and a substrate, and finally carrying out preferred corrosion to expose the enhanced defect, so that the macroscopic detection of the stacking fault defect can be carried out in a darkroom, the detection cost is low, the result is accurate, and the detection efficiency is improved.
Owner:FERROTEC (NINGXIA) SEMICON TECH CO LTD
Silicon carbide crystal growth device
PendingCN122082104APolycrystalline material growthFrom condensed vaporsCarbide siliconStacking fault
This invention discloses a silicon carbide crystal growth apparatus, comprising: a crucible, a seed crystal holder, silicon carbide powder, a filter plate, and a crucible lid. The crucible has a mouth; the seed crystal holder is disposed inside the crucible, with a seed crystal disposed on the side of the seed crystal holder facing away from the mouth; the silicon carbide powder is disposed inside the crucible and located below the seed crystal, with a powder evaporation zone formed on the side of the silicon carbide powder facing the seed crystal, the diameter ratio of the powder evaporation zone to the seed crystal being D, wherein 1.4 ≤ D ≤ 1.6; the filter plate is disposed inside the crucible and located between the silicon carbide powder and the seed crystal; and the crucible lid is disposed on the mouth of the crucible. This silicon carbide crystal growth apparatus can improve the growth rate of large-size silicon carbide single crystals and control defects such as dislocation density and stacking faults to a low level, thereby meeting the demand for large-size and high-quality silicon carbide single crystals in high-end applications.
Owner:JIANG SU JI XIN XIAN JIN CAI LIAO YOU XIAN GONG SI
A phase field model of complex phase structure transformation based on dislocation theory
ActiveCN114626214BDesign optimisation/simulationSpecial data processing applicationsFree energiesStacking fault
The application is a phase field model of complex phase structure transformation based on the theory of stacking fault, comprising the following steps: establishing a sublattice free energy model of complex phase structure according to the thermodynamic parameters of the alloy, and thermodynamically describing the alloy system; establishing a stress-strain model of phase transformation according to the stacking fault theory and the phase structure transformation in the alloy, and solving the elastic strain energy of the alloy system; establishing a phase field evolution equation related to the composition and order parameter; setting appropriate initial parameters, solving the phase field equation to obtain the evolution results of the composition field and the order parameter field of the alloy with time and space, and drawing visual images; and analyzing the microstructure evolution diagram of each precipitated phase of the alloy with time. The application provides a phase field model of complex phase structure transformation based on the theory of stacking fault, and the method can predict the process of phase transformation or decomposition of the alloy strengthening phase at high temperature for a long time.
Owner:NANJING UNIV OF SCI & TECH
Method for depositing thick-layer silicon epitaxial wafer on ultra-thin substrate for semiconductor power device
The present invention discloses a method for depositing a thick layer of silicon epitaxial wafer on an ultra-thin substrate for semiconductor power devices. By comprehensively designing key process parameters different from traditional growth temperature, heating power, heating-up time, cooling-down time, etc., the induced defects of epitaxy such as stacking faults, dislocations, slip lines, orange peel, and back and edge crystal point adsorption easily generated by traditional processes are overcome. The traditional process is simplified, the process is simple, the industrial continuous production cost is reduced, and the batch deposition of thick layer silicon epitaxial wafers on 6-inch and 8-inch ultra-thin silicon substrates is realized. The product parameters have good uniformity, and the five-point thickness non-uniformity is <0.8%, meeting the market demand in the industry for thick layer silicon epitaxial wafers on 6-inch and 8-inch ultra-thin substrates.
Owner:CHINA ELECTRONICS TECH GRP NO 46 RES INST
Low-fault-energy high-entropy alloy and preparation method thereof
PendingCN121988751AHigh Al+Ti contentImprove plasticityAdditive manufacturing apparatusHigh entropy alloysSurface oxidation
The invention discloses a preparation method of a low-fault-energy high-entropy alloy, which comprises the following steps: (1) weighing spherical CoCrNiAl alloy, Co powder, Cr powder, Ni powder and Ti powder according to a stoichiometric equation AlaTibNicCodCre, (2) putting the weighed powder into a ball milling tank for ball milling, uniformly mixing the powder, and then drying, sieving and drying for storage; (3) 304L stainless steel is selected as a base material, and a sand mill is used for polishing the surface of the base material to remove surface oxide skin until a bright surface is exposed; and (4) a laser directional energy deposition method is adopted, the dried powder is placed in a powder feeding tank in a laser system, high-purity Ar gas is used for feeding the powder to a round spot laser head for melting and stacking, and layer-by-layer continuous deposition is conducted. The generation and expansion of cracks in laser additive manufacturing can be inhibited by reducing the stacking fault of a high-entropy alloy system, a large number of coherent L12 phases can be separated out in situ, and the excellent mechanical property is achieved at the normal temperature.
Owner:GUIZHOU UNIV +2
An apparatus and method for reducing the density of threading dislocation defects in silicon carbide crystals
PendingCN122235835APolycrystalline material growthFrom condensed vaporsCarbide siliconThreading dislocations
This application provides an apparatus and method for reducing the density of through-type dislocation defects in silicon carbide crystals. The apparatus includes an insulation component formed by an upper insulation layer, a first outer insulation layer, and a lower insulation layer. The insulation component is provided with gas exchange channels. By placing a crucible containing a silicon carbide seed crystal and silicon carbide raw material into the insulation component and placing them together into a single crystal growth furnace, silicon carbide crystal is grown according to the parameters set for each growth stage to obtain an N-type silicon carbide crystal. When in the isothermal section, N2 is introduced into the single crystal growth furnace in a cycle of n periods according to a first flow rate state and a second flow rate state. Nitrogen is intentionally doped into the silicon carbide crystal during the growth process through the gas exchange channels to increase the conversion probability and ejection probability of through-type dislocations to basal plane dislocations and stacking faults in the N-type silicon carbide crystal. This solves the problem of high dislocation density in SiC single crystals grown by the current PVT method.
Owner:GUANGZHOU SUMMIT CRYSTAL SEMICON CO LTD
Method of manufacturing semiconductor device and semiconductor device
To prevent a lamination defect in an SiC semiconductor device from expanding during current application.SOLUTION: A method of manufacturing a semiconductor device 10 comprises irradiating the semiconductor device 10 with helium ions to form a point defect in a buffer layer 14, where the semiconductor device comprises a substrate 12 made of silicon carbide, the buffer layer 14 of a first conductivity type on a first surface 12a of the substrate 12, and a drift layer 16 of the first conductivity type which is on the buffer layer 14 and has lower impurity concentration than the buffer layer 14. The maximum density of the point defect formed in the buffer layer 14 by the irradiation with the helium ions is 2×1016 / cm3 or larger, and the density of a point defect formed in the drift layer 16 by the irradiation with the helium ions is 2×1017 / cm3 or smaller.SELECTED DRAWING: Figure 2
Owner:SHI ATEX CO LTD
Method for determining the silicon and carbon faces of 3c-sic single crystal wafers
ActiveCN121207971BPreparing sample for investigationMaterial analysis by optical meansWaferingStacking fault
The application provides a method for determining the silicon face and carbon face of a 3C-SiC single crystal wafer, comprising the following steps: (1) immersing the 3C-SiC single crystal wafer into molten alkali for etching treatment; (2) taking out the etched 3C-SiC single crystal wafer and observing the surface morphology; if the surface only presents stacking fault characteristics, it is determined that the face is the () C face; if the surface simultaneously presents stacking fault and dislocation etching pit characteristics, it is determined that the face is the (111) Si face. The application first discovers and utilizes the inherent difference between the (111) Si face and the () C face of the 3C-SiC single crystal in the molten alkali etching morphology: the (111) Si face simultaneously presents stacking fault and dislocation etching pit, while the () C face only presents stacking fault. By observing the significant morphology contrast, the rapid and accurate discrimination of the two crystal faces can be realized.
Owner:INSTITUTE OF PHYSICS CHINESE ACADEMY OF SCIENCES
Method for pre-identification of stacking faults in heavily doped ph products
ActiveCN119715588BFinal product manufacturePreparing sample for investigationChemical physicsStacking fault
The present application relates to a method for pre-identifying the stacking fault of heavily doped Ph products, belonging to the technical field of semiconductor epitaxial detection, comprising the following operation steps: first step: preparing 4 groups of polished wafer samples, 2 groups of normal and abnormal batches, for participating in the experiment. Second step: selecting 1 sample from each of groups A, C and D for the first thermal oxidation and etching test. Third step: selecting another 1 sample from each of groups B, C and D for the second thermal oxidation and etching test. Fourth step: selecting 2 groups of samples from the normal and abnormal samples, and then using different thermal oxidation conditions and etching tests. Fifth step: microscope examination. Sixth step: pre-identifying the silicon wafer with stacking fault. The present application pre-identifies the phenomenon of full-surface stacking fault of silicon wafer after epitaxial processing in some positions of heavily doped Ph products caused by differences in thermal history. The present application avoids the situation of product waste caused by the need to identify abnormalities through epitaxial processing.
Owner:杭州中欣晶圆半导体股份有限公司
An ultrahigh-strength pure metal and a method for producing the same
ActiveCN119973103BTransportation and packagingMetal-working apparatusGrain Boundary SlidingStacking fault
The application provides an ultrahigh-strength pure metal and a preparation method thereof, and relates to the technical field of high-performance metal materials. The preparation method of the ultrahigh-strength pure metal provided by the application takes a nano pure metal powder as an initial raw material, and then forms a small block with a size of dozens of microns through high-pressure welding to form a dense pure metal without adding any alloy element. The pressure is a very pure regulation and control means, which can realize extreme strengthening of the nano metal without introducing any impurities. The pressure can effectively inhibit the grain boundary sliding of the nanocrystalline, can compact the nano metal powder to a certain extent, and can avoid grain coarsening, so that the deformation mechanism of the metal itself is activated, including various crystal defects such as full dislocation, partial dislocation, twinning, stacking fault and the like. The multiple types of defects interact with each other, generate strain fields and superimpose on each other, hinder the movement of dislocations, and then bring about strong work hardening and extreme strengthening, so that the pure metal finally realizes ultrahigh strength.
Owner:HARBIN INSTITUTE OF TECHNOLOGY (SHENZHEN) (INSTITUTE OF SCIENCE AND TECHNOLOGY INNOVATION HARBIN INSTITUTE OF TECHNOLOGY SHENZHEN) +1
Electrolyte Materials and Methods for Forming the Same
The present invention discloses a solid electrolyte material, which may include a halide-based material having a disordered crystalline structure. In one embodiment, the solid electrolyte material may include a crystalline structure containing stacking faults. In another embodiment, the solid electrolyte material may include a crystalline phase including a crystalline structure represented by a space group of the hexagonal crystal system or a space group of the rhombohedral lattice system. In another embodiment, the solid electrolyte material may include a crystalline phase including a crystalline structure represented by a monoclinic space group and a unit cell containing a reduced number of halogen atoms.
Owner:SAINT GOBAIN CERAMICS & PLASTICS INC
Treatment method for optimizing nickel-based high-temperature alloy grain boundary and nickel-based high-temperature alloy
The invention provides a treatment method for optimizing the grain boundary of a nickel-based high-temperature alloy, which comprises the following steps: carrying out pulse current treatment on the nickel-based high-temperature alloy, so that the proportion of the sigma 3 grain boundary in the treated nickel-based high-temperature alloy is greater than 50%. According to the method, annealing twin crystals are promoted to be formed through pulse current treatment, then more sigma 3 grain boundaries are formed, and the sigma 3 grain boundaries have low interface energy and high crack initiation and propagation resistance, so that the plasticity of the nickel-based high-temperature alloy can be improved, and the service life of the alloy is remarkably prolonged; on one hand, the pulse current can quickly eliminate Laves phases in the alloy, reduce element segregation and reduce stacking fault energy (SFE) of an alloy matrix, and creates favorable conditions for annealing twin crystal formation; and on the other hand, the Joule heating effect of the pulse current can improve the temperature of the alloy, reduce the grain boundary atomic diffusion barrier, increase the grain boundary mobility, effectively promote recrystallization nucleation and facilitate annealing twin crystal formation.
Owner:INST OF METAL RESEARCH - CHINESE ACAD OF SCI
Method for eliminating small stacking faults of silicon carbide based on high temperature oxidation
The application belongs to the technical field of third-generation semiconductor material defect control. A method for eliminating small-scale stacking faults of silicon carbide based on high-temperature oxidation is proposed. The silicon carbide substrate is scanned and characterized by photoluminescence, and the target small-scale stacking fault is accurately identified and positioned. Then, the substrate is cleaned to remove surface impurities, and high-temperature oxidation treatment is carried out in a dry oxygen atmosphere, and an oxidation layer is controlled to grow. The mismatch of the thermal expansion coefficient between the oxidation layer and the substrate and the reaction molar volume expansion are used to construct a composite interface stress field at the interface, drive the directional reconstruction of the atomic arrangement of the target stacking fault, and convert it into the standard sequence of the matrix. Finally, nitric oxide assisted annealing is carried out, and the nitrogen passivation effect is used to solidify the lattice configuration after reconstruction. The application has the advantages of simple process, strong compatibility, efficient and stable elimination of small-scale stacking faults, and significantly improved crystal quality of silicon carbide substrate, which provides a guarantee for the preparation of high-reliability power devices.
Owner:SHANDONG UNIV
Electrolyte material and method of forming same
The invention relates to an electrolyte material and a method of forming the same. The invention discloses a solid electrolyte material, and the solid electrolyte material can comprise a halide-based material, and the halide-based material has a crystal structure comprising disorder. In one embodiment, the solid electrolyte material may include a crystalline structure including stacking faults. In another embodiment, the solid electrolyte material may include a crystalline phase including a crystalline structure represented by a space group of a hexagonal system or a space group of a rhombohedral lattice system. In another embodiment, the solid electrolyte material may include a crystalline phase including a crystalline structure represented by a monoclinic space group and unit cells containing a reduced number of halogen atoms.
Owner:SAINT GOBAIN CERAMICS & PLASTICS INC
SiC@BN core-shell nanowire periodic array reinforced Si3N4 high-temperature wave-absorbing ceramic coating and preparation method thereof
The application discloses a SiC@BN core-shell nanowire periodic array reinforced Si3N4 high-temperature wave-absorbing ceramic coating, which is composed of SiC nanowires, a BN shell layer and a Si3N4 ceramic matrix. The SiC nanowires and the BN shell layer are obtained through a chemical vapor infiltration process, and form a core-shell structure to obtain SiC@BN core-shell nanowires, which can avoid oxidation of the SiC nanowires and improve the dielectric constant of the SiC nanowires. The SiC@BN core-shell nanowires are arranged in a three-dimensional periodic array. The Si3N4 ceramic matrix is prepared through the chemical vapor infiltration process, and the Si3N4 ceramic matrix is uniformly filled in the pores between the SiC@BN core-shell nanowires. Through macro-micro multi-scale structure design, lattice distortion, stacking faults and interface defects are introduced in the micro scale to promote the absorption and attenuation loss of the incident electromagnetic wave, and the surface electric field coupling effect and multiple scattering loss mechanism are introduced in the macro scale to realize the widening of the effective absorption band and the synergistic improvement of the electromagnetic wave absorption characteristics.
Owner:NORTHWESTERN POLYTECHNICAL UNIV