1385 results about "Epiwafer" patented technology

The invention relates to the field of semiconductor optoelectronic device manufacturing, in particular to an LED epitaxial wafer growing method capable of reducing warping. Comprising the following steps of: growing a nucleating layer on a substrate at low temperature by adopting an MOCVD (Metal Organic Chemical Vapor Deposition) process, and annealing to form a three-dimensional island-shaped structure to release stress; growing an AlGaN / GaN superlattice or gradient layer as a gradient buffer layer, and adjusting lattice constants layer by layer; a heavily doped or co-doped layer is inserted before growth of n-GaN, and thermal stress is pre-compensated by using local pressure stress; and finally, continuously growing a device layer and carrying out in-situ heat treatment to obtain the LED epitaxial wafer. The method effectively counteracts the macroscopic tensile stress caused by the difference of thermal expansion coefficients in the cooling process, and greatly improves the integrity of the epitaxial wafer.

The invention belongs to the technical field of image enhancement, and particularly relates to an image enhancement method for VCSEL (Vertical Cavity Surface Emitting Laser) epitaxial wafer detection, which comprises the following steps of: analyzing local and global gray information and structure tensor characteristics of pixel points, and calculating a defect saliency value of each pixel point to quantify the possibility of the pixel point as a defect; interference of a stripe structure in an epitaxial wafer image is weakened; a weighted histogram is constructed based on the defect saliency value, so that the defect pixel occupies a higher weight in the histogram; and determining an optimal segmentation threshold value by searching an energy median point of the weighted histogram, and finally performing BBHE enhancement on the image by using the segmentation threshold value. According to the method, the contrast ratio of the tiny defects can be remarkably improved, a high-quality image is provided for subsequent epitaxial wafer detection, and the detection accuracy is improved.

The invention belongs to the technical field of image processing, and particularly relates to a VCSEL epitaxial wafer thickness uniformity detection method comprising the following steps: obtaining a thickness map and a yield map of a VCSEL epitaxial wafer after space alignment; obtaining the global background thickness of each position in the thickness map; calculating the fluctuation standard deviation of the thickness deviation in the neighborhood of each position; obtaining a neighborhood abnormal score and a neighborhood failure rate, and obtaining a neighborhood reference parameter; calculating a problem attribution risk index according to the product of the neighborhood anomaly score and the neighborhood failure rate of each position, the neighborhood reference parameter and the Pearson's correlation coefficient and the relative deviation and correlation weighting relation; and inferring an abnormal mode type according to the problem attribution risk index, and generating an attribution report. According to the invention, the problem that the correlation attribution capability of the thickness and the yield of the VCSEL epitaxial wafer in the prior art is lacked is solved.

The invention relates to the technical field of data processing, in particular to a real-time data monitoring and early warning method for the growth process of a VCSEL epitaxial wafer, which comprises the following steps: acquiring the refractive index of a material used by the epitaxial wafer at the current moment in the growth process of the VCSEL epitaxial wafer by using MOCVD (Metal Organic Chemical Vapor Deposition) equipment; determining the growth rate of the epitaxial wafer at the current moment; determining the mutation degree of the growth rate of the epitaxial wafer at the current moment; determining the correction mutation degree of the growth rate of the epitaxial wafer at the current moment; determining an early warning threshold value at the current moment; and monitoring and early warning of real-time data in the growth process of the VCSEL epitaxial wafer are realized according to the corrected mutation degree and the early warning threshold value. According to the method, accurate inversion of the growth rate and intelligent identification of mutation are realized, abnormal and normal process changes are effectively distinguished, the early warning threshold is adaptively adjusted, the false alarm rate is reduced, and the accuracy and practicability of VCSEL epitaxial growth monitoring are improved.

The invention provides an epitaxial wafer edge morphology compensation type wafer double-sided polishing device and method, and belongs to the technical field of semiconductor wafer ultra-precision machining. The polishing main machine comprises an upper fixed disc, a lower fixed disc and a wafer driving mechanism; the pressure loading system is used for applying adjustable pressure to the fixed disc; the polishing solution supply system is used for conveying a flow-adjustable polishing solution to the processing interface; the central control unit is in communication connection with the two systems and executes edge morphology compensation control logic, specifically, the machining pressure is adjusted in a segmented mode, and the flow of the polishing solution and the pressure are subjected to coupling change. According to the method, the atomic level flatness of the wafer surface is ensured, the edge morphology is accurately controlled, the edge thickening of the epitaxial layer is perfectly counteracted, and the photoetching yield of high-end chip manufacturing is remarkably improved.

The invention discloses a Micro-LED epitaxial wafer and a preparation method thereof, a multi-quantum well light-emitting layer of the Micro-LED epitaxial wafer comprises a first sub-layer, a second sub-layer and a third sub-layer which are stacked in sequence, and each of the first sub-layer, the second sub-layer and the third sub-layer comprises a pre-well protection layer, an InGaN quantum well layer, a post-well protection layer and a quantum barrier layer which are periodically and alternately stacked; the In component proportion of the InGaN quantum well layer in the first sub-layer and the third sub-layer is smaller than the In component proportion of the InGaN quantum well layer in the second sub-layer; the well front protection layer comprises a first InGaN well front protection layer, an AlGaN well front protection layer and a second InGaN well front protection layer which are stacked in sequence, and the well rear protection layer comprises an InGaN well rear protection layer, an AlGaN well rear protection layer and a GaN well rear protection layer which are stacked in sequence. According to the invention, the light-emitting brightness of the Micro-LED can be improved.

The invention discloses a red light Micro light emitting diode epitaxial wafer and a preparation method thereof. The epitaxial wafer comprises a GaAs substrate, an N-type layer, a multi-quantum well active layer and a P-type layer which are sequentially arranged from bottom to top, the multi-quantum well active layer comprises a plurality of AlGaInP quantum well layers and quantum barrier layers which are alternately arranged, a hole injection layer is inserted between at least part of quantum well structures, and the hole injection layer is composed of a first N-type doped sub-layer, a P-type doped sub-layer and a second N-type doped sub-layer which are connected in sequence; the materials of the three sub-layers are (Al < x > Ga < 1-x >) < 0.5 > In < 0.5 > P (x is greater than or equal to 0.5 and less than or equal to 0.9), and the doping concentration is in gradient distribution along the thickness direction. By introducing the N-P-N structure hole injection layer, the hole injection efficiency is improved, electron leakage and Mg diffusion are inhibited, and the luminous efficiency of the red light Micro LED is remarkably improved.

The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and relates to the technical field of semiconductors. The light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a non-doped GaN layer, an N-type GaN layer, an electron dredging layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer which are stacked on the substrate in sequence, the electron dredging layer comprises a first sub-layer, a second sub-layer, a third sub-layer and a fourth sub-layer which are sequentially stacked, the first sub-layer is a Si3N4 layer, the second sub-layer comprises an AlGaN layer, a first InGaN layer and a first GaN layer which are periodically and alternately stacked, the third sub-layer comprises a second GaN layer and a second InGaN layer which are periodically and alternately stacked, and the fourth sub-layer is a Si3N4 layer. And the fourth sub-layer comprises an AlInGaN layer, a third InGaN layer and a third GaN layer which are periodically and alternately stacked. According to the invention, while the electronic expansibility is improved, excessive electrons are prevented from entering the multi-quantum well layer to generate electron overflow.

The invention belongs to the technical field of semiconductor device performance testing, and particularly relates to a VCSEL epitaxial wafer resistivity distribution measuring method and system, and the method comprises the steps: constructing a three-dimensional discretization model representing an epitaxial wafer and an unknown parameter vector containing the vertical resistivity, the top transverse resistivity and the substrate leakage junction nonlinear resistance; a physical response function is defined, the vector is iterated through a discrete point fitting algorithm, so that the total residual error between the analog voltage difference output by the function and the actually measured voltage value under the cross-order-of-magnitude current is minimum, and the real vertical resistivity is extracted from the optimal parameter vector; and obtaining the vertical resistivity of each point on the two-dimensional test point grid so as to generate a distribution diagram and carry out anomaly detection. According to the invention, the problem of measurement distortion caused by the leakage defect of the substrate is solved, and the measurement accuracy of the vertical resistivity is improved.

The invention provides an epitaxial wafer of a high-luminous-efficiency infrared light-emitting diode and a manufacturing method of the epitaxial wafer. The epitaxial wafer comprises a GaAs substrate, an N-type semiconductor structure, a quantum well active region and a P-type semiconductor structure, wherein the N-type semiconductor structure, the quantum well active region and the P-type semiconductor structure are formed on the substrate. The N-type semiconductor structure comprises an N-type AlGaAs stacking layer, diethyl tellurium (DETe) and disilane (Si2H6) are adopted for co-doping, the N-type semiconductor structure is designed to be of a superlattice structure, and the doping concentration in the vertical direction is periodically alternated from high to low; and a doping concentration gradient is arranged at a position close to the quantum well region, so that the tellurium doping concentration is gradually increased. Through the design, the content of carbon impurities in the material and the non-radiative recombination probability are reduced, a better current expansion effect and quantum well stress release are achieved, and the luminous efficiency and performance of an infrared LED are greatly improved.

The invention provides a GaN-based LED epitaxial wafer and a preparation method thereof, and the method comprises the following steps: S1, providing a substrate, and placing the substrate on a graphite disc of an MOCVD reaction chamber; s2, carrying out heat treatment on the substrate; s3, growing a buffer layer on the substrate after heat treatment; s4, sequentially growing an unintentional doping layer and an N-type GaN layer on the buffer layer; s5, growing a multi-quantum well light-emitting layer on the N-type GaN layer; s6, growing a P-type electron blocking layer on the multi-quantum well light-emitting layer; step S7, growing a P-type GaN layer on the P-type electron barrier layer; and S8, after growing the P-type GaN layer, adjusting the temperature of the reaction chamber to 20-30 DEG C to obtain the GaN-based LED epitaxial wafer. The GaN-based LED epitaxial wafer obtained by the method has fewer surface particles and higher surface quality.

The invention discloses a method for growing a low-surface-defect epitaxial wafer on a heavily-doped silicon substrate and the epitaxial wafer, and belongs to the field of semiconductor material preparation. The method comprises the following steps: carrying out rapid heat treatment on a heavily doped silicon substrate of which the resistivity is not greater than 1.15 m omega.cm in an inert atmosphere at the treatment temperature of 1000-1500 DEG C and the heating / cooling rate of 10-120 DEG C / s, and keeping the high temperature for 30-120 seconds; then HCl gas phase polishing is carried out at the temperature of 650-1250 DEG C, and mixed gas of HCl and hydrogen is introduced to remove a surface silicon layer by 50-150 nm; and finally growing an epitaxial layer. And the substrate can be subjected to particle detection and screening, and only the substrate with the specific pattern defect is subjected to the treatment. According to the method, through the synergistic effect of RTP and HCl polishing, in-vivo defect repairing and surface finishing are achieved, the number of LPDs, larger than or equal to 55 nm, on the surface of the epitaxial wafer is stably reduced to 10 or below, and the quality of the epitaxial wafer is remarkably improved.

The invention provides a surface-emitting gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof, and relates to the technical field of laser chips, the surface-emitting gallium nitride VCSEL laser chip comprises a substrate, a low-temperature nucleating layer, a high-temperature recovery layer, a stress regulation type nano mask composite defect blocking layer, an n-type nitride DBR reflector, an active region, a polarization enhanced tunnel junction and the like, the defect blocking layer adopts an in-situ silicon nitride nano-porous mask layer to be matched with an aluminum gallium nitride / gallium nitride stress compensation superlattice layer, through pulse type lateral epitaxial overgrowth annihilation penetrating dislocation, and the n-type nitride DBR reflector adopts an AlInN / GaN lattice matching material system to be combined with a hydrogen etching interruption modification technology, so that thick film growth with zero cracks and high reflectivity is realized; a polarization enhanced tunneling junction is used at the top to replace ITO, and the hole tunneling probability is enhanced by piezoelectric polarization in InGaN, so that efficient current injection with low working voltage and no absorption loss is realized, the dislocation density and the device voltage are remarkably reduced, and the yield of an epitaxial wafer and the photoelectric conversion efficiency are improved.

The present invention provides a light-emitting diode epitaxial wafer and a method for fabricating the same. The light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a three-dimensional nucleation layer, an undoped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially deposited on the substrate. The three-dimensional nucleation layer comprises a stacked first and second three-dimensional nucleation sublayers, the thickness of the first three-dimensional nucleation sublayer being less than that of the second three-dimensional nucleation sublayer, both being MgGaN layers, and the growth temperature of the second three-dimensional nucleation sublayer being 10 to 100°C higher than that of the first three-dimensional nucleation sublayer. This light-emitting diode epitaxial wafer can increase the density of V-pits, improve carrier injection efficiency, and enhance the optoelectronic performance of the light-emitting diode.

The invention relates to an epitaxial wafer defect positioning method based on machine vision, and relates to the field of defect localization, dislocation and crack scale parameters are predicted by collecting a control parameter sequence in the epitaxial wafer growth process, then the number of microscopic image collection areas is configured, a recognition area is selected on an epitaxial wafer, and microscopic images are collected; dislocation and crack identification is carried out by utilizing machine vision, the propagation direction of the dislocation is predicted when the dislocation is identified, meanwhile, the crack influence coefficient when the dislocation and the crack coexist is processed to correct the number of crack areas, and finally, identification and correction are continued according to the dislocation propagation direction. The technical problem that the defect detection efficiency and accuracy are insufficient due to the fact that control parameters, defect propagation rules and mutual influences in the epitaxial wafer growth process are difficult to comprehensively consider is solved, accurate positioning of epitaxial wafer defects is achieved, and the defect detection accuracy is improved. And the efficiency and the accuracy of epitaxial wafer defect detection are obviously improved.

The present invention relates to the field of optoelectronics, and discloses a light-emitting diode epitaxial wafer, a method for manufacturing the same, and an LED. The light-emitting diode epitaxial wafer comprises a substrate, on which a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electron blocking layer, and a P-type GaN layer are sequentially provided; the electron blocking layer comprises a BAlN / P-GaN superlattice layer, an AlGaN / P-InGaN superlattice layer, and a BN layer stacked in sequence. The light-emitting diode epitaxial wafer provided by the present invention reduces electron overflow, improves hole injection efficiency, replenishes hole concentration, and enhances the luminous efficiency of the light-emitting diode.

The invention discloses a double-color light-mixing LED structure and a preparation method thereof, relates to the technical field of semiconductor photoelectronics, and realizes chip-level double-color light mixing by integrating two independent epitaxial light-emitting units on the same epitaxial wafer, thereby not only greatly simplifying the preparation process, but also remarkably improving the light mixing uniformity and the light color stability. The double-color light-mixing LED structure comprises a first epitaxial light-emitting unit in a central area, and the first epitaxial light-emitting unit emits first colored light; the second epitaxial light-emitting unit in the peripheral area emits second colored light, and the peak wavelength of the second colored light is longer than that of the first colored light; the second epitaxial light-emitting unit is arranged around the first epitaxial light-emitting unit, and the first colored light and the second colored light are emitted after being mixed.

The embodiment of the invention provides a GaAs-based HBT epitaxial wafer multi-parameter cooperative control growth processing system. The GaAs-based HBT epitaxial wafer multi-parameter cooperative control growth processing system comprises a data acquisition module which is used for monitoring the actual temperature of different positions of a substrate tray and the growth thickness of an epitaxial layer in real time; the temperature regulation and control module is used for independently regulating the temperature of each area according to a preset target temperature range to form temperature gradient distribution; the carrier gas control module is used for dynamically adjusting the carrier gas flow according to the temperature adjustment result to maintain uniform distribution of reaction gas and stable reaction rate; the growth rate monitoring module is used for comparing the actually measured growth thickness with the theoretical design thickness and triggering compensation adjustment when the deviation exceeds a set threshold value; and the model processing module is used for establishing a mathematical model among the temperature, the gas carrying capacity and the growth rate to predict and optimize the growth process. By systematically integrating each functional module, accurate control and intelligent management of the epitaxial growth process are realized, and the product consistency and the production efficiency are remarkably improved.

The invention provides a SiC epitaxial wafer and a preparation method thereof, relates to the technical field of semiconductor chips, and aims to reduce the defect density of the SiC epitaxial wafer, and the SiC epitaxial wafer comprises a SiC substrate and an epitaxial layer arranged on one side of the SiC substrate. The epitaxial layer comprises a C surface and a Si surface which are oppositely arranged, any one of the C surface and the Si surface is close to the SiC substrate, the thickness range of the epitaxial layer is 50-500 microns, and the defect density range of the epitaxial layer is 0.02 / cm < 2 >-1 / cm < 2 >.

According to the LED thin-film device and the preparation method thereof provided by the invention, the problem that a silicon support substrate is broken due to overlarge warping degree after evaporation is avoided in a manner of bonding and then performing back gold evaporation. By evaporating a plurality of stress-adjusting metal layers, the metal on the back surface of the silicon support substrate generates downward large pressure stress on the silicon support substrate so as to counteract the pressure stress back to the silicon support substrate generated after a substrate of an epitaxial wafer is removed, so that the warping degree of a thin film device is reduced, and large-scale production is realized. The preparation method comprises the following steps: providing an LED epitaxial wafer, wherein the LED epitaxial wafer comprises a substrate and an epitaxial layer; sequentially preparing a reflector layer and a first bonding layer on the epitaxial layer; providing a silicon support substrate, and preparing a second bonding layer on the front surface of the silicon support substrate; the thickness of the silicon support substrate is less than 180 [mu] m; the LED epitaxial wafer and the silicon supporting substrate are bonded; evaporating a metal layer for adjusting stress on the back surface of the silicon support substrate; the metal layer sequentially comprises a bonding layer, a stress adjusting layer and a contact layer; and removing the substrate.

The invention provides an enhanced GaN HEMT (High Electron Mobility Transistor) device and a preparation method thereof. The device comprises a substrate; the epitaxial structure is epitaxially grown on the substrate; the secondary epitaxial layer is epitaxially grown on the epitaxial structure; the dielectric layer is arranged on the secondary epitaxial layer; communicated groove regions are arranged in the p-GaN layer, the dielectric layer and the secondary epitaxial layer, and the p-GaN layer epitaxially grows in the groove regions from the upper surface of the epitaxial structure; the grid electrode is arranged on the p-GaN layer; and the source electrode and the drain electrode are respectively arranged at two sides of the epitaxial structure, the secondary epitaxial layer and the dielectric layer. The device has a better high-frequency dynamic characteristic; the stability and the consistency of the grid threshold voltage are improved; the crack generation risk of the epitaxial wafer is low, and the MBE-grown p-GaN does not need to be subjected to subsequent activation treatment; the gate reliability is improved, and the stability of the device is further improved.

The invention relates to the technical field of stress testing, in particular to a VCSEL epitaxial wafer stress distribution monitoring method and system. The method comprises the following steps: acquiring a PL spectrum of each measurement point and a peak wavelength of the PL spectrum, and decomposing the PL spectrum into polarization components along a first crystal orientation and a second crystal orientation; obtaining the initial polarization orthogonality of the measurement point based on the peak intensity of the polarization component; obtaining a reference wavelength of the VCSEL epitaxial wafer, and calculating a thermally induced wavelength drift factor of a measurement point; based on the thermally induced wavelength drift factor and a set maximum saturation value, thermally induced polarization artifacts of the measurement points are calculated, the thermally induced polarization artifacts are in positive correlation with the thermally induced wavelength drift factor, and the maximum saturation value is taken as an upper limit; subtracting the thermally induced polarization artifact from the initial polarization orthogonality to obtain a pure stress index; the pure stress indexes are mapped to the corresponding coordinates, the stress distribution diagram of the VCSEL epitaxial wafer is obtained, and the accuracy of the stress distribution monitoring result of the VCSEL epitaxial wafer is effectively improved.

The invention provides a silicon carbide substrate for epitaxial growth, a preparation method of the silicon carbide substrate, a silicon carbide epitaxial wafer and a preparation method of the silicon carbide epitaxial wafer. In one aspect, there is provided a method for preparing a silicon carbide substrate for epitaxial growth, the method comprising: performing ion implantation on a surface of the silicon carbide substrate to form a damaged region below the surface; and annealing the silicon carbide substrate subjected to ion implantation so as to recrystallize the damaged region and form a defect gettering layer comprising a dislocation ring. Therefore, the density of defects in the epitaxial layer can be remarkably reduced, and the silicon carbide epitaxial wafer with more excellent crystal quality can be obtained.

The invention relates to an epitaxial structure of a low-specific on-resistivity GaN HEMT and a preparation method thereof, and the preparation method comprises the steps: S1, sequentially growing an initial layer, a buffer layer, a channel layer, a first insertion layer, a first barrier layer, a second insertion layer and a second barrier layer on a substrate from bottom to top, and obtaining a thick barrier epitaxial wafer; s2, preparing a hard mask layer, patterning and etching the hard mask layer, then transferring the hard mask layer to the upper surface of the thick barrier epitaxial wafer, and etching the thick barrier epitaxial wafer to the upper surface of the second insertion layer; s3, secondarily growing a p-GaN layer on the upper surface of the second insertion layer in the gate region; and S4, removing the polycrystalline GaN in a non-gate region, depositing metal on the p-GaN layer to manufacture a gate, and depositing metal on two sides of the structure to manufacture a source and a drain respectively. By selectively growing the p-GaN layer in the grid region, two-dimensional electron gas in a channel is effectively exhausted, and the carrier concentration of the region below the grid is remarkably reduced.

The embodiment of the invention provides a semiconductor substrate, an epitaxial wafer and a semiconductor device. The semiconductor substrate comprises a silicon carbide substrate layer, a transition layer arranged on the carbon surface of the silicon carbide substrate layer, and a stress regulation and control layer arranged on the side, away from the silicon carbide substrate layer, of the transition layer. The transition layer comprises a two-dimensional material layer, and the stress regulation layer comprises a 3C-SiC layer; or the transition layer comprises a polycrystalline 3C-SiC layer, and the stress regulation layer comprises a single crystal 3C-SiC layer. According to the semiconductor substrate provided by the embodiment of the invention, the transition layer and the stress regulation and control layer are arranged on the silicon carbide substrate layer, so that the surface type of the SiC substrate can be effectively improved, and the problem of non-uniform thickness distribution of the epitaxial layer caused by an overlarge bow value of the substrate in a SiC epitaxial process is solved to a certain extent, thereby improving the manufacturing yield of an epitaxial wafer, and improving the yield of the epitaxial wafer. Manufacturing cost is reduced, and semiconductor device performance is improved.

Provided is an epitaxial wafer having a silicon epitaxial film on a silicon single crystal substrate having a resistivity of 10 [Omega] * cm or more and 5000 [Omega] * cm or less, the epitaxial wafer being characterized in that the concentration of carbon atoms in the silicon epitaxial film is 5 * 1017 atoms / cm < 3 > or more and less than 2 * 1019 atoms / cm < 3 >, and carbon defects are formed in the silicon epitaxial film. As a result, provided are: an epitaxial wafer and an SOI wafer which can be manufactured with a small number of steps without using a high-resistivity substrate, are easy to process, and more reliably reduce harmonics; and a method for manufacturing the epitaxial wafer and the SOI wafer.

The invention provides an ITO film preparation method, an LED chip and electronic equipment, and the method comprises the steps: providing an epitaxial wafer, and depositing an initial ITO film; preparing an initial photoresist mask on the initial ITO film, and performing first etching to form a patterned transition ITO film; heating the initial photoresist mask to soften the initial photoresist mask so as to form a final photoresist mask; and performing second etching on the transition ITO film based on the final photoresist mask to form a final ITO film. The graphical transition ITO film is obtained through the first etching, the edge of the initial photoresist mask is softened and then collapses downwards to form the final photoresist mask, the transition ITO film is protected, the over-etching phenomenon is effectively avoided, meanwhile, residual ITO, metal and other impurities can be removed through the second etching, and abnormity of the appearance and the electrical yield of the chip is prevented.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer contains an impurity element which determines the conductivity type of the epitaxial layer and boron which has a conductivity type different from the conductivity type of the impurity element, and the concentration of boron is less than 1.0×1014 cm−3 at any position in the plane of the epitaxial layer.

The invention discloses a vertical LED chip and a preparation method thereof, and relates to the field of semiconductor photoelectric devices. The preparation method of the vertical LED chip comprises the following steps: S1, providing an epitaxial wafer; s2, forming a transparent conductive layer, a SiO2 mask layer and a photoresist layer in sequence; s3, removing the SiO2 mask layer and the transparent conductive layer in the first preset area; s4, removing the P-type contact layer in the first preset area; s5, forming a dielectric layer; s6, the dielectric layer on the SiO2 mask layer is removed, and then the remaining SiO2 mask layer is removed; s7, forming a DBR reflecting layer; s8, etching and exposing the transparent conductive layer; s9, sequentially forming a metal reflecting layer and a bonding layer; s10, bonding with a second substrate; s11, forming an N electrode and a P electrode to obtain an LED wafer; and S12, cutting the LED wafer to obtain a vertical LED chip. According to the invention, the luminous efficiency of the vertical LED chip can be improved.

The invention discloses a high-quality silicon carbide homoepitaxial wafer and a preparation method thereof, the epitaxial wafer comprises an epitaxial layer, a SiC substrate and a regulation and control layer, the regulation and control layer is located outside the back surface of the substrate or inside the back surface of the substrate, and the epitaxial layer is located on the front surface of the substrate; wherein the lattice mismatch degree between the regulation and control layer and the substrate has the same sign as the lattice mismatch degree between the epitaxial layer and the substrate, but the absolute value is larger; the preparation method comprises the following steps: preparing the regulation and control layer on the back surface of the SiC substrate; front deposition and surface scratch of the substrate caused by the previous step are eliminated through chemical mechanical polishing; growing an epitaxial layer on the front surface of the substrate through epitaxial deposition; and finally, chemically and mechanically polishing to eliminate micro pits and step coalescence morphology on the surface of the epitaxial layer to obtain the epitaxial wafer. The regulation and control layer is introduced to the back surface of the substrate, lattice mismatch between the epitaxial layer and the substrate is weakened through the regulation and control layer, dislocation proliferation and slippage are reduced, and the high-quality silicon carbide homoepitaxial wafer with low defect density and small deformation is prepared.