2284 results about "Epiwafer" patented technology

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the technical field of semiconductors. The light-emitting diode epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, a low-temperature stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer and a P-type semiconductor layer. The multi-quantum well light-emitting layer comprises a first sub-layer, a second sub-layer, a third sub-layer and a fourth sub-layer which are stacked in sequence, and each of the first sub-layer, the second sub-layer, the third sub-layer and the fourth sub-layer comprises an InGaN quantum well layer and a GaN quantum barrier layer which are periodically and alternately stacked; an electron injection layer is inserted into at least one of the GaN quantum barrier layer of the first sub-layer, the GaN quantum barrier layer of the second sub-layer and the GaN quantum barrier layer of the third sub-layer; and a hole injection layer is inserted into the GaN quantum barrier layer of the fourth sub-layer. By implementing the invention, the electron hole matching degree of the multi-quantum well light-emitting layer can be improved, so that the luminous efficiency of the light-emitting diode is improved.

The invention provides a temperature optimization method for a gallium source furnace of a molecular beam epitaxy system, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: under a plurality of different filament temperature difference conditions, epitaxially growing epitaxial layers with preset structures to obtain a plurality of epitaxial wafers corresponding to the temperature difference conditions; measuring and acquiring surface defect data of the epitaxial wafer; establishing a model for representing the relationship between the defect data and the filament temperature difference; calculating a constant value in the model through numerical fitting; and substituting the constant value into the model, calculating and solving the minimum value of y in the model, and taking the filament temperature difference corresponding to the minimum value of y as the filament temperature difference of the gallium source furnace during next epitaxial growth. According to the method, the model is established, the model constant value is solved, and the filament temperature difference corresponding to the minimum surface defect is obtained by using the model, so that the filament temperature difference of the gallium source furnace is optimized and the surface defect is reduced. In mass production, the measurement results are continuously added to fitting data of the model, so that the process conditions can be continuously improved.

The invention discloses a gallium oxide monolithic heterogeneous integrated device and a manufacturing method thereof, which can be used in the field of semiconductor devices, in the device, an N-type gallium oxide epitaxial wafer comprises an epitaxial layer and a substrate layer; one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded with one side of the P-type material layer; the N-type doped region is arranged in the P-type material layer and is in contact with the epitaxial layer of the N-type gallium oxide epitaxial wafer; the gate control region covers the N-type doped region and is arranged on the other side of the P-type material layer; ohmic contact is formed between the source electrode and the P-type material layer. The drain electrode is arranged on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms ohmic contact with the substrate layer; and the substrate layer is bonded with the drain electrode. Therefore, small-size gallium oxide is bonded to the substrate for tape-out, so that large-scale preparation of the device on a production line can be realized, and the heat dissipation performance of the gallium oxide device is improved; by bonding the N-type gallium oxide and the P-type material, a heterogeneous PN junction is formed to make up for a missing gallium oxide homogeneous PN junction, and the stability of the structure is improved.

Disclosed is a method for monolithic integration preparation of a full-color nitride semiconductor micro light-emitting diode (micro-LED) array. The method includes preparing a composite conductive substrate; overlaying an insulating template onto the composite conductive substrate to prepare a template substrate; overlaying monocrystalline graphene onto the template substrate in a completely aligned manner to obtain a customized template graphene substrate including graphene array units, wherein one blue-region graphene array element, one green-region graphene array element, and two red-region graphene array elements in each graphene array unit have surface properties different from each other; then performing an in-situ process to epitaxially grow a vertical-structure all-nitride material, to obtain a full-color micro-LED array epitaxial wafer by one-step in-situ process; finally, performing packaging and preparing a transparent electrode, to obtain a vertical-structure full-color nitride micro-LED array with top light emission.

The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer sequentially comprises a substrate, a buffer layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer. The buffer layer sequentially comprises a first AlN layer, a second AlN layer, a third AlN layer, a first superlattice layer, a first AlGaN layer, a second superlattice layer and a first GaN layer; the first superlattice layer comprises a fourth AlN layer and a second AlGaN layer which are alternately stacked, and the second superlattice layer comprises a third AlGaN layer and a second GaN layer which are alternately stacked; a first V-shaped pit extending to the second superlattice layer is formed in the third AlN layer, a second V-shaped pit is formed in the first superlattice layer, and the second V-shaped pit is filled and leveled up by the first AlGaN layer; the second superlattice layer forms a third V-shaped pit, and the first V-shaped pit and the third V-shaped pit are filled and leveled up by the first GaN layer. By implementing the invention, the luminous efficiency can be improved.

The invention provides a gallium oxide epitaxial wafer preparation method, an epitaxial growth system and a gallium oxide epitaxial wafer. The method comprises the following steps: placing a (100)-surface gallium oxide substrate in a reaction chamber, introducing a carrier gas with a first preset flow, setting the pressure in the reaction chamber to be a first preset pressure, and raising the temperature to a first preset temperature; a second preset flow of hydrogen is introduced, and the (100) surface gallium oxide substrate is pretreated; setting the pressure in the reaction chamber as a second preset pressure, raising the temperature of the source region to a second preset temperature, and raising the temperature of the growth region to a third preset temperature; and introducing hydrogen chloride with a third preset flow rate, oxygen with a fourth preset flow rate and hydrogen with a fifth preset flow rate into the reaction chamber, and carrying out vapor phase epitaxy so as to prepare the (100)-surface gallium oxide epitaxial film on the surface of the (100)-surface gallium oxide substrate. The method can promote step flow growth, reduce polycrystal particle aggregation, reduce three-dimensional island-shaped growth, and improve the surface continuity and quality of an epitaxial film.

The invention belongs to the technical field of integrated circuits, and particularly relates to a nitride HEMT device with a light-emitting structure and a preparation method of the nitride HEMT device. The HEMT device comprises a heterojunction epitaxial wafer, a light-emitting structure, a grid electrode, a source electrode and a drain electrode. The heterojunction epitaxial wafer sequentially comprises a substrate, a buffer layer formed by III-group nitride, a channel layer and a barrier layer from bottom to top. The light-emitting structure is prepared through a selective area epitaxial growth technology and sequentially comprises a quantum well layer, a P-type nitride layer, a current expansion layer and a P-type electrode from bottom to top. Wherein the quantum well layer can also be used as a barrier layer, and the P-type electrode and the drain electrode are interconnected through metal. According to the invention, the drain electrode of the nitride device is connected with the P-type electrode of the light-emitting structure, so that when the device is turned on, the quantum well layer of the light-emitting structure emits light at the same time, photons are incident into the device body, electrons in various deep energy levels in the device body are effectively accelerated to break away from traps, the current collapse effect of the device is effectively inhibited, and the stability of the device is improved.

A method of preparing a silicon-on-insulator structure includes forming an epitaxial silicon layer on a front surface of a single crystal silicon donor substrate, forming a dielectric layer on the epitaxial silicon layer to thereby form an epitaxial donor structure including the single crystal silicon donor substrate, the epitaxial silicon layer, and the dielectric layer, bonding the dielectric layer of the epitaxial donor structure to a front surface of a handle structure, the handle structure including a single crystal semiconductor handle substrate, to thereby form a bonded structure including the handle structure, the dielectric layer, the epitaxial silicon layer, and the single crystal silicon donor substrate, and removing the single crystal silicon donor substrate and a portion of the epitaxial silicon layer from the bonded structure to thereby form the silicon-on-insulator structure including the handle structure, the dielectric layer, and a silicon device layer.

The invention relates to the technical field of semiconductor processing, and particularly discloses a gas inlet structure and a P-type silicon carbide epitaxial growth device and method.The gas inlet box adopts three channels for gas inlet, the mode that C2H4, TCS and TMA enter a reaction chamber can be flexibly controlled, and the thickness of large-size SiC epitaxy and the uniformity of doping concentration can be more accurately regulated and controlled; by adjusting the combination of the air inlet channel and the flow, the P-type doping concentration difference between the edge and the center of the SiC epitaxial wafer can be greatly reduced during P-type high-speed epitaxial growth, and low doping concentration non-uniformity is achieved; starting from two aspects of SiC epitaxial equipment hardware and a process method, a simple and effective hardware design scheme and an epitaxial process method are provided to solve the problem of poor doping concentration uniformity of a P-type epitaxial wafer during high-speed epitaxial growth. Compared with single modification of epitaxial equipment or single adjustment of epitaxial process parameters, the method is more time-saving and labor-saving, and the effect is better.

The invention relates to the field of semiconductor optoelectronic device manufacturing, in particular to an LED epitaxial wafer growing method capable of reducing warping. Comprising the following steps of: growing a nucleating layer on a substrate at low temperature by adopting an MOCVD (Metal Organic Chemical Vapor Deposition) process, and annealing to form a three-dimensional island-shaped structure to release stress; growing an AlGaN / GaN superlattice or gradient layer as a gradient buffer layer, and adjusting lattice constants layer by layer; a heavily doped or co-doped layer is inserted before growth of n-GaN, and thermal stress is pre-compensated by using local pressure stress; and finally, continuously growing a device layer and carrying out in-situ heat treatment to obtain the LED epitaxial wafer. The method effectively counteracts the macroscopic tensile stress caused by the difference of thermal expansion coefficients in the cooling process, and greatly improves the integrity of the epitaxial wafer.

The invention relates to the technical field of photoelectricity, and discloses a full-spectrum LED epitaxial wafer, a preparation method thereof and an LED chip, the epitaxial wafer comprises a substrate, and the substrate is sequentially provided with a buffer layer, an N-type GaN layer, a multispectral light-emitting well layer and a P-type GaN layer; the multispectral light-emitting well layer comprises a first light-emitting well layer, a second light-emitting well layer and a third light-emitting well layer which are stacked in sequence, the first light-emitting well layer comprises a plurality of groups of InxGa (1-x) N quantum well layers, AlaGa (1-a) N interface layers and first GaN quantum barrier layers which are stacked in sequence, the second light-emitting well layer comprises a plurality of groups of InyGa (1-y) N quantum well layers, AlbGa (1-b) N interface layers and second GaN quantum barrier layers which are stacked in sequence, and the third light-emitting well layer comprises a plurality of groups of InzGa (1-z) N quantum well layers, AlcGa (1-c) N interface layers and third GaN quantum barrier layers which are stacked in sequence. According to the full-spectrum LED epitaxial wafer provided by the invention, the luminous efficiency and the color rendering index of a full-spectrum chip can be improved.

The invention discloses an epitaxial wafer and a preparation method thereof, and belongs to the technical field of semiconductor manufacturing. The preparation method of the epitaxial wafer comprises the following steps: raising the temperature of a reaction cavity to a first annealing temperature T1; reducing the temperature of the reaction cavity from the first annealing temperature T1 to a second annealing temperature T2 so as to perform annealing treatment on the substrate in the reaction cavity; forming a buffer layer on the substrate; forming an epitaxial layer on one side, away from the substrate, of the buffer layer; wherein the first annealing temperature T1 and the second annealing temperature T2 meet the following condition: T2lt; t1. According to the invention, by annealing the substrate, part of stress in the substrate can be eliminated, and the contact surface between the substrate and the buffer layer can be improved, so that the BPD conversion rate can be improved, and the BPD defects are reduced.

The invention relates to the technical field of photoelectricity, and discloses a Micro LED epitaxial wafer, a preparation method thereof and a Micro LED chip, the Micro LED epitaxial wafer comprises a substrate, and the substrate is sequentially provided with a buffer layer, an N-type GaN layer, a multi-quantum well layer and a P-type GaN layer; the first multi-quantum well layer comprises at least one group of a first InGaN quantum well layer, a first AlGaN / GaN superlattice layer and a first GaN quantum barrier layer which are stacked in sequence, and the second multi-quantum well layer comprises at least one group of a second InGaN quantum well layer, a second AlGaN / GaN superlattice layer and a second GaN quantum barrier layer which are stacked in sequence. And the third multi-quantum well layer comprises at least one group of third InGaN quantum well layer, hole injection layer and third GaN quantum barrier layer which are stacked in sequence. According to the Micro LED epitaxial wafer provided by the invention, the lighting effect of a Micro LED chip under low working current density can be improved.

The invention belongs to the technical field of image enhancement, and particularly relates to an image enhancement method for VCSEL (Vertical Cavity Surface Emitting Laser) epitaxial wafer detection, which comprises the following steps of: analyzing local and global gray information and structure tensor characteristics of pixel points, and calculating a defect saliency value of each pixel point to quantify the possibility of the pixel point as a defect; interference of a stripe structure in an epitaxial wafer image is weakened; a weighted histogram is constructed based on the defect saliency value, so that the defect pixel occupies a higher weight in the histogram; and determining an optimal segmentation threshold value by searching an energy median point of the weighted histogram, and finally performing BBHE enhancement on the image by using the segmentation threshold value. According to the method, the contrast ratio of the tiny defects can be remarkably improved, a high-quality image is provided for subsequent epitaxial wafer detection, and the detection accuracy is improved.

The invention relates to the technical field of photoelectricity, and discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and an LED, the light-emitting diode epitaxial wafer comprises a substrate, and the substrate is sequentially provided with a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer; the multi-quantum well layer comprises a high-barrier multi-quantum well layer, a middle-barrier multi-quantum well layer, a low-barrier multi-quantum well layer and a low-barrier end multi-quantum well layer which are stacked in sequence. According to the light-emitting diode epitaxial wafer provided by the invention, the hole injection efficiency of the P-type semiconductor material can be improved, the phenomenon of insufficient hole concentration in the multi-quantum well layer is improved, and the matching degree of electron hole concentration in the multi-quantum well layer is improved, so that the radiation recombination efficiency in the multi-quantum well layer is improved, and the brightness and the lighting effect of an LED device are finally improved.

The invention provides an epitaxial growth process for improving doping uniformity of n-type doped silicon carbide, and relates to the technical field of semiconductors. The method is based on a chemical vapor deposition growth technology; 11 to 20 gt; the silicon carbide epitaxial growth is carried out by taking silicon carbide with a 4-degree silicon surface in the direction as a substrate, taking trichlorosilane (TCS) and ethylene (C2H4) as growth sources and taking ammonia gas (NH3) as a doping source. Ammonia gas is adopted as an n-type dopant, the decomposition efficiency of the n-type dopant is close to 100% at the temperature of 700 DEG C or above, and the energy of N-H bond breakage of ammonia gas molecules is 390 KJ / mo which is far lower than 946 KJ / mo needed by N-N bond breakage of nitrogen molecules. Therefore, compared with a traditional doping source such as nitrogen, the ammonia gas has higher doping efficiency, residues of excessive nitrogen-containing precursors in the reaction chamber can be reduced, the memory effect is reduced, and thus more excellent in-chip uniformity and stable inter-chip repeatability of the epitaxial wafer are obtained. The selection range of the doping source is widened, the accurate control of the doping concentration is realized, and the stability of the doping concentration in the continuous growth process is improved.

The invention belongs to the technical field of image processing, and particularly relates to a VCSEL epitaxial wafer thickness uniformity detection method comprising the following steps: obtaining a thickness map and a yield map of a VCSEL epitaxial wafer after space alignment; obtaining the global background thickness of each position in the thickness map; calculating the fluctuation standard deviation of the thickness deviation in the neighborhood of each position; obtaining a neighborhood abnormal score and a neighborhood failure rate, and obtaining a neighborhood reference parameter; calculating a problem attribution risk index according to the product of the neighborhood anomaly score and the neighborhood failure rate of each position, the neighborhood reference parameter and the Pearson's correlation coefficient and the relative deviation and correlation weighting relation; and inferring an abnormal mode type according to the problem attribution risk index, and generating an attribution report. According to the invention, the problem that the correlation attribution capability of the thickness and the yield of the VCSEL epitaxial wafer in the prior art is lacked is solved.

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer sequentially comprises a substrate, a buffer layer, an intrinsic semiconductor layer, an N-type semiconductor layer, a multi-quantum well layer, an electron blocking layer and a P-type semiconductor layer. The P-type semiconductor layer comprises a Si3N4 layer, a first superlattice layer and a second superlattice layer which are sequentially stacked on the electron blocking layer, the first superlattice layer comprises a Mg-doped Al < x > Ga < 1-x > N layer and a Mg-doped GaN layer which are alternately stacked, and the second superlattice layer comprises a non-doped GaN layer and a Mg-doped In < y > Ga < 1-y > N layer which are alternately stacked. By implementing the invention, the luminous efficiency of the light-emitting diode can be improved.

The invention relates to the technical field of data processing, in particular to a real-time data monitoring and early warning method for the growth process of a VCSEL epitaxial wafer, which comprises the following steps: acquiring the refractive index of a material used by the epitaxial wafer at the current moment in the growth process of the VCSEL epitaxial wafer by using MOCVD (Metal Organic Chemical Vapor Deposition) equipment; determining the growth rate of the epitaxial wafer at the current moment; determining the mutation degree of the growth rate of the epitaxial wafer at the current moment; determining the correction mutation degree of the growth rate of the epitaxial wafer at the current moment; determining an early warning threshold value at the current moment; and monitoring and early warning of real-time data in the growth process of the VCSEL epitaxial wafer are realized according to the corrected mutation degree and the early warning threshold value. According to the method, accurate inversion of the growth rate and intelligent identification of mutation are realized, abnormal and normal process changes are effectively distinguished, the early warning threshold is adaptively adjusted, the false alarm rate is reduced, and the accuracy and practicability of VCSEL epitaxial growth monitoring are improved.

The invention discloses a homogeneous pn junction terminal gallium oxide Schottky barrier diode and a preparation method thereof. The problems that gallium oxide p-type doping is difficult, and heterojunction electric leakage is high and voltage resistance is low are solved. The semiconductor device comprises a cathode, an n-Ga2O3 substrate and an n-Ga2O3 epitaxial layer from bottom to top, ion implantation regions are arranged at the left end and the right end of the upper surface of the n-Ga2O3 epitaxial layer, and the upper surface of the n-Ga2O3 epitaxial layer is covered with an anode; the ion implantation region is subjected to annealing treatment to form a p-type Ga2O3 region, and the p-type Ga2O3 region and the n-Ga2O3 epitaxial layer form a homogeneous pn junction terminal, so that the gallium oxide Schottky barrier diode with high voltage resistance and low electric leakage is realized. The preparation method comprises the steps of cleaning an epitaxial wafer, photoetching to form a region to be implanted with ions, carrying out ion implantation, cleaning, carrying out rapid thermal annealing to form p-Ga2O3, and preparing a cathode and an anode. According to the invention, N / P ions are injected, annealing treatment is carried out, a gallium-oxygen-nitrogen-phosphorus compound with a p-type characteristic is generated in the n-Ga2O3 epitaxial layer, and the homogeneous pn junction terminal gallium oxide Schottky barrier diode is realized. The method can be used in high-voltage and high-power fields such as power grids and high-speed rails

The invention provides an epitaxial wafer edge morphology compensation type wafer double-sided polishing device and method, and belongs to the technical field of semiconductor wafer ultra-precision machining. The polishing main machine comprises an upper fixed disc, a lower fixed disc and a wafer driving mechanism; the pressure loading system is used for applying adjustable pressure to the fixed disc; the polishing solution supply system is used for conveying a flow-adjustable polishing solution to the processing interface; the central control unit is in communication connection with the two systems and executes edge morphology compensation control logic, specifically, the machining pressure is adjusted in a segmented mode, and the flow of the polishing solution and the pressure are subjected to coupling change. According to the method, the atomic level flatness of the wafer surface is ensured, the edge morphology is accurately controlled, the edge thickening of the epitaxial layer is perfectly counteracted, and the photoetching yield of high-end chip manufacturing is remarkably improved.

The invention relates to the technical field of LEDs, in particular to a quaternary yellow-green LED epitaxial wafer and a preparation method thereof. The quaternary yellow-green LED epitaxial wafer sequentially comprises a GaAs substrate, a GaAs buffer layer, an N-type gradient doped waveguide layer, a single quantum well active layer, a P-type gradient doped waveguide layer, a P-type self-absorption layer, a P-type transition layer and a P-type periodic current expansion layer from bottom to top. Through the design that the N / P type gradient doped waveguide layer is combined with the single quantum well active layer, the P type self-absorption layer and the P type GaP / GaAsP periodic current expansion layer, and the MOCVD technology is adopted for growth, the obtained low-brightness and high-reliability quaternary yellow-green LED epitaxial wafer structure has the advantages of being high in antistatic performance, excellent in aging performance, good in surface flatness and uniformity, high in light emitting efficiency and the like. The method has the characteristics of simple process, low production cost and raw material cost and the like, is used for replacing two-component and three-component LEDs grown by an LPE technology, and has better reliability and application prospect.

The invention discloses a Micro-LED epitaxial wafer and a preparation method thereof, a multi-quantum well light-emitting layer of the Micro-LED epitaxial wafer comprises a first sub-layer, a second sub-layer and a third sub-layer which are stacked in sequence, and each of the first sub-layer, the second sub-layer and the third sub-layer comprises a pre-well protection layer, an InGaN quantum well layer, a post-well protection layer and a quantum barrier layer which are periodically and alternately stacked; the In component proportion of the InGaN quantum well layer in the first sub-layer and the third sub-layer is smaller than the In component proportion of the InGaN quantum well layer in the second sub-layer; the well front protection layer comprises a first InGaN well front protection layer, an AlGaN well front protection layer and a second InGaN well front protection layer which are stacked in sequence, and the well rear protection layer comprises an InGaN well rear protection layer, an AlGaN well rear protection layer and a GaN well rear protection layer which are stacked in sequence. According to the invention, the light-emitting brightness of the Micro-LED can be improved.

The invention discloses a red light Micro light emitting diode epitaxial wafer and a preparation method thereof. The epitaxial wafer comprises a GaAs substrate, an N-type layer, a multi-quantum well active layer and a P-type layer which are sequentially arranged from bottom to top, the multi-quantum well active layer comprises a plurality of AlGaInP quantum well layers and quantum barrier layers which are alternately arranged, a hole injection layer is inserted between at least part of quantum well structures, and the hole injection layer is composed of a first N-type doped sub-layer, a P-type doped sub-layer and a second N-type doped sub-layer which are connected in sequence; the materials of the three sub-layers are (Al < x > Ga < 1-x >) < 0.5 > In < 0.5 > P (x is greater than or equal to 0.5 and less than or equal to 0.9), and the doping concentration is in gradient distribution along the thickness direction. By introducing the N-P-N structure hole injection layer, the hole injection efficiency is improved, electron leakage and Mg diffusion are inhibited, and the luminous efficiency of the red light Micro LED is remarkably improved.

The invention discloses a butt-joint epitaxial growth ridge waveguide laser chip and a manufacturing method thereof, and belongs to the technical field of lasers, and the manufacturing method comprises the following steps: manufacturing a ridge waveguide structure on an epitaxial wafer subjected to butt-joint growth, coating a layer of photoresist adhesive and two layers of photoresist on the ridge waveguide structure, forming a window at a convex ridge of the overlay ridge waveguide structure, and forming the butt-joint epitaxial growth ridge waveguide laser chip. The window covers an area above the passive area and a part of the active area, exposing and developing the epitaxial wafer in the window, removing a part of photoresist, etching and removing the residual photoresist in the window to expose the ohmic contact layer, corroding and removing the ohmic contact layer in the window, and removing all the photoresist on the surface of the epitaxial wafer. The length of the ohmic contact layer is controlled through double-layer adhesive photoetching and wet etching, and the ohmic contact layer above the active region is further etched, so that diffusion of current to the passive waveguide direction is effectively inhibited, the threshold current of the chip is reduced, the heating value of the passive waveguide region is reduced, and the reliability of the chip is improved.

The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and relates to the technical field of semiconductors. The light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a non-doped GaN layer, an N-type GaN layer, an electron dredging layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer which are stacked on the substrate in sequence, the electron dredging layer comprises a first sub-layer, a second sub-layer, a third sub-layer and a fourth sub-layer which are sequentially stacked, the first sub-layer is a Si3N4 layer, the second sub-layer comprises an AlGaN layer, a first InGaN layer and a first GaN layer which are periodically and alternately stacked, the third sub-layer comprises a second GaN layer and a second InGaN layer which are periodically and alternately stacked, and the fourth sub-layer is a Si3N4 layer. And the fourth sub-layer comprises an AlInGaN layer, a third InGaN layer and a third GaN layer which are periodically and alternately stacked. According to the invention, while the electronic expansibility is improved, excessive electrons are prevented from entering the multi-quantum well layer to generate electron overflow.

The invention provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a gallium nitride epitaxial wafer; the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially deposited on the upper surface of the gallium nitride epitaxial wafer, a grid electrode is arranged in the second dielectric layer, and a first source electrode field plate is arranged between the second dielectric layer and the third dielectric layer; the first drain electrode is deposited at one end of the upper surface of the gallium nitride epitaxial wafer, and the second drain electrode is arranged on the upper surface of the first drain electrode; the first source is deposited on the upper surface of one end, far away from the first drain, of the gallium nitride epitaxial wafer, and the second source is arranged on the upper surface of the first source; the second source field plate is deposited on the upper surface of the third dielectric layer; and the passivation layer is deposited on the upper surface of the third dielectric layer, and the lower surface of the passivation layer is in contact with the upper surfaces of the second source electrode field, the second drain electrode and the second source electrode. According to the invention, the breakdown voltage effect can be effectively improved, and the purpose of realizing a plurality of field plates without adding extra process levels can be achieved.

The invention provides a preparation method and a preparation device of a silicon carbide epitaxial wafer. The preparation method comprises the following steps: providing a substrate, and placing the substrate in an epitaxial reaction cavity; the substrate is heated, the distance between the substrate and a heating heat source is controlled to be H mm, and the reaction temperature in the epitaxial reaction cavity is T DEG C; introducing carrier gas, a growth source and a doping source, and preparing an epitaxial layer on the surface of the substrate to obtain a silicon carbide epitaxial wafer; wherein the distance H mm and the reaction temperature T DEG C meet the condition that (T-1500) / H is larger than or equal to 5.5 and smaller than or equal to 7. By controlling the distance between the substrate and a heating heat source, the airflow and the temperature field on the surface of the substrate are adjusted, the temperature difference between the center and the edge of the wafer is reduced, and the triangular defects on the surface of the wafer are reduced; meanwhile, the distance between the substrate and the heating heat source is matched with the temperature in the epitaxial reaction cavity, the growth rate of the epitaxial layer can be ensured, triangular defects are reduced, meanwhile, step defects are avoided, and therefore the overall quality of the epitaxial wafer is improved.

The invention discloses a manufacturing method of a Micro LED matrix headlamp, and belongs to the technical field of semiconductor processing technologies. Eutectic bonding is carried out on a device of a sapphire / silicon substrate GaN epitaxial wafer-ITO film-metal layer and a silicon-based CMOS-metal layer structure, then a Mesa table top of a periodic island-shaped structure is manufactured, an LED light-emitting surface is manufactured after a SiO2 layer is grown, then a retaining wall structure is manufactured on the periphery of the LED light-emitting surface, finally, a mixture of fluorescent powder and silica gel is integrally molded on the surface of the device, and the LED light-emitting surface is manufactured. And finally, the manufacturing of the Micro LED matrix headlamp is completed. In a traditional matrix headlamp, light between adjacent pixels can be laterally conducted through a fluorescent powder adhesive layer, so that when the headlamp is used, especially when two vehicles meet face to face, the corresponding pixels cannot be closed in a targeted mode, and therefore the safety problem is caused. In addition, lateral conduction may affect light extraction, thereby losing light efficiency. The problems are solved by manufacturing the retaining wall structure.

The invention provides a preparation method of a GaN HEMT (High Electron Mobility Transistor) device and the GaN HEMT device. The preparation method comprises the following steps: forming a substrate of an SIC material of a second doping type; forming a single SIC epitaxial wafer of the first doping type growing along the C axis; forming an electric field stop layer of a first doping type on the front surface of the SIC epitaxial wafer; wherein the doping concentration of the electric field stop layer is greater than that of the substrate; forming a stripping layer at a position below the electric field stop layer in the SIC epitaxial wafer; wherein the part, located between the electric field stop layer and the stripping layer, in the SIC epitaxial wafer serves as an electric field pressure bearing layer; bonding the front surface of the electric field stop layer and the front surface of the substrate together; stripping is carried out at the stripping layer; the electric field stop layer is arranged on the substrate, and the electric field pressure bearing layer is arranged on the electric field stop layer. According to the GaN HEMT device and the manufacturing method thereof, the technical problem caused by relatively high cost of a traditional GaN HEMT device is solved.