1687 results about "Epiwafer" patented technology

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the technical field of semiconductors. The light-emitting diode epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, a low-temperature stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer and a P-type semiconductor layer. The multi-quantum well light-emitting layer comprises a first sub-layer, a second sub-layer, a third sub-layer and a fourth sub-layer which are stacked in sequence, and each of the first sub-layer, the second sub-layer, the third sub-layer and the fourth sub-layer comprises an InGaN quantum well layer and a GaN quantum barrier layer which are periodically and alternately stacked; an electron injection layer is inserted into at least one of the GaN quantum barrier layer of the first sub-layer, the GaN quantum barrier layer of the second sub-layer and the GaN quantum barrier layer of the third sub-layer; and a hole injection layer is inserted into the GaN quantum barrier layer of the fourth sub-layer. By implementing the invention, the electron hole matching degree of the multi-quantum well light-emitting layer can be improved, so that the luminous efficiency of the light-emitting diode is improved.

A method of preparing a silicon-on-insulator structure includes forming an epitaxial silicon layer on a front surface of a single crystal silicon donor substrate, forming a dielectric layer on the epitaxial silicon layer to thereby form an epitaxial donor structure including the single crystal silicon donor substrate, the epitaxial silicon layer, and the dielectric layer, bonding the dielectric layer of the epitaxial donor structure to a front surface of a handle structure, the handle structure including a single crystal semiconductor handle substrate, to thereby form a bonded structure including the handle structure, the dielectric layer, the epitaxial silicon layer, and the single crystal silicon donor substrate, and removing the single crystal silicon donor substrate and a portion of the epitaxial silicon layer from the bonded structure to thereby form the silicon-on-insulator structure including the handle structure, the dielectric layer, and a silicon device layer.

The invention relates to the field of semiconductor optoelectronic device manufacturing, in particular to an LED epitaxial wafer growing method capable of reducing warping. Comprising the following steps of: growing a nucleating layer on a substrate at low temperature by adopting an MOCVD (Metal Organic Chemical Vapor Deposition) process, and annealing to form a three-dimensional island-shaped structure to release stress; growing an AlGaN / GaN superlattice or gradient layer as a gradient buffer layer, and adjusting lattice constants layer by layer; a heavily doped or co-doped layer is inserted before growth of n-GaN, and thermal stress is pre-compensated by using local pressure stress; and finally, continuously growing a device layer and carrying out in-situ heat treatment to obtain the LED epitaxial wafer. The method effectively counteracts the macroscopic tensile stress caused by the difference of thermal expansion coefficients in the cooling process, and greatly improves the integrity of the epitaxial wafer.

The invention relates to the technical field of photoelectricity, and discloses a full-spectrum LED epitaxial wafer, a preparation method thereof and an LED chip, the epitaxial wafer comprises a substrate, and the substrate is sequentially provided with a buffer layer, an N-type GaN layer, a multispectral light-emitting well layer and a P-type GaN layer; the multispectral light-emitting well layer comprises a first light-emitting well layer, a second light-emitting well layer and a third light-emitting well layer which are stacked in sequence, the first light-emitting well layer comprises a plurality of groups of InxGa (1-x) N quantum well layers, AlaGa (1-a) N interface layers and first GaN quantum barrier layers which are stacked in sequence, the second light-emitting well layer comprises a plurality of groups of InyGa (1-y) N quantum well layers, AlbGa (1-b) N interface layers and second GaN quantum barrier layers which are stacked in sequence, and the third light-emitting well layer comprises a plurality of groups of InzGa (1-z) N quantum well layers, AlcGa (1-c) N interface layers and third GaN quantum barrier layers which are stacked in sequence. According to the full-spectrum LED epitaxial wafer provided by the invention, the luminous efficiency and the color rendering index of a full-spectrum chip can be improved.

The invention belongs to the technical field of image enhancement, and particularly relates to an image enhancement method for VCSEL (Vertical Cavity Surface Emitting Laser) epitaxial wafer detection, which comprises the following steps of: analyzing local and global gray information and structure tensor characteristics of pixel points, and calculating a defect saliency value of each pixel point to quantify the possibility of the pixel point as a defect; interference of a stripe structure in an epitaxial wafer image is weakened; a weighted histogram is constructed based on the defect saliency value, so that the defect pixel occupies a higher weight in the histogram; and determining an optimal segmentation threshold value by searching an energy median point of the weighted histogram, and finally performing BBHE enhancement on the image by using the segmentation threshold value. According to the method, the contrast ratio of the tiny defects can be remarkably improved, a high-quality image is provided for subsequent epitaxial wafer detection, and the detection accuracy is improved.

The invention provides an epitaxial growth process for improving doping uniformity of n-type doped silicon carbide, and relates to the technical field of semiconductors. The method is based on a chemical vapor deposition growth technology; 11 to 20 gt; the silicon carbide epitaxial growth is carried out by taking silicon carbide with a 4-degree silicon surface in the direction as a substrate, taking trichlorosilane (TCS) and ethylene (C2H4) as growth sources and taking ammonia gas (NH3) as a doping source. Ammonia gas is adopted as an n-type dopant, the decomposition efficiency of the n-type dopant is close to 100% at the temperature of 700 DEG C or above, and the energy of N-H bond breakage of ammonia gas molecules is 390 KJ / mo which is far lower than 946 KJ / mo needed by N-N bond breakage of nitrogen molecules. Therefore, compared with a traditional doping source such as nitrogen, the ammonia gas has higher doping efficiency, residues of excessive nitrogen-containing precursors in the reaction chamber can be reduced, the memory effect is reduced, and thus more excellent in-chip uniformity and stable inter-chip repeatability of the epitaxial wafer are obtained. The selection range of the doping source is widened, the accurate control of the doping concentration is realized, and the stability of the doping concentration in the continuous growth process is improved.

The invention belongs to the technical field of image processing, and particularly relates to a VCSEL epitaxial wafer thickness uniformity detection method comprising the following steps: obtaining a thickness map and a yield map of a VCSEL epitaxial wafer after space alignment; obtaining the global background thickness of each position in the thickness map; calculating the fluctuation standard deviation of the thickness deviation in the neighborhood of each position; obtaining a neighborhood abnormal score and a neighborhood failure rate, and obtaining a neighborhood reference parameter; calculating a problem attribution risk index according to the product of the neighborhood anomaly score and the neighborhood failure rate of each position, the neighborhood reference parameter and the Pearson's correlation coefficient and the relative deviation and correlation weighting relation; and inferring an abnormal mode type according to the problem attribution risk index, and generating an attribution report. According to the invention, the problem that the correlation attribution capability of the thickness and the yield of the VCSEL epitaxial wafer in the prior art is lacked is solved.

The invention relates to the technical field of data processing, in particular to a real-time data monitoring and early warning method for the growth process of a VCSEL epitaxial wafer, which comprises the following steps: acquiring the refractive index of a material used by the epitaxial wafer at the current moment in the growth process of the VCSEL epitaxial wafer by using MOCVD (Metal Organic Chemical Vapor Deposition) equipment; determining the growth rate of the epitaxial wafer at the current moment; determining the mutation degree of the growth rate of the epitaxial wafer at the current moment; determining the correction mutation degree of the growth rate of the epitaxial wafer at the current moment; determining an early warning threshold value at the current moment; and monitoring and early warning of real-time data in the growth process of the VCSEL epitaxial wafer are realized according to the corrected mutation degree and the early warning threshold value. According to the method, accurate inversion of the growth rate and intelligent identification of mutation are realized, abnormal and normal process changes are effectively distinguished, the early warning threshold is adaptively adjusted, the false alarm rate is reduced, and the accuracy and practicability of VCSEL epitaxial growth monitoring are improved.

The invention discloses a homogeneous pn junction terminal gallium oxide Schottky barrier diode and a preparation method thereof. The problems that gallium oxide p-type doping is difficult, and heterojunction electric leakage is high and voltage resistance is low are solved. The semiconductor device comprises a cathode, an n-Ga2O3 substrate and an n-Ga2O3 epitaxial layer from bottom to top, ion implantation regions are arranged at the left end and the right end of the upper surface of the n-Ga2O3 epitaxial layer, and the upper surface of the n-Ga2O3 epitaxial layer is covered with an anode; the ion implantation region is subjected to annealing treatment to form a p-type Ga2O3 region, and the p-type Ga2O3 region and the n-Ga2O3 epitaxial layer form a homogeneous pn junction terminal, so that the gallium oxide Schottky barrier diode with high voltage resistance and low electric leakage is realized. The preparation method comprises the steps of cleaning an epitaxial wafer, photoetching to form a region to be implanted with ions, carrying out ion implantation, cleaning, carrying out rapid thermal annealing to form p-Ga2O3, and preparing a cathode and an anode. According to the invention, N / P ions are injected, annealing treatment is carried out, a gallium-oxygen-nitrogen-phosphorus compound with a p-type characteristic is generated in the n-Ga2O3 epitaxial layer, and the homogeneous pn junction terminal gallium oxide Schottky barrier diode is realized. The method can be used in high-voltage and high-power fields such as power grids and high-speed rails

The invention provides an epitaxial wafer edge morphology compensation type wafer double-sided polishing device and method, and belongs to the technical field of semiconductor wafer ultra-precision machining. The polishing main machine comprises an upper fixed disc, a lower fixed disc and a wafer driving mechanism; the pressure loading system is used for applying adjustable pressure to the fixed disc; the polishing solution supply system is used for conveying a flow-adjustable polishing solution to the processing interface; the central control unit is in communication connection with the two systems and executes edge morphology compensation control logic, specifically, the machining pressure is adjusted in a segmented mode, and the flow of the polishing solution and the pressure are subjected to coupling change. According to the method, the atomic level flatness of the wafer surface is ensured, the edge morphology is accurately controlled, the edge thickening of the epitaxial layer is perfectly counteracted, and the photoetching yield of high-end chip manufacturing is remarkably improved.

The invention relates to the technical field of LEDs, in particular to a quaternary yellow-green LED epitaxial wafer and a preparation method thereof. The quaternary yellow-green LED epitaxial wafer sequentially comprises a GaAs substrate, a GaAs buffer layer, an N-type gradient doped waveguide layer, a single quantum well active layer, a P-type gradient doped waveguide layer, a P-type self-absorption layer, a P-type transition layer and a P-type periodic current expansion layer from bottom to top. Through the design that the N / P type gradient doped waveguide layer is combined with the single quantum well active layer, the P type self-absorption layer and the P type GaP / GaAsP periodic current expansion layer, and the MOCVD technology is adopted for growth, the obtained low-brightness and high-reliability quaternary yellow-green LED epitaxial wafer structure has the advantages of being high in antistatic performance, excellent in aging performance, good in surface flatness and uniformity, high in light emitting efficiency and the like. The method has the characteristics of simple process, low production cost and raw material cost and the like, is used for replacing two-component and three-component LEDs grown by an LPE technology, and has better reliability and application prospect.

The invention discloses a Micro-LED epitaxial wafer and a preparation method thereof, a multi-quantum well light-emitting layer of the Micro-LED epitaxial wafer comprises a first sub-layer, a second sub-layer and a third sub-layer which are stacked in sequence, and each of the first sub-layer, the second sub-layer and the third sub-layer comprises a pre-well protection layer, an InGaN quantum well layer, a post-well protection layer and a quantum barrier layer which are periodically and alternately stacked; the In component proportion of the InGaN quantum well layer in the first sub-layer and the third sub-layer is smaller than the In component proportion of the InGaN quantum well layer in the second sub-layer; the well front protection layer comprises a first InGaN well front protection layer, an AlGaN well front protection layer and a second InGaN well front protection layer which are stacked in sequence, and the well rear protection layer comprises an InGaN well rear protection layer, an AlGaN well rear protection layer and a GaN well rear protection layer which are stacked in sequence. According to the invention, the light-emitting brightness of the Micro-LED can be improved.

The invention discloses a red light Micro light emitting diode epitaxial wafer and a preparation method thereof. The epitaxial wafer comprises a GaAs substrate, an N-type layer, a multi-quantum well active layer and a P-type layer which are sequentially arranged from bottom to top, the multi-quantum well active layer comprises a plurality of AlGaInP quantum well layers and quantum barrier layers which are alternately arranged, a hole injection layer is inserted between at least part of quantum well structures, and the hole injection layer is composed of a first N-type doped sub-layer, a P-type doped sub-layer and a second N-type doped sub-layer which are connected in sequence; the materials of the three sub-layers are (Al < x > Ga < 1-x >) < 0.5 > In < 0.5 > P (x is greater than or equal to 0.5 and less than or equal to 0.9), and the doping concentration is in gradient distribution along the thickness direction. By introducing the N-P-N structure hole injection layer, the hole injection efficiency is improved, electron leakage and Mg diffusion are inhibited, and the luminous efficiency of the red light Micro LED is remarkably improved.

The invention discloses a butt-joint epitaxial growth ridge waveguide laser chip and a manufacturing method thereof, and belongs to the technical field of lasers, and the manufacturing method comprises the following steps: manufacturing a ridge waveguide structure on an epitaxial wafer subjected to butt-joint growth, coating a layer of photoresist adhesive and two layers of photoresist on the ridge waveguide structure, forming a window at a convex ridge of the overlay ridge waveguide structure, and forming the butt-joint epitaxial growth ridge waveguide laser chip. The window covers an area above the passive area and a part of the active area, exposing and developing the epitaxial wafer in the window, removing a part of photoresist, etching and removing the residual photoresist in the window to expose the ohmic contact layer, corroding and removing the ohmic contact layer in the window, and removing all the photoresist on the surface of the epitaxial wafer. The length of the ohmic contact layer is controlled through double-layer adhesive photoetching and wet etching, and the ohmic contact layer above the active region is further etched, so that diffusion of current to the passive waveguide direction is effectively inhibited, the threshold current of the chip is reduced, the heating value of the passive waveguide region is reduced, and the reliability of the chip is improved.

The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and relates to the technical field of semiconductors. The light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a non-doped GaN layer, an N-type GaN layer, an electron dredging layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer which are stacked on the substrate in sequence, the electron dredging layer comprises a first sub-layer, a second sub-layer, a third sub-layer and a fourth sub-layer which are sequentially stacked, the first sub-layer is a Si3N4 layer, the second sub-layer comprises an AlGaN layer, a first InGaN layer and a first GaN layer which are periodically and alternately stacked, the third sub-layer comprises a second GaN layer and a second InGaN layer which are periodically and alternately stacked, and the fourth sub-layer is a Si3N4 layer. And the fourth sub-layer comprises an AlInGaN layer, a third InGaN layer and a third GaN layer which are periodically and alternately stacked. According to the invention, while the electronic expansibility is improved, excessive electrons are prevented from entering the multi-quantum well layer to generate electron overflow.

The invention provides a preparation method and a preparation device of a silicon carbide epitaxial wafer. The preparation method comprises the following steps: providing a substrate, and placing the substrate in an epitaxial reaction cavity; the substrate is heated, the distance between the substrate and a heating heat source is controlled to be H mm, and the reaction temperature in the epitaxial reaction cavity is T DEG C; introducing carrier gas, a growth source and a doping source, and preparing an epitaxial layer on the surface of the substrate to obtain a silicon carbide epitaxial wafer; wherein the distance H mm and the reaction temperature T DEG C meet the condition that (T-1500) / H is larger than or equal to 5.5 and smaller than or equal to 7. By controlling the distance between the substrate and a heating heat source, the airflow and the temperature field on the surface of the substrate are adjusted, the temperature difference between the center and the edge of the wafer is reduced, and the triangular defects on the surface of the wafer are reduced; meanwhile, the distance between the substrate and the heating heat source is matched with the temperature in the epitaxial reaction cavity, the growth rate of the epitaxial layer can be ensured, triangular defects are reduced, meanwhile, step defects are avoided, and therefore the overall quality of the epitaxial wafer is improved.

A beam laser diode takes a silicon-based nitride epitaxial wafer as a carrier and comprises a silicon substrate layer, an aluminum nitride layer, a u-type gallium nitride layer, an n-type gallium nitride layer, a quantum well layer, a p-type gallium nitride layer and a SiO2 layer which are sequentially arranged from bottom to top, the p-type electrode is arranged on the p-type gallium nitride layer, and the n-type electrode is arranged on the edge of the n-type gallium nitride layer. A nitride material on a silicon substrate is used for preparing a micro-beam stress sensitive area LD by utilizing photoetching and ICP (Inductively Coupled Plasma) etching processes for emitting light, and after electrification, the laser LD is obtained in the stress sensitive area of the beam. Under the power-on condition, before and after acceleration loading, due to the fact that quantum limits the stark effect, the frequency wavelength of laser changes, and the magnitude of the acceleration can be sensed through difference frequency.

The invention relates to the technical field of photoelectron manufacturing, and particularly discloses a flip LED chip and a preparation method thereof. The preparation method comprises the steps of providing an epitaxial wafer; forming a transparent conductive layer; etching to form an etching pit; forming a first passivation protection layer; forming a first photoresist layer; etching to form a groove for exposing the transparent conductive layer, and forming an evaporation hole; the width of the top of the evaporation hole is smaller than that of the groove; a reflecting layer and a connecting layer are sequentially evaporated in the evaporation hole, and a first angle is formed between the metal beam and the epitaxial wafer during evaporation; a protective layer is evaporated in the evaporation hole, during evaporation, a second angle is formed between the metal beam and the epitaxial wafer, and the second angle is smaller than the first angle; removing the fourth photoresist layer; forming a second passivation protection layer, and etching to form a hole; and forming a first electrode and a second electrode. According to the invention, the first passivation layer and the protection layer are compounded to form good wrapping of the reflection layer, metal migration of the reflection layer is greatly reduced, and reliability is improved.

The invention relates to the technical field of solar cell structures, in particular to a flexible multi-junction solar cell and a manufacturing method thereof. The flexible multi-junction solar cell comprises a PI film, a bonding metal layer, a back metal layer, an ohmic contact metal layer, a DBR reflecting layer, an epitaxial layer structure, an antireflection film and an N electrode. According to the flexible multi-junction solar cell, the GaAs substrate is firstly used, the sapphire substrate is used in the middle, the PI film is finally used as the final substrate, the mode of overturning the epitaxial wafer twice is adopted, the process is simple, and the problems that the consumption of precious metal is large due to multiple times of metal bonding, and the performance of the epitaxial wafer is affected due to high temperature of the evaporation and thermal stripping film process can be solved; germanium materials are saved, and cost is low; the PI film is used as the cell substrate, the weight is light, the mechanical strength is high, the cell substrate can be bent, and the design requirement of a solar cell array on a spacecraft can be met.

The invention belongs to the technical field of semiconductor device performance testing, and particularly relates to a VCSEL epitaxial wafer resistivity distribution measuring method and system, and the method comprises the steps: constructing a three-dimensional discretization model representing an epitaxial wafer and an unknown parameter vector containing the vertical resistivity, the top transverse resistivity and the substrate leakage junction nonlinear resistance; a physical response function is defined, the vector is iterated through a discrete point fitting algorithm, so that the total residual error between the analog voltage difference output by the function and the actually measured voltage value under the cross-order-of-magnitude current is minimum, and the real vertical resistivity is extracted from the optimal parameter vector; and obtaining the vertical resistivity of each point on the two-dimensional test point grid so as to generate a distribution diagram and carry out anomaly detection. According to the invention, the problem of measurement distortion caused by the leakage defect of the substrate is solved, and the measurement accuracy of the vertical resistivity is improved.

An objective of the present invention is to provide a SiC epitaxial wafer with a large diameter, a low triangular defect density, and high carrier concentration uniformity. According to the present invention, a SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer. The SiC substrate has a diameter of 195 mm or more. The SiC epitaxial layer has a triangular defect density of 0.2 pieces / cm2 or less and a carrier concentration variation of 20% or less.

The invention provides an epitaxial wafer of a high-luminous-efficiency infrared light-emitting diode and a manufacturing method of the epitaxial wafer. The epitaxial wafer comprises a GaAs substrate, an N-type semiconductor structure, a quantum well active region and a P-type semiconductor structure, wherein the N-type semiconductor structure, the quantum well active region and the P-type semiconductor structure are formed on the substrate. The N-type semiconductor structure comprises an N-type AlGaAs stacking layer, diethyl tellurium (DETe) and disilane (Si2H6) are adopted for co-doping, the N-type semiconductor structure is designed to be of a superlattice structure, and the doping concentration in the vertical direction is periodically alternated from high to low; and a doping concentration gradient is arranged at a position close to the quantum well region, so that the tellurium doping concentration is gradually increased. Through the design, the content of carbon impurities in the material and the non-radiative recombination probability are reduced, a better current expansion effect and quantum well stress release are achieved, and the luminous efficiency and performance of an infrared LED are greatly improved.

The invention provides a GaN-based LED epitaxial wafer and a preparation method thereof, and the method comprises the following steps: S1, providing a substrate, and placing the substrate on a graphite disc of an MOCVD reaction chamber; s2, carrying out heat treatment on the substrate; s3, growing a buffer layer on the substrate after heat treatment; s4, sequentially growing an unintentional doping layer and an N-type GaN layer on the buffer layer; s5, growing a multi-quantum well light-emitting layer on the N-type GaN layer; s6, growing a P-type electron blocking layer on the multi-quantum well light-emitting layer; step S7, growing a P-type GaN layer on the P-type electron barrier layer; and S8, after growing the P-type GaN layer, adjusting the temperature of the reaction chamber to 20-30 DEG C to obtain the GaN-based LED epitaxial wafer. The GaN-based LED epitaxial wafer obtained by the method has fewer surface particles and higher surface quality.

The invention discloses a high-luminous-efficiency LED chip and a preparation method thereof, and relates to the field of semiconductor photoelectric devices. The preparation method comprises the steps of providing an epitaxial wafer; the device comprises a substrate, a first semiconductor layer, an active layer and a second semiconductor layer which are stacked in sequence; forming a transparent conductive layer on the epitaxial wafer; etching to form an exposed region exposing the first semiconductor layer; forming a first electrode and a second electrode; wherein the first electrode is formed on the first semiconductor layer in the exposed area, and the second electrode is formed on the second semiconductor layer; taking silicon and copper as target materials, and sputtering to form a first composite film; annealing the first composite film in an oxygen-containing atmosphere at 550-700 DEG C to obtain a second composite film; forming a silicon oxide film on the second composite film; holes are formed in the second composite film and the silicon oxide film in the areas where the first electrode and the second electrode are located, so that the first electrode and the second electrode are at least partially exposed. According to the invention, the light extraction efficiency and reliability of the LED chip can be improved.

The embodiment of the invention provides an epitaxial wafer, a radio frequency device, a terminal radio frequency module and terminal equipment. The epitaxial wafer comprises a silicon substrate layer and an epitaxial layer which are stacked, wherein the epitaxial layer comprises a nucleating layer stacked on the surface of the silicon substrate layer; and an air gap is arranged at the interface of the silicon substrate layer and the nucleating layer. Based on the special structure and parameter design at the interface of the silicon substrate layer and the nucleating layer in the epitaxial wafer, the epitaxial wafer can be used for providing a radio frequency device with lower radio frequency loss.

The invention discloses a method for growing a low-surface-defect epitaxial wafer on a heavily-doped silicon substrate and the epitaxial wafer, and belongs to the field of semiconductor material preparation. The method comprises the following steps: carrying out rapid heat treatment on a heavily doped silicon substrate of which the resistivity is not greater than 1.15 m omega.cm in an inert atmosphere at the treatment temperature of 1000-1500 DEG C and the heating / cooling rate of 10-120 DEG C / s, and keeping the high temperature for 30-120 seconds; then HCl gas phase polishing is carried out at the temperature of 650-1250 DEG C, and mixed gas of HCl and hydrogen is introduced to remove a surface silicon layer by 50-150 nm; and finally growing an epitaxial layer. And the substrate can be subjected to particle detection and screening, and only the substrate with the specific pattern defect is subjected to the treatment. According to the method, through the synergistic effect of RTP and HCl polishing, in-vivo defect repairing and surface finishing are achieved, the number of LPDs, larger than or equal to 55 nm, on the surface of the epitaxial wafer is stably reduced to 10 or below, and the quality of the epitaxial wafer is remarkably improved.

The invention provides a surface-emitting gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof, and relates to the technical field of laser chips, the surface-emitting gallium nitride VCSEL laser chip comprises a substrate, a low-temperature nucleating layer, a high-temperature recovery layer, a stress regulation type nano mask composite defect blocking layer, an n-type nitride DBR reflector, an active region, a polarization enhanced tunnel junction and the like, the defect blocking layer adopts an in-situ silicon nitride nano-porous mask layer to be matched with an aluminum gallium nitride / gallium nitride stress compensation superlattice layer, through pulse type lateral epitaxial overgrowth annihilation penetrating dislocation, and the n-type nitride DBR reflector adopts an AlInN / GaN lattice matching material system to be combined with a hydrogen etching interruption modification technology, so that thick film growth with zero cracks and high reflectivity is realized; a polarization enhanced tunneling junction is used at the top to replace ITO, and the hole tunneling probability is enhanced by piezoelectric polarization in InGaN, so that efficient current injection with low working voltage and no absorption loss is realized, the dislocation density and the device voltage are remarkably reduced, and the yield of an epitaxial wafer and the photoelectric conversion efficiency are improved.

The invention relates to a method for controlling BMD of a heavily boron-doped substrate and a lightly boron-doped epitaxial wafer through RTP, which belongs to the technical field of silicon wafer processing, and comprises the following operation steps of: 1, drawing a single crystal by adopting a Czochralski method, and doping Bo metal during crystal drawing; and 2, slicing, grinding and thinning, polishing, cleaning and epitaxy processes are carried out. Step 3, dividing the silicon wafers after completion into three groups A, B and C for annealing treatment; and meanwhile, a group of reference silicon wafers without RTP annealing treatment are manufactured. And 4, carrying out low-temperature heat treatment, wherein the low-temperature treatment is used for promoting nucleation of oxygen precipitation. And 5, performing high-temperature heat treatment which is used for promoting the growth of an oxygen precipitation nucleation center in the silicon wafer body so as to form high-density oxygen precipitation and induced defects thereof in the silicon wafer body. The method improves the yield of silicon wafers, greatly shortens the time consumed in the annealing process in the manufacturing of an integrated circuit, meets the actual requirement for low temperature in the manufacturing process of the integrated circuit, reduces the technological process, and saves the cost.

The present invention provides a light-emitting diode epitaxial wafer and a method for fabricating the same. The light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a three-dimensional nucleation layer, an undoped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially deposited on the substrate. The three-dimensional nucleation layer comprises a stacked first and second three-dimensional nucleation sublayers, the thickness of the first three-dimensional nucleation sublayer being less than that of the second three-dimensional nucleation sublayer, both being MgGaN layers, and the growth temperature of the second three-dimensional nucleation sublayer being 10 to 100°C higher than that of the first three-dimensional nucleation sublayer. This light-emitting diode epitaxial wafer can increase the density of V-pits, improve carrier injection efficiency, and enhance the optoelectronic performance of the light-emitting diode.

The invention provides a preparation method of an LED chip structure and the LED chip structure. The preparation method comprises the following steps: providing an LED epitaxial wafer; pixel isolation is carried out on the LED epitaxial layer; the top surface of the electrode leading-out structure is higher than the first semiconductor layer; the bottom surface is in contact with an electrode leading-out position of the pixel unit; bonding a first temporary substrate on the electrode lead-out structure; stripping the substrate; based on the LED chip unit area, the LED epitaxial layer and the first temporary substrate are cut into a plurality of separated LED chip units; providing a second temporary substrate, wherein the material of the second temporary substrate is the same as that of the driving substrate; the LED chip unit is bonded to the second temporary substrate; the first temporary substrate is removed. According to the technical scheme, Die to wafer is realized, wafer to wafer bonding is carried out, the two substrates are made of the same material, and offset caused by thermal expansion difference in the bonding process is avoided; and moreover, the waste of Die is reduced, and the performance is improved.