164 results about "Epiwafer" patented technology

A method of fabricating a high-quality GaN HEMT power semiconductor epitaxial wafer includes forming a nucleation region on a growth substrate, and forming a three-dimensional nitride structure region (3DNS region), a stress release region, a buffer region, a channel region, and a barrier region on the nucleation region. The 3DNS region is formed at one or more of the following locations: between the nucleation region and the stress release region, between individual regions within the stress release region, between the stress release region and the buffer region, between the buffer region and the channel region, and between the barrier region and a pGaN region formed thereon. The 3DNS region is formed of a nitride material having a bandgap that is less than a bandgap of an underlying region.

This invention discloses a light-emitting diode (LED) epitaxial wafer and its fabrication method. The LED epitaxial wafer includes a substrate and a buffer layer, an N-type GaN layer, a stress relief layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate. The stress relief layer includes a Si-doped GaN layer, a Si-doped porous GaN layer, a GaN leveling layer, and an InGaN / GaN superlattice layer sequentially stacked on the N-type GaN layer. The LED fabricated by this invention can reduce the stress and defect density of the epitaxial layer material, improve the quality of the multiple quantum well layer, and enhance the radiative recombination efficiency in the multiple quantum well layer, thereby improving the luminous efficiency of the LED.

This invention relates to an epitaxial wafer structure and its fabrication method. The epitaxial wafer structure includes: a silicon substrate layer; a nucleation layer disposed on the silicon substrate layer, wherein the nucleation layer includes an aluminum nitride layer; a buffer layer disposed on the nucleation layer, wherein the buffer layer includes an indium-doped aluminum gallium nitride layer; a gallium nitride channel layer disposed on the buffer layer; and an aluminum gallium nitride barrier layer disposed above the gallium nitride channel layer. This embodiment, by doping the buffer layer with indium, prevents substrate loss in the epitaxial wafer structure, reduces defects in the epitaxial layer, and improves the quality of the epitaxial wafer structure.

The present disclosure provides an engineered epitaxial wafer of an ultra-thin GaN HEMT by wafer bonding and a manufacturing method thereof. According to an embodiment of the present invention, there is provided an engineered epitaxial wafer of an ultra-thin GaN HEMT by wafer bonding, comprising: a support substrate; an electrically insulating thin film region disposed on the support substrate; a buffer region disposed on the electrically insulating thin film region and containing Al(x)Ga(1-x)N (0≤x<1) doped with undoped carbon (C) and iron (Fe); a channel region disposed on the buffer region and containing Al(y)Ga(1-y)N (0≤y≤1); and a barrier region disposed on the channel region and containing Al(z)Ga(1-z)N (0<z<1) or In(w)Al(1-w)N (0<w<1).

This invention provides a nitride LED epitaxial wafer, its fabrication method, and its application. The nitride LED epitaxial wafer includes a substrate, a composite buffer layer, a nitride buffer layer, a first nitride semiconductor layer, a nitride light-emitting layer, and a second nitride semiconductor layer stacked together. The composite buffer layer comprises n sets of stacked composite buffer sublayers. The first to (n-1)th sets of composite buffer sublayers respectively include a modulation sublayer, a first capping sublayer, a composite structure sublayer, and a second capping sublayer stacked together. The nth set of composite buffer sublayers includes a modulation sublayer, a first capping sublayer, and a composite structure sublayer stacked together, where n ≥ 2. The composite structure sublayer has a nanostructured pattern. By employing the solution provided by this invention, the problems of dislocations or defects caused by lattice constant and thermal mismatch can be overcome, enabling the development of multifunctional buffer technology.

The invention provides a hole activation method of p-type nitride, which comprises the following steps: heating an object to be activated to an annealing temperature for annealing by using heating equipment, the object to be activated comprising the p-type nitride or an epitaxial wafer comprising the p-type nitride; and in the annealing process, applying an electric field to the to-be-activated object by applying voltage, and controlling positively charged H ions in the to-be-activated object to move out of a p-type layer of the to-be-activated object in an accelerated manner. According to the method, an electric field is added in the annealing process to accelerate movement of H elements in a p-type layer and escape from an epitaxial wafer, so that the hole concentration of p-type nitride is increased.

The application discloses a growth method for improving pit defects of a silicon carbide epitaxial wafer, and comprises the following steps: cleaning a silicon carbide substrate and placing the substrate in an epitaxial reaction chamber, introducing hydrogen, and performing high-temperature annealing treatment; increasing the hydrogen flow and the reaction chamber temperature, and performing hydrogen etching; reducing or maintaining the reaction chamber temperature, introducing a carbon source and a silicon source, and growing a buffer layer on the substrate surface; maintaining the gas introduction, increasing the reaction chamber temperature, and growing a gradient layer on the buffer layer; reducing the reaction chamber temperature, simultaneously opening a center gas source and an edge gas source, and growing a base epitaxial layer on the gradient layer; maintaining the reaction chamber temperature, adjusting the edge gas source flow to form a gradient flow, and growing a flat epitaxial layer on the base epitaxial layer. Through the substrate pretreatment-low rate epitaxy-high rate flat epitaxy, combined with the gradient process filling process, the application realizes the step-by-step filling and surface flattening of the pit defects, and effectively reduces the number of Pit defects and the epitaxial thickness uniformity.

This application discloses a Si-based GaN epitaxial wafer, a semiconductor device, a method for manufacturing the Si-based GaN epitaxial wafer, and a method for manufacturing the semiconductor device, belonging to the field of semiconductor epitaxial growth. The Si-based GaN epitaxial wafer includes: a Si substrate; an AlN nucleation layer located on the Si substrate; and a buffer layer located on the AlN nucleation layer, wherein the buffer layer includes at least Al... x Y 1‑x N sublayer and Al y Y 1‑y N sublayer, Al x Y 1‑x The N-sublayer is located near the epitaxial wafer growth direction, Al y Y 1‑y The N sublayer is located on the far side of the growth direction, and y <x,Al y Y 1‑y The lattice constant of the N sublayer is greater than that of GaN; GaN insertion layer; GaN channel layer; HEMT functional layer; The Si-based GaN epitaxial wafer disclosed in this application can provide stronger voltage withstand performance with a thinner buffer layer thickness.

The application belongs to InGaAs infrared focal plane detector, and provides a preparation method of a new type of InGaAs short-wave infrared detector. After growing P electrode, N electrode, P type metal and N type metal to form ohmic contact, growing connecting layer metal, thinning and polishing InP substrate to form a flat mirror surface, corresponding photoetching on a readout circuit wafer, growing lower electrode metal and indium column, and then carrying out metal stripping; InP epitaxial wafer PDA and readout circuit are uniformly glued, protected, and diced to form independent single; PDA and readout circuit are inversely interconnected to form an infrared detector, and secondary polishing treatment and growth of anti-reflection coating are carried out. The indium column is grown at the end of the readout circuit, and one-step photoetching can be completed. The PDA chip end can reduce the growth of the lower electrode, the growth of the indium column, and the growth of the corresponding passivation layer and the opening of the passivation layer. The process steps are reduced, the probability of defects is reduced, the production cost is reduced, and the final yield of the product is further improved.

This invention provides a method for fabricating LED epitaxial wafers and a Micro-LED. The method involves fabricating a multi-quantum-well layer with a periodic stacked structure of InGaN / InN / AlGaN / GaN layers. The InGaN layer acts as a potential well layer, allowing electrons and holes to recombine and participate in light emission. The ultra-thin design improves polarization and reduces QCSE (Quantum Conversion Efficiency). Simultaneously, the ultra-thin design also reduces indium segregation caused by high In content. The InN layer enhances effective In incorporation, and sufficient NH3 further reacts with precipitated In atoms to form InN, resulting in effective incorporation. This improves the In content while maintaining crystal quality. Furthermore, the AlGaN layer acts as a high barrier layer, effectively confining electrons, while the GaN layer provides hole-rich channels, thereby improving luminous efficiency.

This disclosure provides a method, system, and epitaxial wafer for improving particulate contamination of silicon wafers during epitaxy. The method includes: selecting at least one test silicon wafer from a batch of silicon wafers to be processed, and determining a target power range to be applied to the epitaxial furnace based on the test results of the test silicon wafer; adjusting the effective power applied to the epitaxial furnace to the target power range before the silicon wafer to be processed is fed into the epitaxial chamber of the epitaxial furnace, so that the temperature inside the epitaxial chamber is within a target temperature range; maintaining the effective power of the epitaxial furnace within the target power range until the silicon wafer to be processed enters the epitaxial chamber, thereby using the target temperature range to suppress thermal deformation of the silicon wafer to be processed; and growing an epitaxial layer on the surface of the silicon wafer to be processed after it enters the epitaxial chamber. This disclosure can effectively reduce particulate contamination of the silicon wafer to be processed during epitaxy.

This invention discloses a method for removing a double-layer positive photoresist for preparing metal bumps: S1, cleaning the epitaxial wafer; S2, spin-coating a first-type positive photoresist as the bottom layer onto the epitaxial wafer; S3, soft baking to cure the first-type positive photoresist; S4, spin-coating a second-type positive photoresist as the top layer onto the first-type positive photoresist; S5, soft baking to cure the second-type positive photoresist; S6, exposure using a photolithography machine to expose the double-layer photoresist; S7, post-baking; S8, development using an alkaline developer to develop the double-layer photoresist; S9, metal deposition using a metal deposition apparatus; S10, removing the double-layer photoresist using a photoresist stripping solution; S11, preparing metal bumps on the surface of the epitaxial wafer. This invention achieves a lift-off process using a double-layer positive photoresist, solving the problem of difficult preparation of small-sized metal bumps in Micro-LED micro-display devices, and enabling the preparation of metal bumps with small spacing and high thickness.

This invention relates to an LED chip assembly and its fabrication method. The method includes: providing an epitaxial assembly; depositing a plurality of metal electrodes on a functional layer; patterning the functional layer to form a plurality of LED epitaxial structures; depositing a passivation layer on the epitaxial wafer, such that the passivation layer at least covers the metal electrodes on the LED epitaxial structures; etching the passivation layer to expose a driving substrate; forming a fill layer on the driving substrate after etching the passivation layer; forming a protective layer on the fill layer; creating openings in the protective layer on the LED epitaxial structures to expose the metal electrodes; and depositing a common electrode metal layer on the driving substrate with exposed metal electrodes. This application, by simultaneously etching grooves around the core region during Mesa etching and metal etching, transfers areas of uneven resist application to locations away from the core region, resulting in more uniform PV thinning and trench filling processes.

A method for manufacturing a silicon epitaxial wafer comprising a phosphorus-doped silicon wafer and an epitaxial layer provided on a surface of the silicon wafer, wherein the method comprises: forming (S2) an oxide layer on a back side of the silicon wafer cut (S1) from a single-crystal ingot produced by a Czochralski process; removing (S3) the oxide layer present on an outer circumference of the silicon wafer; argon annealing (S4), wherein the silicon wafer is subjected to heat treatment in an argon gas atmosphere after removal of the oxide layer; and forming the epitaxial layer on the surface of the silicon wafer after argon annealing, wherein the formation of the epitaxial layer comprises: pre-baking (S5), wherein the silicon wafer is subjected to heat treatment in a gas atmosphere comprising hydrogen and hydrogen chloride to etch an outer layer of the silicon wafer;and growth (S6) of the epitaxial layer on the surface of the silicon wafer after pre-baking, wherein during argon annealing (S4) clusters of phosphorus and oxygen present on an outer layer of the silicon wafer are dissolved in a solid solution, and during pre-baking (S5) a thickness of the outer layer of the silicon wafer removed by etching is made smaller than a thickness of the outer layer where the clusters are dissolved in the solid solution during argon annealing.;

The present disclosure provides a graphite carrier disc, and relates to the technical field of semiconductors. The graphite carrier disc comprises a graphite cover disc, a bearing surface of the graphite cover disc has a plurality of first grooves, side walls of the first grooves have a plurality of convex structures, and the plurality of convex structures are distributed along a circumferential direction of the first grooves. During growth of an epitaxial wafer, part of the carrier gas flows into a gap region between the side walls of the first grooves and a planetary disc. The plurality of convex structures on the side walls of the first grooves make the carrier gas flowing into the gap region more likely to form a turbulent carrier gas field, the turbulent carrier gas field makes it difficult for by-products of a side reaction to accumulate in the gap region, avoids hindering rotation of the planetary disc, thereby affecting uniformity of the epitaxial wafer, and also prevents part of the accumulated by-products from being thrown onto the epitaxial wafer being grown when the planetary disc rotates, which is conducive to improving crystal quality of the epitaxial wafer.

This disclosure provides a composite dielectric structure, a device having the same, and a fabrication method thereof. The fabrication method includes operations S1-S4. Operation S1: Depositing source and drain ohmic metals at designated locations on the surface of an epitaxial wafer; Operation S2: Using photoresist and electron beam lithography to create the required window for the gate structure; Operation S3: Etching a portion of the epitaxial wafer surface structure corresponding to the window and removing the photoresist to fabricate a gate trench; Operation S4: Growing AlN / SiN within the gate trench. X Composite dielectrics enable the fabrication of devices with composite dielectric structures.

This application provides an epitaxial wafer and a method for preparing the epitaxial wafer. The method includes: preparing a substrate; the substrate includes an upper surface and a lower surface, and a ramp structure is provided at the edge of the upper surface of the substrate, the surface of the ramp structure not exceeding the surface inside the ramp structure; forming a protective layer on the upper surface of the substrate; grinding the protective layer on the substrate until the upper surface of the substrate is exposed, while retaining the protective layer covering the surface of the ramp structure; and fabricating an epitaxial layer on the substrate, wherein the epitaxial layer covers the protective layer on the surface of the ramp structure. The technical solution of this application provides a ramp structure at the edge of the substrate and a protective layer on the surface of the ramp structure, forming active protection, isolating hydrogen gas, reducing the risk of stress concentration, improving the resistance to stress concentration, and reducing the risk of epitaxial wafer breakage.

The application discloses a kind of to be related to the field of semiconductor laser, specifically discloses a kind of grating structure for DFB laser and its preparation method, DFB laser.The preparation method of grating structure includes: S1, grating layer is grown on initial epitaxial wafer;S2, grating layer is etched;S3, load into MOCVD reaction chamber, warm up to T1, keep warm first preset time;PH3 is continuously imported during the process of warming up;PH3 is imported flow rate F1 when keeping warm ends;S4, warm up to T2, PH3 and TMIn are continuously imported during the process of warming up;T2-T1>10 ℃, and PH3 import flow rate is increasing during the process of warming up;S5, cool down to T1, PH3 and TMIn are continuously imported during the process of cooling down;PH3 import flow rate is decreasing during the process of cooling down;S6, periodically repeat steps S4 and S5, until buried layer is obtained, grating structure is obtained.The application can reduce grating remelting, improve the crystal quality of grating structure, reduce interface roughness, so as to improve the side mode suppression ratio, slope efficiency of DFB laser.

A method for producing silicon carbide, SiC, epitaxial wafers in a wafer growth system (1) comprising an outer container, an insulating container arranged inside the outer container, a growth container (2) arranged inside the insulating container, and a heating arrangement arranged outside the outer container to heat an inside of the growth container (2). The method comprises providing a source material (3) of polycrystalline SiC in the growth container (2), providing a substrate (4) of monocrystalline SiC in the growth container (2) substantially parallel to the source material (3), the substrate (4) having a doping concentration of ≤5—1016 cm−3, increasing the temperature in the growth container (2) to a sublimation temperature of the source material (3), maintaining the temperature in the growth container (2) until a conductive layer (6) of monocrystalline SiC having a thickness of ≥10 μm and having a doping concentration of ≥1·1018 cm−3 has grown on the substrate (4). The substrate (4) and the grown conductive layer (6) together define an epitaxial boule. The method further comprises cooling the epitaxial boule to room temperature, and slicing the epitaxial boule, through the substrate (4) in a plane substantially parallel to the grown conductive layer (6), into an excess substrate (8) and an epitaxial wafer comprising a substrate layer (7) having the grown conductive layer (6) thereon.

This invention relates to the field of semiconductor technology, specifically disclosing a gallium oxide epitaxial wafer and its preparation method. The preparation method of the gallium oxide epitaxial wafer includes the following steps: S1, placing a (011)-plane gallium oxide substrate in a reaction chamber, introducing a carrier gas, and then introducing oxygen, chlorine, and hydrogen for a first growth; S2, introducing oxygen and hydrogen chloride for a second growth on the first-grown gallium oxide substrate to obtain a gallium oxide epitaxial wafer; wherein, in S1, the flow rate ratio of oxygen to chlorine is (2~3):1; in S2, the flow rate of oxygen is 200~400 sccm, and the flow rate ratio of oxygen to hydrogen chloride is (5~20):1. This invention optimizes the number of growth cycles and growth conditions during the preparation of the gallium oxide epitaxial wafer, reduces epitaxial defect density, improves epitaxial film quality, and realizes the preparation of high-thickness gallium oxide epitaxial wafers with low surface defects and nanoscale surfaces.

The application discloses a kind of grinding control device and method for epitaxial wafer, belong to production control technical field, the method includes: the thickness point cloud data in historical production data is converted into Zernike coefficient, historical production data is converted into the projection matrix of corresponding equipment health state based on dynamic principal component analysis method;Real-time acquisition multi-modal data in epitaxial wafer production process, and the thickness point cloud data in multi-modal data is converted into Zernike coefficient, multi-modal data is constructed as augmented state vector, the health index of current operating state is calculated in conjunction with augmented state vector and projection matrix;Determine dynamic weight matrix, construct MPC model, apply dynamic weight matrix to the cost function of MPC model, solve MPC model to obtain optimal control sequence in conjunction with prediction model.The method can ensure the uniformity of grinding thickness while reducing the risk of epitaxial wafer defects.

This invention discloses a high-crystal-quality light-emitting diode epitaxial wafer and its fabrication method. The method includes: after depositing a buffer layer on a substrate and before depositing a three-dimensional nucleation layer, performing a high-temperature recrystallization treatment on the buffer layer under low-pressure and high-temperature conditions in an atmosphere containing H2 and NH3 but without N2; subsequently, sequentially depositing a low-temperature three-dimensional nucleation layer, a three-dimensional nucleation transition layer, and a high-temperature three-dimensional nucleation layer in the same N2-free atmosphere; wherein the deposition process of the three-dimensional nucleation transition layer includes a gradual increase in deposition temperature and trimethylgallium flux with increasing deposition time. This invention, through buffer layer recrystallization treatment and the use of a "double-gradient" transition layer process to grow the three-dimensional nucleation layer in an N2-free atmosphere, effectively reduces N vacancies and GaN epitaxial layer defects, improves crystal quality, reduces leakage current, and enhances electrostatic breakdown resistance.

A fixing fixture for testing the performance improvement of LED epitaxial wafer substrate materials, belonging to the LED field, addresses the problem that relying solely on lateral limiting with elastic support rods cannot prevent substrate bounce, tilting, and breakage caused by vibration. Furthermore, conventional fixing methods such as groove-type limiting or bottom vacuum adsorption cannot be optimized, resulting in low pass rates for PSS substrates under conditions such as fully automated microscopic scanning and equipment resonance. This fixing fixture includes a testing device housing. When the scanning detector pushes the device to resonate, a guide rod moves outward along a second guide groove, pushing a push plate to compress the first elastic pad and pass over a baffle. This achieves the effect of further outward movement and release of the buffer plate when the PSS substrate tilts due to resonance, allowing the buffer plate to fall under gravity and re-clamp the substrate in a horizontal position, reducing damage to the buffer plate.

The application discloses an epitaxial method of a very long wave InAs / InAsSb superlattice infrared detector and relates to the technical field of semiconductor devices. The method comprises the following steps: first, preheating a GaSb substrate; then, growing an InAs layer by applying In beam and As beam; then, growing a transition layer by synchronously increasing As and Sb beams at equal increments; then, growing an InAsSb layer by stabilizing As and Sb beams; then, synchronously adjusting As and Sb beams at equal decrements to restore the initial As beam and make the Sb beam zero; and then, repeating the growth process of each layer to form a superlattice structure, and obtaining a target epitaxial wafer through post-processing. The application realizes smooth transition of the InAs layer and the InAsSb layer by precisely controlling the beam and the V / III ratio, obtains a high-quality superlattice structure, guarantees the very long wave response characteristics, and significantly improves the response rate, the detection rate and the working stability of the detector.

The application provides a high-efficiency red light plant lighting LED epitaxial wafer and a manufacturing method, and the structure comprises a GaAs substrate, a GaAs buffer layer, an N-type GaInP cutoff layer, an N-type GaAs ohmic contact layer, an N-type AlGaInP roughening layer, an N-type AlGaInP current spreading layer, an N-type AlInP confinement layer, an N-type AlGaInP waveguide layer, a multi-quantum well layer, a P-type AlGaInP waveguide layer, a P-type AlInP composite doped confinement layer with a three-sublayer structure, a P-type AlGaInP transition layer, a P-type GaP window layer and a P-type GaP ohmic contact layer. The Mg diffusion is effectively inhibited through the composite doped structure, the hole injection efficiency is improved, the device voltage is reduced, the photon efficiency (PPE) and the reliability are significantly improved, and the application is suitable for large-scale industrial application.

This invention provides a trench-type gallium oxide radiation detector and its manufacturing method, belonging to the field of semiconductor device technology. The detector, by designing a rectangular trench structure on the Ga2O3 epitaxial layer of an epitaxial wafer, achieves a more uniform electric field distribution under high reverse bias, effectively avoiding the electric field accumulation effect at the electrode edges and significantly improving the device's breakdown voltage. Simultaneously, the trench structure increases the effective area of ​​the heterojunction, enabling the device to obtain a wider longitudinal depletion region under the same reverse bias, making it easier to achieve full-energy alpha particle deposition, thereby improving the efficiency and energy resolution of radiation detection.

This invention relates to the field of semiconductor manufacturing technology, specifically disclosing a method for processing heavily doped substrate silicon wafers and the epitaxial wafers formed therefrom. This invention adjusts the process steps of traditional processing methods for heavily doped substrate silicon wafers with a composite back-sealing structure of "polysilicon + silicon dioxide". After the polysilicon layer is deposited on the substrate, edge polishing is performed first to remove polysilicon from the chamfered surface, followed by the deposition of the silicon dioxide layer. This process optimization ensures that the junction between the flat back surface and the chamfered surface of the substrate is always completely covered by the silicon dioxide layer, avoiding polysilicon deposition and protrusion formation during epitaxy caused by exposure of monocrystalline silicon. This invention effectively solves problems such as lithography machine vacuum alarms and defocus defects caused by back edge protrusions in existing processes, significantly improving the flatness of the epitaxial wafer and the manufacturing yield for end customers.

The present application relates to a GaN HEMT power semiconductor epitaxial wafer, comprising: a silicon (Si) substrate; a nucleation region formed on the substrate; a stress relief region formed on the nucleation region; a buffer region formed on the stress relief region; a channel region formed on the buffer region; and a barrier region formed on the channel region. Wherein, below the channel region, specifically, at any position between the buffer region and the channel region, inside the buffer region, or between the stress relief region and the buffer region, a rear barrier region is provided. The rear barrier region has a superlattice structure or a multilayer structure in which layers of 2H-Al(Ga)N material and layers of 4H-SiC(N) material are alternately stacked.

The invention relates to a GaN HEMT epitaxial wafer and a manufacturing method thereof. The manufacturing method of the present invention comprises: a step for preparing a Si (111) substrate; a step of forming a Nucleation Region (Nucleation Region) on the Si (111) substrate, and a step of forming a Nucleation Region (Nucleation Region) on the Si (111) substrate; a step of forming a stress regulation region on the nucleating layer region, and a step of forming a stress regulation region on the nucleating layer region; a step of forming a high impedance buffer layer region (Buffer Region) on the stress regulation region; and forming an active layer region including a channel layer and a barrier layer on the buffer layer region. In particular, the step of forming the nucleation layer region is characterized in that a layer comprising aluminum nitride (AlN) and a layer comprising silicon carbide (SiC) or silicon carbonitride (SiCN) are laminated. According to the invention, crystal defects can be minimized and residual stress can be effectively controlled.

This invention relates to a method for preparing low-surface-defect epitaxial wafers on high-COP silicon single-crystal substrates, comprising the following steps: S1, substrate preparation: selecting a high-COP silicon single-crystal substrate; S2, single-sided polishing: polishing the high-COP silicon single-crystal substrate using conventional single-sided polishing equipment to remove the mechanical damage layer on the substrate surface and obtain a preliminarily planarized surface; S3, improved polishing and cleaning process; S4, epitaxial growth of qualified substrate: performing epitaxial growth on the qualified substrate to prepare a low-surface-defect epitaxial wafer. This invention improves the polishing and cleaning processes, thoroughly removing residues within COP voids and suppressing the generation of epitaxial stacking faults, thereby achieving the preparation of high-quality, low-surface-defect epitaxial wafers.