3182 results about "Dislocation" patented technology

The present invention provides a wafer support tool for heat treatment easy in working and capable of realizing reduction in cost without generating damages or slip dislocations that would be otherwise caused by high temperature heat treatment and a heat treatment apparatus. The present invention is directed to a wafer support tool for heat treatment comprising: a plurality of wafer support members for supporting a wafer to be heat treated; and a support member holder for holding the wafer support members, wherein the wafer support members each has a contact portion with the wafer, at least one of the contact portions being movable relative to the support member holder.

Method and devices are disclosed for device manufacture of gallium nitride devices by growing a gallium nitride layer on a silicon substrate using Atomic Layer Deposition (ALD) followed by rapid thermal annealing. Gallium nitride is grown directly on silicon or on a barrier layer of aluminum nitride grown on the silicon substrate. One or both layers are thermally processed by rapid thermal annealing. Preferably the ALD process use a reaction temperature below 550° C. and preferable below 350° C. The rapid thermal annealing step raises the temperature of the coating surface to a temperature ranging from 550 to 1500° C. for less than 12 msec.

The present invention provides a delivery device for self-expanding stent. The delivery device includes pipe head, inner pipe, near end controller, medium pipe, texturing tube, external protection apparatus, at least one locked coil and at least one stayguy. The external protection apparatus is a tearable external protection apparatus or a flexible connects collar hold-down mechanism or a stayguy hold-down mechanism. The present invention has a plenty of following advantages: to locate the stent rotarily, to fix the expanded stent effectively, to reduce the valvular abrasion of artificial cardiac stent, to reduce the abrasion of stayguy, to avoid the dislocation of stayguy and so on.

The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed. The method may further comprises growing a fourth semiconductor layer having the second lattice constant on the second semiconductor layer, wherein the fourth semiconductor layer is relaxed, and growing a strained fifth semiconductor layer having the first semiconductor lattice constant on the fourth semiconductor layer. The method controls the surface roughness of the semiconductor layers. The method also has the unexpected benefit of reducing dislocations in the semiconductor layers.

The surgical device according to the invention comprises both means for per-operative measurement and for memorization of a plurality of positions of a given femoral prosthetic direction and means for per-operative comparison of these positions with the cone of mobility of the prosthesis to be implanted, the position of the axis of revolution of this cone being, during the implantation of the prosthesis, adjustable with respect to the zone of the pelvis where the implantation of an acetabulum of the prosthesis is provided. By using this device, the surgeon can easily and rapidly determine, in the course of the surgical operation, a preferential direction for implanting the prosthetic acetabulum in order to reduce the subsequent risks of dislocations of the implanted prosthesis.

A susceptor for use in a deposition apparatus includes a recess in which a wafer is received, and a stress-reducing bumper disposed along the side of the recess. The stress-reducing bumper is of material having ductility at a relatively high temperature. Therefore, when the wafer contacts the stress-reducing bumper, such as may occur due to thermal expansion of the wafer during processing, the force of the impact on the wafer is minimized by an elastic deformation of the stress-reducing bumper. As a result, defects, such as slip dislocations at the outer peripheral edge of the wafer, are prevented.

Devices, systems and methods are disclosed for repairing soft tissue. The surgical system allows for the creation of tissue repair by grasping, aligning and sewing or fixing tissue. For example, this system may be used for clipping together excessive capsular tissue and reducing the overall capsular volume. The deployment device includes a central grasping mechanism and an outer clip delivery system. The clip embodiments may be single or multi-component (penetration and locking base components) that penetrate tissue layers and deploy or lock to clip the tissue together. An example of the system is used to reduce the joint capsule tissue laxity and reduces the potential for subluxation or dislocation of the joint by either restricting inferior laxity (anterior or posterior) and resolving or eliminating pathologic anterior or posterior translation.

A GaN substrate comprises a GaN single crystal substrate, an AlxGa1-xN intermediate layer (0<x<=1) epitaxially grown on the substrate, and an GaN epitaxial layer grown on the intermediate layer. The intermediate layer is made of AlGaN and this AlGaN grows over the entire surface of the substrate with contaminants thereon and high dislocation regions therein. Thus, the intermediate layer is normally grown on the substrate, and a growth surface of the intermediate layer can be made flat. Since the growth surface is flat, a growth surface of the GaN epitaxial layer epitaxially grown on the intermediate layer is also flat.

A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.

A single crystalline ternary nanostructure having the formula A_xB_yO_z, wherein x ranges from 0.25 to 24, and y ranges from 1.5 to 40, and wherein A and B are independently selected from the group consisting of Ag, Al, As, Au, B, Ba, Br, Ca, Cd, Ce, Cl, Cm, Co, Cr, Cs, Cu, Dy, Er, Eu, F, Fe, Ga, Gd, Ge, Hf, Ho, I, In, Ir, K, La, Li, Lu, Mg, Mn, Mo, Na, Nb, Nd, Ni, Os, P, Pb, Pd, Pr, Pt, Rb, Re, Rh, Ru, S, Sb, Sc, Se, Si, Sm, Sn, Sr, Ta, Tb, Tc, Te, Ti, Ti, Tm, U, V, W, Y, Yb, and Zn, wherein the nanostructure is at least 95% free of defects and/or dislocations.

There are provided a GaN field effect transistor (FET) exhibiting an excellent breakdown voltage owing to the high quality of GaN crystal in a region where the electric lines of force concentrate during operation of the same, and a method of manufacturing the same. The FET has a layer structure formed of a plurality of GaN epitaxial layers. A gate electrode and a source electrode are disposed on the surface of the layer structure, and a drain electrode is disposed on the reverse surface of the same. A region of the layer structure in which the electric lines of force concentrate during operation of the FET has a reduced dislocation density compared with the other regions in the layer structure. The GaN FET is manufactured by forming, on a crystal-growing substrate having a surface formed with a plane pattern of a material other than a GaN-based material in an identical design to a plane pattern of an electrode determining the region in which the electric lines of force concentrate, a plurality of GaN epitaxial layers, one upon another, by using the epitaxial lateral overgrowth technique, thereby forming a layer structure, and then forming operational electrodes on the surface of the layer structure.

A III-nitride optoelectronic device comprising a light emitting diode (LED) or laser diode with a peak emission wavelength longer than 500 nm. The III-nitride device has a dislocation density, originating from interfaces between an indium containing well layer and barrier layers, less than 9×10⁹ cm⁻². The III-nitride device is grown with an interruption time, between growth of the well layer and barrier layers, of more than 1 minute.

A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage. Three different methods to introduce dispersion in the 50 nm closest to the gate are described: (1) introduction of a small gap between the passivation and the gate metal, (2) gradually reducing the thickness of the passivation, and (3) gradually reducing the thickness of the AlGaN cap layer in the region close the gate.

A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.

The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm², it is more than 1.0 μm thick and its C-plane surface dislocation density is less than 10⁶/cm², while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm². More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm², it is more 1.0 μm thick and its surface dislocation density is less than 10⁶/cm². Mono-crystals according to the present invention are suitable for epitaxial growth of nitride semiconductor layers. Due to their good crystalline quality they are suitable for use in opto-electronics for manufacturing opto-electronic semiconductor devices based on nitrides, in particular for manufacturing semiconductor laser diodes and laser devices. The a.m bulk mono-crystals of gallium-containing nitride are crystallized on seed crystals. Various seed crystals may be used. The bulk mono-crystals of gallium-containing nitride are crystallized by a method involving dissolution of a gallium-containing feedstock in a supercritical solvent and crystallization of a gallium nitride on a surface of seed crystal, at temperature higher and/or pressure lower than in the dissolution process.

Large area, uniformly low dislocation density single crystal III-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm², a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm⁻², and a dislocation density standard deviation ratio of less than 25%. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 10² pits/cm² of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.

A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell, the method including: providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a barrier layer over the second subcell to reduce threading dislocations; forming a grading interlayer over the barrier layer, the grading interlayer having a third band gap greater than the second band gap; and forming a third solar subcell over the grading interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell.

A surgical fastener system for acromioclavicular (AC) joint dislocations, includes a first fastener having an elongate body, and an inner pair of openings centered on the long axis of the body. A closed loop stitch passes through the openings, and the length of the stitch corresponds to the depth of a passage defined between the top of a first hole bored through a patient's clavicle, and the bottom of a second hole bored through the coracoid in axial alignment with the first hole. A second fastener has an elongate body arranged to slide under a portion of the loop stitch that protrudes from the top of the hole in the clavicle, after the first fastener is set beneath the coracoid and the stitch is pulled upward through the passage. In an alternate embodiment, the second fastener also has an inner pair of openings for passing and engaging the loop stitch.

Light emitting devices include an active region comprising a plurality of layers and a pit opening region on which the active region is disposed. The pit opening region is configured to expand a size of openings of a plurality of pits to a size sufficient for the plurality of layers of the active region to extend into the pits. In some embodiments, the active region comprises a plurality of quantum wells. The pit opening region may comprise a superlattice structure. The pits may surround their corresponding dislocations and the plurality of layers may extend to the respective dislocations. At least one of the pits of the plurality of pits may originate in a layer disposed between the pit opening layer and a substrate on which the pit opening layer is provided. The active region may be a Group III nitride based active region. Methods of fabricating such devices are also provided.

Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.

Methods, and structures formed thereby, are disclosed for forming laterally grown structures with nanoscale dimensions from nanoscale arrays which can be patterned from nanoscale lithography. The structures and methods disclosed herein have applications with electronic, photonic, molecular electronic, spintronic, microfluidic or nano-mechanical (NEMS) technologies. The spacing between laterally grown structures can be a nanoscale measurement, for example with a spacing distance which can be approximately 1-50 nm, and more particularly can be from approximately 3-5 nm. This spacing is appropriate for integration of molecular electronic devices. The pitch between posts can be less than the average distance characteristic between dislocation defects for example in GaN (ρ=10¹⁰/cm²→d=0.1 μm) resulting an overall reduction in defect density. Large-scale integration of nanoscale devices can be achieved using lithographic equipment that is orders of magnitude less expensive that that used for advanced lithographic techniques, such as electron beam lithography.

In accordance with the invention, there are electron beam inspection systems, electron beam testable semiconductor test structures, and methods for detecting systematic defects, such as, for example contact-to-gate shorts, worm hole leakage paths, holes printing issues, and anomalies in sparse holes and random defects, such as, current leakage paths due to dislocations and pipes during semiconductor processing.

A thermal enhance multi-chips module (MCM) package mainly comprises a first package, a first carrier, a second package, a second carrier, an intermediate substrate and a cap-like heat spreader. The intermediate substrate has an opening. The first carrier and the second carrier are electrically connected to the first package and the second package respectively. The second package is accommodated in the opening and electrically connected to the first package via the first carrier, the second carrier and the intermediate carrier. The cap-like heat spreader has a supporting portion and an alignment portion wherein the supporting portion is connected to the alignment portion to define a cavity. The cavity not only accommodates the first package, the first carrier, the second package, the second carrier and the intermediate substrate but also provides alignment mechanism by the supporting portion and the alignment portion to prevent the dislocation after all the components of the thermal enhance MCM package are connected with each other. Furthermore, the first carrier has a first side and the second carrier has a second side. The first side and the second side both have grounding portions, for example recessed portions and metal layers, for providing a ground shielding of the first package and the second package against the outside. In addition, the grounding portions also provide thermal paths to increase the ability of the heat dissipation. Besides, a method for manufacturing the thermal enhance MCM package is provided.

A high efficiency textured-surface light emitting diode comprises a flip-chipped stack of Al_xIn_yGa_1-x-yN layers, where 0≦x, y, x+y≦1. Each layer has a high crystalline quality, with a dislocation density below about 10⁵ cm⁻². The backside of the stack, exposed by removal of the original substrate, has a textured surface for improved light extraction.

A substrate is made of SiC. A plurality of AlxGa1-xN patterns (0<=x<=1) is formed on a surface of the substrate and dispersively distributed in an in-plane of the substrate. An AlyGa1-yN buffer layer (0<=y<=1) covers the surface of the substrate and the AlxGa1-xN patterns. A laser structure is formed on the AlyGa1-yN buffer layer. Since the AlGaN buffer layer is grown by using the AlGaN patterns as seed crystals, a dislocation density of a predetermined region in the AlGaN buffer layer can be lowered. The characteristics of a laser structure can be improved by forming the laser structure above the region having a low dislocation density. Since the AlGaN pattern has electric conductivity, the device resistance can be suppressed from being increased.

GaN single crystal substrates are produced by slicing a GaN single crystal ingot in the planes parallel to the growing direction. Penetration dislocations which have been generated in the growing direction extend mainly in the bulk of the GaN substrate. A few of the threading dislocations appear on the surface of the GaN substrate. GaN substrates of low-dislocation density are obtained.

The present invention relates to a fabrication method of nitride-based semiconductors and a nitride-based semiconductor fabricated thereby. In the fabrication method of the invention, a self-organizing metal layer is formed on a sapphire substrate. The sapphire substrate having the self-organizing metal layer is heated so that self-organizing metal coalesces into nanoscale clusters to irregularly expose an upper surface of the sapphire substrate. Exposed portions of the sapphire substrate is plasma etched using the self-organized metal clusters as a mask to form a nanoscale uneven structure on the sapphire substrate. A resultant structure is wet etched to remove the self-organized metal clusters. The nanoscale uneven structure formed on the sapphire substrate decreases the stress and resultant dislocation between the sapphire substrate and a nitride-based semiconductor layer as well as increases the quantum efficiency between the same.

Lateral epitaxial overgrowth (LEO) of non-polar a-plane gallium nitride (GaN) films by hydride vapor phase epitaxy (HVPE) results in significantly reduced defect density.

A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.