48487 results about "Heat treated" patented technology

A shape-memory device manufactured from shape memory material includes multiple activation temperatures. The multiple activation temperatures arise from either the heat treatment of the device during manufacturing, or by combining different elements with different activation temperatures. To manufacture a shape-memory device with multiple activation temperatures, it is formed into a first shape. A first portion of the shape-memory device is heated to a first temperature, and a second portion of the shape-memory device is heated to a second temperature. The shape-memory device is then worked into a second shape. Accordingly, the first portion has a first transition temperature, and the second portion has a second transition temperature. In use, the shape-memory device is placed into a desired position. Energy is applied such that the first portion, second portion, or both portions are transformed.

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.

Low dielectric constant films with improved elastic modulus. The method of making such coatings involves providing a porous network coating produced from a resin containing at least 2 Si-H groups and plasma curing the coating to convert the coating into porous silica. Plasma curing of the network coating yields a coating with improved modulus, but with a higher dielectric constant. The costing is plasma cured for between about 15 and about 120 seconds at a temperature less than or about 350° C. The plasma cured coating can optionally be annealed. Rapid thermal processing (RTP) of the plasma cured coating reduces the dielectric constant of the coating while maintaining an improved elastic modulus as compared to the plasma cured porous network coating. The annealing temperature is typically loss than or about 475° C., and the annealing time is typically no more than or about 180 seconds. The annealed, plasma cured coating has a dielectric constant in the range of from about 1.1 to about 2.4 and an improved elastic modulus.

When a two-division structure heat treatment jig for semiconductor substrate that includes a silicon first jig that comes into direct contact with a semiconductor substrate that is heat treated and supports the semiconductor substrate, and a second jig (holder) that holds the first jig and is mounted on a heat treatment boat is adopted as a heat treatment boat of a vertical heat treatment furnace, the stress concentrated during the heat treatment on a particular portion of the semiconductor substrate can be reduced; in the case of a semiconductor substrate large in the tare stress and having an outer shape of 300 mm being heat treated, or even in the case of the heat treatment being carried out under very high temperature conditions, the slips can be suppressed from occurring. The present invention can be widely applied as a stable heat treatment method of semiconductor substrates.

Embodiments of the invention provide a novel apparatus and methods for forming a conformal doped layer on the surface of a substrate. A substrate is provided to a process chamber, and a layer of dopant source material is deposited by plasma deposition, atomic layer deposition, or plasma-assisted atomic layer deposition. The substrate is then subjected to thermal processing to activate and diffuse dopants into the substrate surface.

A method for forming a conformal, homogeneous dielectric film includes: forming a conformal dielectric film in trenches and / or holes of a substrate by cyclic deposition using a gas containing a silicon and a carbon, nitrogen, halogen, hydrogen, and / or oxygen, in the absence of a porogen gas; and heat-treating the conformal dielectric film and continuing the heat-treatment beyond a point where substantially all unwanted carbons are removed from the film and further continuing the heat-treatment to render substantially homogeneous film properties of a portion of the film deposited on side walls of the trenches and / or holes and a portion of the film deposited on top and bottom surfaces of the trenches and / or holes.

The present invention provides a wafer support tool for heat treatment easy in working and capable of realizing reduction in cost without generating damages or slip dislocations that would be otherwise caused by high temperature heat treatment and a heat treatment apparatus. The present invention is directed to a wafer support tool for heat treatment comprising: a plurality of wafer support members for supporting a wafer to be heat treated; and a support member holder for holding the wafer support members, wherein the wafer support members each has a contact portion with the wafer, at least one of the contact portions being movable relative to the support member holder.

A substrate heat treatment apparatus for heat-treating a substrate includes a bake plate having projections on an upper surface thereof, a seal unit disposed peripherally of the upper surface of the bake plate for closing a lateral area of a minute space formed between a lower surface of the substrate and the upper surface of the bake plate when the substrate is placed on the bake plate, and exhaust bores for exhausting gas from the minute space. The substrate placed on the bake plate is heat-treated in a state of the gas exhausted from the minute space through the exhaust bores.

This invention provides a heat treatment jig for semiconductor silicon substrates, which, in respective heat treatment of hydrogen annealing or argon annealing, can handle enlargement of the diameter of wafers to be treated and can also prevent slipping and dislocations that occur as a result of the stress caused by the weight of the wafer itself or the deflection of the heat treatment jig itself.

A heat treatment jig for supporting silicon semiconductor substrates by contacting, being loaded onto a heat treatment boat in a vertical heat treatment furnace, comprises; the configuration of a ring or a disc structure with the wall thickness between 1.5 and 6.0 mm; the deflection displacement of 100 μm or less at contact region in loaded condition; the outer diameter which is 65% or more of the diameter of said substrate; and the surface roughness (Ra) of between 1.0 and 100 μm at the contact region. The use of said jig enables to effectively retard the slip generation and to avoid the growth hindrance of thermally oxidized film at the back surface of said substrate, diminishing the surface steps causing the defocus in photolithography step in device fabrication process, thereby enabling to maintain high quality of silicon semiconductor substrates and to substantially enhance the device yield.

Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-demensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.

A baffled liner cover supported at the top of a liner surrounding a wafer support tower for semiconductor thermal processing. The cover may present a continuous horizontal surface for preventing particles from falling within the liner but present horizontal extending gas passageways in a baffle assembly to allow the flow of processing gas through the cover. In one embodiment, the baffle assembly includes a cup-shaped member disposed in a central aperture of a top plate having an open top, a continuous bottom, horizontal holes through the sides, and a flange around sides defining a convolute annular passage. Alternatively, the planar top plate may included slanted holes therethrough or vertical holes occupying a small fraction of the surface area. The liner and cover may be composed of quartz, silicon carbide, or preferably silicon.

A thermal processing apparatus including: a cylindrical processing vessel; a support unit to be loaded into and unloaded from the vessel; and a heating furnace surrounding an outer periphery of the vessel, with a cooling space therebetween. The furnace is connected to a cooling-gas introduction unit, including a gas introduction passage to which a blowing fan is connected, for introducing a cooling gas into the cooling space during a temperature lowering operation after a thermal process. The furnace is connected to a cooling-gas discharge unit, including a heat exchanger, a suction fan, and a gas discharge passage, for discharging the cooling gas of a raised temperature from the cooling space. Connected to the gas discharge passage at a position upstream of the heat exchanger is a temperature-lowering gas introduction unit for introducing a temperature-lowering gas to the cooling gas of a raised temperature so as to lower its temperature.