276 results about "Field-effect transistor" patented technology

This document describes an electro-optic photonic memory device comprising a micro-ring resonator, and at least one ferroelectric field effect transistor (FeFET) that is disposed along a partial circumference of a raised ring waveguide of the micro-ring resonator. The FeFET comprises a ferroelectric gate stack and a heterojunction channel layer.

A semiconductor structure is presented including a plurality of field effect transistor (FET) devices, each FET device having a different gate threshold voltage, first spacers disposed on sidewalls of each FET device, second spacers disposed over and in direct contact with the first spacers, the second spacers having a width greater than a width of the first spacers, and a gate contact directly contacting an FET device of the plurality of FET devices, where only an upper portion of the gate contact directly contacts third spacers on opposed ends thereof. The second spacers can have a bi-layer configuration and the gate contact wraps around a top portion of the FET device in direct contact with the gate contact.

This invention provides a radio frequency (RF) switch circuit and module. The RF switch circuit includes a first resistor and stacked switching units. Each stacked switching unit comprises multiple stages of stacked field-effect transistor (FET) circuits connected in series. Each stage of the stacked FET circuit includes a FET, a second resistor, and a bootstrap unit, which includes one or two bootstrap circuits. The bootstrap unit in each stage of the stacked FET circuit is used to raise the gate voltage of the corresponding FET during electrostatic discharge (ESD) to assist in turning on the FET and allowing the ESD current to be discharged through the path formed by the FET. This invention can prevent gate oxide breakdown or thermal damage caused by localized overheating of the FET acting as a switch during an ESD event in the RF switch circuit, thereby improving the stability of the RF switch circuit.

The present application relates to a metal oxide semiconductor field effect transistor and a manufacturing method therefor. The metal oxide semiconductor field effect transistor comprises: a source region (142) having a first conductivity type; a drift region (130) having the first conductivity type; a first well region (120) having the first conductivity type, and located below the drift region (130) and connected to the drift region (130); a drain trench structure extending downward from the drift region (130) into the first well region (120), the drain trench structure comprising an insulating dielectric layer (145) located on a sidewall of a first trench, and a conductive material (146) located in the first trench and laterally surrounded by the insulating dielectric layer (145), and at least a portion of the drift region (130) being located between the source region (142) and the drain trench structure; and a gate (152) located on the drift region (130).

This invention provides a common-source common-gate field-effect transistor (CFET) and a semiconductor chip with a shielded gate, comprising multiple parallel-connected transistor structure groups, each including a first transistor structure and a second transistor structure. A first stacked structure is connected to the upper end of a first drain, and both a first oxide layer and a second stacked structure are connected to the upper end of the first stacked structure. A first shielded gate is connected inside the first oxide layer and is connected to the first source. A first gate is connected to the upper end of the first oxide layer, and the first source is connected to the first oxide layer and the second stacked structure. A third stacked structure is connected to the upper end of a second drain, and the second oxide layer and a fourth stacked structure are connected to the upper end of the third stacked structure. A second shielded gate is connected to the interior of the second oxide layer and is connected to the second gate. The second gate is connected to the upper end of the second oxide layer, and the second source is connected to the second oxide layer and the fourth stacked structure.

The application provides an integrated circuit, comprising: a first metal oxide semiconductor field effect transistor (FET), wherein a first effective gate and a second effective gate are arranged in the first FET, and a first redundant gate is arranged between the first effective gate and the second effective gate; the first effective gate, the second effective gate and the first redundant gate surround a first channel; the first effective gate and the second effective gate are connected to a gate end of the first FET; the first channel on both sides of the first effective gate and the first channel on both sides of the second effective gate are respectively connected to a source end and a drain end of the first FET; and the first redundant gate is connected to a redundant potential or is suspended. Through the structure of the redundant gate arranged between the two effective gates, the current density of the GAA tube can be reduced, and the heat dissipation performance of the GAA tube is further improved.

The application discloses a junction field effect transistor. The junction field effect transistor comprises a drain region, a drain terminal coupled to the drain region, an insulating electrode, and an insulating terminal coupled to the insulating electrode. The junction field effect transistor has an active region. The insulating electrode presents a capacitance to the drain terminal, and the capacitance value is between 0.1 nanofarad per square centimeter of the active region and 10 nanofarad per square centimeter of a lateral range of the active region. The junction field effect transistor reduces the cell size, has better shielding performance, and makes the device have stronger voltage resistance.

This invention discloses an automatically wake-up driving circuit for a test pen, comprising a detection module, a trigger module, a locking module, and a sampling module. The detection module includes a transistor powered by a battery via a field-effect transistor, connected to the main pen. Based on the connection state of the main pen, it outputs a detection signal. An operational amplifier acquires the detection signal and supplies it to a comparator for comparison. A Schottky diode outputs an external trigger signal. The trigger module conducts based on the external trigger signal, supplying operating current to the sampling module. The locking module maintains the conduction of the trigger module according to a power-locking signal. The sampling module samples and outputs an indicator signal. Thus, in standby mode, monitoring is maintained with minimal power consumption. When contact between the main pen and the auxiliary pen is detected, the circuit automatically conducts, generating a power-locking signal to maintain power supply. When the main pen and the auxiliary pen are disconnected, the circuit returns to standby mode. Therefore, manual power on / off is unnecessary; circuit testing can be triggered at any time, and the circuit returns to standby mode when idle, significantly reducing overall device power consumption and effectively extending device lifespan.

Methods and systems for depositing vanadium and / or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and / or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and / or indium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures. The vanadium and / or indium layers can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

Provided are a test element group (TEG) device and a cryogenic intrinsic characteristic analysis method for quantitatively assessing impact of a high-k-based passivation layer on an electrical characteristic of a device in a two-dimensional (2D) field effect transistor (FET) structure. Herein, to analyze a FET device that includes a channel of a 2D material and a passivation layer of a high-k material, a first FET device in which the passivation layer is arranged in a first direction with respect to the channel and a second FET device in which the passivation layer is arranged in a second direction different from the first direction with respect to the channel may be prepared. The first and second charge amounts trapped in the passivation layers in the first and second FET devices, respectively, may be compared to assess quantitative impact of the shape of the passivation layer on the FET device.

This invention relates to the field of inverter technology, and particularly to a heterogeneous power device hybrid inverter and its space vector modulation method. The heterogeneous power device hybrid inverter provided in this invention includes a first constant current source, a second constant current source, a main power inverter module, a secondary power inverter module, and a capacitive reactance module. The first constant current source is connected to the main power inverter module to provide current to the main power inverter module. The main power inverter module includes multiple silicon-based insulated-gate bipolar transistors (SBMTs) as main switching transistors, and the main power inverter module is connected to the capacitive reactance module. The second constant current source is connected to the secondary power inverter module to provide current to the secondary power inverter module. The secondary power inverter module includes multiple silicon carbide-based metal-oxide-semiconductor field-effect transistors (MOSFETs) as secondary switching transistors, and the secondary power inverter module is connected to the capacitive reactance module. The heterogeneous power device hybrid inverter and its space vector modulation method provided by this invention can balance high inverter frequency and low switching losses.

The present application provides nanostructure field effect transistor devices and methods of forming the same. A method of forming a semiconductor device includes forming a fin structure protruding above a substrate, wherein the fin structure includes a fin and a layer stack above the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; forming a first dummy gate structure and a second dummy gate structure above the fin structure; forming an opening in the fin structure between the first dummy gate structure and the second dummy gate structure; converting an upper layer of the fin exposed to a bottom of the opening to a seed layer by performing an implantation process; selectively depositing a dielectric layer above the seed layer at the bottom of the opening; and selectively growing a source / drain material on opposing sidewalls of the second semiconductor material exposed by the opening.

The application discloses a double-gate reconfigurable field effect transistor process design kit construction method, and belongs to the field of integrated circuit process design kit expansion, reconfigurable device modeling and physical verification. In view of the fact that existing open source PDK mainly faces traditional CMOS devices and is difficult to support circuit design, layout drawing and post-layout verification of double-gate RFET, the application provides a process design kit construction method for double-gate RFET. The method comprises the following steps: constructing a four-terminal RFET compact model and packaging the four-terminal RFET compact model into a SPICE subcircuit; establishing a schematic symbol, a layout unit and parameter configuration; extending LVS device identification rules to identify four-port RFET devices containing a source, a drain, a control gate and a polarity gate; constructing a parasitic parameter extraction file and integrating the parasitic parameter extraction file into a layout verification process; and finally, performing post-layout simulation verification on an RFET inverter and reconfigurable NAND and NOR logic. The application realizes a complete design closed loop of double-gate RFET from a model, a schematic, a layout, DRC / LVS, PEX and reverse label simulation.

This application relates to the field of electronic equipment technology, and discloses a method, apparatus, electronic device, and storage medium for protecting a Pogopin. In this apparatus, a first end of a first resistor is connected to a power supply voltage input terminal, and a second end of the first resistor is connected to a first end of a second resistor; a first end of a third resistor is connected to a detection pin of the target Pogopin, and a second end of the third resistor is connected to a second end of the second resistor; the gate of a first field-effect transistor is connected to a control signal input terminal, and its drain is connected to the connection point of the first and second resistors; a voltage detection terminal is connected to the connection point of the second and third resistors; the voltage signal input to the control signal input terminal is defaulted to a high level; a detection control module is used to detect the voltage signal output from the voltage detection terminal, and when its voltage value exceeds a first preset threshold, it determines that the target Pogopin is damp. This allows for timely detection of moisture or water ingress into the connector interface of the electronic device.

The application discloses a dead time control circuit and electronic equipment, and belongs to the technical field of electronics. The dead time control circuit comprises an inductive element, a first field effect tube connected with the inductive element, a second field effect tube connected with the inductive element and the first field effect tube, a detection circuit for detecting a first switching state of the first field effect tube, a second switching state of the second field effect tube and a current flow direction of the inductive element, a logic judgment circuit for outputting an adjustment mode signal of a dead time, a first off time and a second off time according to the first switching state, the second switching state and the current flow direction, an operation circuit for outputting a dead time control signal according to the first off time and the second off time in an adjustment direction indicated by the adjustment mode signal, and a time delay circuit, wherein the dead time control signal is used for adjusting a time delay value of the time delay circuit to adjust the dead time of the first field effect tube and the second field effect tube.

This disclosure relates to the technical field of semiconductors. Through localized design optimization of the structure of existing Schottky-junction MOSFETs, the disclosure proposes a novel field-effect transistor possessing both large on-state current capability and normally-off functionality. The field-effect transistor disclosed herein comprises: an n-type semiconductor layer; a drain electrode; a source electrode; a gate electrode; and a gate insulating film. A Schottky barrier exists between a first portion of the source electrode and the n-type semiconductor layer, while a second portion of the source electrode contacts the n-type semiconductor layer forming an Ohmic contact. The on-state current capability of the field-effect transistor of the disclosure matches or even exceeds that of a pn-junction MOSFET under equivalent conditions.

The embodiment of the application discloses a kind of circuit systems based on cascaded bidirectional gallium nitride, it is applied to integrated circuit manufacturing and production special photoetching machine, etching machine and other semiconductor device special equipment manufacturing field.Circuit system includes the first field effect tube, bidirectional gallium nitride device and second field effect tube connected in series, substrate selection switch between the substrate electrode of connecting bidirectional gallium nitride device and the source of each field effect tube, negative voltage grid drive network for driving each substrate selection switch, and clamping holding network for clamping or keeping the voltage of one end of each substrate selection switch, to inhibit "self-triggering" caused by device body capacitance charging under voltage rate of change (i.e. dv / dt), avoid two substrate selection switches to form straight-through while being turned on simultaneously.Especially suitable for the demand of strategic emerging industry high-performance integrated circuit and semiconductor special equipment manufacturing.

The utility model relates to low voltage difference linear voltage stabilizing circuit field, the utility model discloses a low -cost low voltage difference linear voltage stabilizing protection circuit, include: VCC input, VCC output, field effect transistor Q1, triode Q7, diode D2, voltage stabilizing diode D3, electric capacity C2, resistance R3, R4, R5, R6, VCC input and VCC output are respectively connected with the source electrode and the drain electrode of field effect transistor Q1, and R3 is connected between the grid of field effect transistor Q1 and the collector of triode Q7, and the positive pole and the negative pole of D3 are connected with ground and the base of triode Q7 respectively, and R5 is connected between the emitter of triode Q7 and VCC output, and R6 is connected between the emitter of triode Q7 and ground, and the negative pole of diode D2 is connected with the base of triode Q7, and R4 is connected between the drain of field effect transistor Q1 and the positive pole of diode D2, and one end of electric capacity C2 is connected between resistance R6 and ground, and the other end of electric capacity C2 is connected with VCC output. The utility model has the advantages of low cost and strong anti -interference ability.

According to embodiments of the present invention, a semiconductor device includes a plurality of nanodevices (ND1, ND2) including a plurality of upper transistors and a plurality of lower transistors. The plurality of nanodevices includes upper active regions (135, 140, 145) and lower active regions (120, 125) that are offset from each other across the plurality of upper transistors and the plurality of lower transistors. A first front-side gate cut dielectric pillar (190, 195) is adjacent to and parallel with a first nanodevice of the plurality of nanodevices along an x-axis. A backside surface of the first front-side gate cut dielectric pillar extends a first width along a y-axis. A first backside dielectric filler (240, 245) is in direct contact with the backside surface of the first front-side gate cut dielectric pillar. A frontside surface of the first backside dielectric filler extends a second width along the y-axis. The second width is greater than the first width.

Devices, integrated circuit transistor structures, systems, and techniques are described herein related to gate all around field effect transistor circuits having an n-type transistor integrated with a p-type transistor such that each has stress engineering in the channel material thereof. The nanowires of the p-type transistor are released and surrounded by a sacrificial flowable oxide structure during source and drain material growth to apply compressive stress to the channel material. The n-type transistor source and drain are grown in the presence of a sacrificial lattice matched material to apply tensile stress to the channel material, and the nanowires are subsequently released. After removal of the sacrificial flowable oxide structure, gate structures are coupled to the n-type and p-type transistors.

This utility model discloses a protection circuit, a terminal block, and a cryogenic sensor system. The protection circuit of this application is characterized by comprising a first surge protection module and a second surge protection module; wherein the first surge protection module comprises a first junction field-effect transistor and a first TVS diode connected in series; the second surge protection module comprises a second junction field-effect transistor and a second TVS diode connected in series; the first surge protection module and the second surge protection module are connected in reverse parallel on the same signal line to suppress forward and reverse overshoot voltages on the signal line. The terminal block of this application includes the above-mentioned protection circuit; the cryogenic sensor system of this application includes an input module, multiple cryogenic sensors, and the terminal block. The protection circuit of this application not only reduces leakage current during normal circuit operation but also effectively protects the internal circuitry when the circuit malfunctions.

A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.

A ferroelectric field effect transistor (FeFET), a memory device including the FeFET, and an electronic apparatus including the FeFET are provided. The FeFET includes a gate electrode, a ferroelectric layer provided on the gate electrode, an intermediate conductive layer provided on the ferroelectric layer, a gate insulating layer provided on the intermediate conductive layer, a channel layer provided on the gate insulating layer, and a source electrode and a drain electrode provided on the channel layer. The source electrode and the drain electrode each contact the gate insulating layer.

The utility model discloses a kind of multi-path protection signal control circuit, belong to the technical field of automation equipment protection circuit.The circuit is input by several protection sensor signals, and each signal is connected to N channel MOS field effect transistor through input resistance and load resistance, and MOS tube is connected to triode after cascading, and triode output end connects motor driver I O port, and 24V is simultaneously stabilized as 5V for sensor power supply using 78L05.The utility model solves the problem of insufficient motor controller I O port resources, high cost and low reliability in prior art, can be flexibly configured according to sensor type, reduces cost and assembly difficulty, and improves system reliability.

The application provides a substrate voltage modulation type image sensor pixel unit, namely array, and an operation method. The pixel unit comprises a field effect tube and a triode, the doping type of the substrate of the field effect tube is the same as the doping type of the base of the triode, but is opposite to the doping type of the source and the drain of the field effect tube; the substrate of the field effect tube is connected with the base of the triode, the emitter of the triode is connected with one of the source and the drain of the field effect tube as the source of the image element, the collector of the triode is connected with the other of the source and the drain of the field effect tube as the drain of the image element, and the gate of the field effect tube is connected with an external voltage as the gate of the image element. The image sensor provided by the application can be applied to submicron pixels, has low dark current, low crosstalk, high signal-to-noise ratio, and the size of the image element can be reduced to 9F 2 and other characteristics.

The application discloses a self-powered driving circuit applied to a switching power supply circuit and relates to the technical field of integrated circuits, wherein the output end of a current driving switching circuit is connected with the second end of a Darlington power tube, the first input end and the second input end of the current driving switching circuit, the gate of a first field effect transistor and the gate of a second field effect transistor are all connected with a control chip; the first end of a voltage clamping circuit is connected with the second end of the Darlington power tube, and the second end is connected with the ground through an energy storage circuit; the gate of the first field effect transistor is connected with the control chip, the drain thereof is connected with the third end of the Darlington power tube, and the source thereof is connected with the ground; the drain of the second field effect transistor is connected with the fourth end of the Darlington power tube, and the source thereof is connected with the ground; the base and the collector of a first triode are both connected with the fourth end of the Darlington power tube, and the emitter thereof is connected with the ground through the energy storage circuit. The stability of the transformer output end voltage is improved.

A field effect transistor comprises a gate, an insulating layer, a source, a drain and a channel layer, the insulating layer is on the surface of the gate, the channel layer is on the surface of the insulating layer away from the gate, the source and the drain are arranged on the surface of the channel layer away from the insulating layer; the source and the drain are one-dimensional structures. The application further provides a preparation method of the field effect transistor and a method for measuring the contact resistance of the field effect transistor.

The present disclosure relates to a ferroelectric field effect transistor device. The ferroelectric field effect transistor device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is disposed on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type different from the first semiconductor type. Embodiments of the invention also relate to integrated chips and methods of forming ferroelectric field effect transistor devices.

The utility model provides a kind of high voltage pre-charging circuit and fuel cell system of fuel cell system, the high voltage pre-charging circuit includes the high voltage input terminal V1 for receiving external high voltage power supply, capacitor C2, pre-charging branch, the anode of capacitor C2 is connected with the anode of high voltage input terminal V1, the cathode of capacitor C2 is connected with the cathode of high voltage input terminal V1, capacitor C2 both sides parallel pre-charging branch, pre-charging branch is connected in series with the battery of fuel cell system, pre-charging branch includes inductance L1, diode D2, transformer TR2, field effect transistor FET2 that successively connect in series.The utility model has the beneficial effect that: the high voltage pre-charging circuit of the utility model makes pre-charging process reduce the loss of energy, improves the energy utilization of fuel cell system.

This utility model relates to the field of motor drive circuit technology, and more particularly to a drive circuit for a stepper motor. The stepper motor drive circuit includes a signal preprocessing module and a signal conversion module. The signal preprocessing module includes a transistor, and the signal conversion module includes a field-effect transistor (FET). The transistor amplifies the phase control signal into a boost control signal for the motor, and the FET converts the boost control signal into the drive signal for the stepper motor. This design ensures the drive circuit is simple, versatile, and adaptable to various stepper motors.