2021 results about "Field-effect transistor" patented technology

The invention belongs to the technical field of power devices, and provides a silicon carbide device structure, a preparation method thereof and a chip, a P-type heavily doped region is isolated from a junction field effect transistor region at an adjacent position by a P-type well region, and an N-type heavily doped region is isolated from the junction field effect transistor region at an adjacent position by the P-type well region. The adjacent junction field effect transistor regions are isolated by the P-type well regions, so that a super-junction-like structure is formed, the junction field effect transistor regions can have donor doping with higher doping concentration, corner arrangement is avoided, a depletion region can be completely closed, the on resistance of the device is reduced, and the reliability of the device is improved.

A semiconductor device includes a semiconductor substrate having a mesa structure, a dielectric layer surrounding the mesa structure, and a gate electrode over the dielectric layer. The semiconductor substrate includes a bottom source region, a contact source region, and a sidewall body region in the mesa structure. The semiconductor substrate includes a liner doped region adjoining a frontside surface of the semiconductor substrate and a drain region adjoining a backside surface of the semiconductor substrate. The bottom source region, the contact source region, and the drain region have a first conductivity type, and the sidewall body region and the liner doped region have a second conductivity type opposite to the first conductivity type. A bottom of the gate electrode is higher than a top end of a first portion of the liner doped region in the mesa structure.

In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

The invention provides a switching power supply device comprising a transformer which comprises a primary winding and a secondary winding and is used for converting an input voltage into an output voltage; the primary switching tube is connected with the primary winding and controls the on-off of the primary winding; the rectifying unit is connected with the secondary winding and rectifies the output of the secondary winding, and the rectifying unit comprises a semiconductor field effect transistor; the control unit is connected with the rectification unit and generates a control signal so as to control the switch of the semiconductor field effect transistor through the control signal; the current detection unit detects the output current and generates a current detection signal; the control unit receives the current detection signal and adjusts the control signal according to the current detection signal. According to the device, the COOLMOS with small internal resistance and high switching speed is adopted, the switching loss is reduced, the switching signal is dynamically adjusted by the control unit according to the real-time output current, the rectification conduction loss and the switching noise are reduced, the power supply conversion efficiency is improved, and the electromagnetic interference is reduced.

Techniques are provided to form an integrated circuit having different semiconductor devices with different backside contact structures. Field effect transistors (FETs) each includes semiconductor material extending in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. Different contact structures are formed on the source or drain regions of the n-channel FETs compared to the p-channel FETs. A backside contact structure on an n-channel source or drain region includes a first layer of phosphorous-doped titanium, a second layer that includes scandium, and a third layer that includes a metal, such as molybdenum. A backside contact structure on a p-channel source or drain region may include only a layer of metal, such as molybdenum, or the layer of metal and a layer of boron-doped titanium. The contact structures may be used to provide enhanced ohmic contact.

The invention discloses a P-type tellurium oxide thin film field effect transistor and a preparation method thereof. The transistor is provided with a bottom gate top contact structure. The preparation method comprises the following steps: firstly, cleaning the silicon / silicon dioxide substrate, then depositing a tellurium oxide film as the semiconductor active layer by using a metal mask and an electron beam evaporation method, and finally preparing a layer of nickel with the thickness of about 50nm on the active layer by using the mask to serve as the source electrode and the drain electrode. Compared with a traditional tellurium oxide transistor, the tellurium oxide transistor prepared by the method has the advantages that the carrier mobility and the switching ratio are obviously improved, and the hysteresis effect can be ignored. The electrical performance of the tellurium oxide transistor with the bottom gate top contact structure is improved, and the tellurium oxide transistor has the advantages of being low in cost and simple in process step.

The invention discloses a system for detecting viral nucleic acid on the basis of a CRISPR (clustered regularly spaced short palindromic repeat) technology and an FET (field effect transistor) chip and application of the system, and relates to a method for detecting the viral nucleic acid on the basis of clustered CRISPR (clustered regularly spaced short palindromic repeat) and related proteins (Cas) and a field effect transistor (FET). The CRISPR-FET (clustered regularly interspaced short palindromic repeats-field effect transistor) detection system comprises a non-amplified CRISPR system, a reporter RNA (ribonucleic acid) and gold nanoparticles (AuNPs) connection system, a separation system and a field effect transistor chip detection system. The CRISPR-FET detection method provided by the invention has high sensitivity and high specificity on virus nucleic acid detection, and the lower limit of detection reaches a single copy (100 copies / [mu] L).

A semiconductor device includes: a substrate including active patterns; a device isolation layer disposed between the active patterns; a stacked pattern disposed on the substrate; a power transmission network layer disposed on a first surface of the substrate; a first through via penetrating the stacked pattern; and a second through via disposed between the power transmission network layer and the first through via, wherein the second through via penetrates the active patterns and the device isolation layer.

The invention provides a low-noise amplification circuit, a radio frequency front-end module and an electronic terminal.The low-noise amplification circuit comprises an input matching adjustment circuit, a common-source amplification circuit, a first inductor, an inter-stage feedback circuit, a common-gate amplification circuit, an input and output feedback circuit, an output matching adjustment circuit and an output attenuation circuit; the common-source amplification circuit comprises at least two first signal amplification units; each first signal amplification unit comprises a first field effect transistor; the common-gate amplification circuit comprises at least two second signal amplification units; and each second signal amplification unit comprises a second field effect transistor. According to the low-noise amplification circuit, transconductance nonlinearity of devices under different bias signals can be mutually counteracted, so that the linearity fluctuation of the low-noise amplification circuit at different temperatures is optimized, and the linearity of the low-noise amplification circuit is kept basically not to change along with the temperature change.

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N / P channel properties, provide a simple way to form the N / P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

The invention relates to a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) surge failure real-time discrimination method and system, and the method comprises the steps: 1, collecting SiC MOSFET surge waveform data, and carrying out the multi-scale physical feature extraction, and obtaining a physical frequency band energy feature; 2, performing feature alignment on the physical frequency band energy features to form a standardized feature vector; and 3, constructing a surge failure prediction model, performing temperature compensation on an output result of the surge failure prediction model, and judging a failure state. Current and voltage waveforms in a surge event are captured through a high-speed data acquisition system, key physical frequency band energy features are extracted by adopting an adaptive wavelet packet decomposition technology, a pulse width normalization coding model is constructed to realize feature alignment, and a physical guide degradation path auto-encoder model is designed to perform failure prediction. The method innovatively solves the problem of failure discrimination of surges with different pulse widths, and has the characteristics of high precision and strong real-time performance.

The invention discloses an ultra-wideband circulator based on a periodic modulation topology circuit, and belongs to the technical field of microwave and radio frequency nonreciprocal circuits. The working bandwidth range of the circulator is widened, and non-reciprocal transmission is achieved through non-magnetic materials. A time sequence control unit is respectively connected with a Floquet topology circuit layer, a clock signal driving module, a reset signal driving module and a start signal driving module; the Floquet topology circuit layer is respectively connected with a first coupling port, a second coupling port and a third coupling port; the other ends of the first coupling port, the second coupling port, the third coupling port, the clock signal driving module, the reset signal driving module and the starting signal driving module are respectively grounded; the Floquet topology circuit layer adopts a six-layer parallel network structure, and each layer of network structure comprises a coupling capacitor and three N-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) switches. The advantages of the switched capacitor structure are utilized, and the signal processing capacity which is high in integration level, small in size and capable of breaking through delay-bandwidth limitation is achieved.

The invention relates to the technical field of electronic circuits, in particular to a field effect transistor dynamic threshold voltage measuring method and system. The method comprises the following steps: generating a high-speed pulse signal with preset rise time through a pulse signal generator; applying the high-speed pulse signal to the grid electrode of the field-effect tube to be tested, and collecting the voltage waveform of the grid electrode of the field-effect tube through an oscilloscope, and recording the voltage waveform as a grid electrode voltage waveform; the current probe monitors the current response of the drain electrode of the field effect transistor in real time, the current response is recorded as drain electrode current response, and the sampling rate of the drain electrode current response is synchronous with the sampling rate of the grid voltage waveform. According to the invention, the channel establishment delay is quantified in situ on the electrical characteristic, so that the threshold voltage is redefined by the potential at the completion moment of the channel formation, and the concealment of the transient characteristic caused by direct current slow scanning is eliminated.

A ferroelectric field effect transistor includes a channel layer, a gate electrode facing the channel layer, a ferroelectric layer provided between the channel layer and the gate electrode, an oxygen-deficient layer provided between the channel layer and the ferroelectric layer, a diffusion barrier layer provided between the channel layer and the oxygen-deficient layer and configured to reduce or prevent oxygen exchange between the channel layer and the oxygen-deficient layer, and a source electrode and a drain electrode, electrically connected to the channel layer, wherein the channel layer and the oxygen-deficient layer include an oxide semiconductor material, and a concentration of oxygen vacancies in the oxygen-deficient layer may be greater than a concentration of oxygen vacancies in the channel layer.

A vertical channel oxide semiconductor field effect transistor and a manufacturing method, relating to the technical field of information materials and devices. In the oxide semiconductor field effect transistor, a trench-shaped oxide semiconductor channel layer is used, the trench is then filled with an oxide semiconductor material, and an oxygen vacancy concentration of a material of an oxide semiconductor filling layer is less than an oxygen vacancy concentration of a material of the oxide semiconductor channel layer; and by using an oxide semiconductor having a low carrier concentration as an internal filling material, a threshold regulation capability of the vertical channel oxide semiconductor field effect transistor can be effectively improved, and the impacts of interface damage and unnecessary doping can be avoided, thereby achieving a vertical channel oxide semiconductor field effect transistor of which a threshold can be accurately regulated.

A method is provided that includes providing a substrate having an N-type region for n-type field effect transistors (nFETs) and a P-type region for p-type field effect transistors (pFETs); forming a gate dielectric layer in the N-type region and the P-type region to wrap the vertically stacked channels; performing dipole processing on the first part of the gate dielectric layer in the N-type region, and keeping the second part of the gate dielectric layer in the P-type region unprocessed; depositing a P-type metal layer in the gate dielectric layer of the P-type region and the N-type region; and forming a filling metal layer on the P-type metal layer of the P-type region and the N-type region.

The invention provides an intelligent power module and a power electronic device, which are used for avoiding the problems of reliability and complexity of the existing intelligent power module through an IPM (Intelligent Power Module) which takes a hybrid device consisting of a normally open MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a low-voltage silicon MOSFET as a core power unit. The intelligent power module comprises at least one power unit, and the power unit comprises a normally open MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a low-voltage silicon MOSFET; the drain electrode of the low-voltage silicon MOSFET is electrically connected with the source electrode of the normally open type MOSFET; and the source electrode of the low-voltage silicon MOSFET is electrically connected with the grid electrode of the normally open MOSFET.

The invention discloses a trench separation gate field effect transistor. The trench separation gate field effect transistor comprises a multi-stage step trench structure. The first-stage groove structure comprises a gate dielectric layer formed on the side face of the gate groove, a first dielectric layer on the surface of the bottom and a filled gate conductive material layer. The second-stage groove structure comprises a plurality of source electrode grooves, source dielectric layers and source electrode conductive material layers, wherein the source dielectric layers and the source electrode conductive material layers are formed in the source electrode grooves. First spacer regions are arranged among the source trenches, and the sum of the widths of all the source trenches and the first spacer regions is smaller than the width of the gate trench. A first buried layer and a second buried layer doped with a first conductive type and a second conductive type are formed at the top and the bottom of the first spacer region, and the second buried layer further wraps the bottom corners of the adjacent source trenches on the two sides. The gate conductive material layer is connected to the gate. Each source conductive material layer, the first buried layer and the second buried layer are connected to a source. The invention further discloses a manufacturing method of the trench separation gate field effect transistor. The invention can reduce the electric field intensity at the bottom of the gate trench.

An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor and a second transistor stacked vertically. A conductive via extends vertically from a first source / drain region of the first transistor past the second transistor. The second transistor includes an asymmetric second source / drain region. The asymmetry of the second source / drain region helps ensure that the second source / drain region does not contact the conductive via.

The invention discloses a high-efficiency UPS (Uninterrupted Power Supply) management system for well logging, and belongs to the technical field of power management. The system comprises a rectifier, a charger, a storage battery pack, an inverter, a change-over switch and a management module. The management module comprises an on-line monitoring unit, a power supply controller and a driving circuit, and the on-line monitoring unit collects UPS power supply operation state parameters in real time; the power supply controller receives and processes the parameters, and generates a control instruction according to a preset threshold value; and the driving circuit converts the control instruction into a driving signal and accurately controls the working state of the inverter. Wherein a signal conditioning circuit is arranged between the sensor module and the data acquisition unit and can perform enhancement and noise reduction processing on an analog signal output by the sensor. The driving circuit effectively resists well logging environment interference through cooperative work of an instruction amplifier, a photoelectric coupler and a field effect transistor, stable operation of a UPS power supply system is guaranteed, accurate control over the working state of an inverter is achieved, and it is ensured that stable and reliable electric power supply is provided for well logging equipment.

A hybrid stacked semiconductor device includes a nanosheet stack on a substrate and an all-around gate. The nanosheet stack includes a first stack portion and a second stack portion. The first stack portion includes first channels. The second stack portion is stacked on the first stack portion, and includes second channels. The all-around gate includes a first gate portion that wraps around the first channels and a second gate portion that wraps around the second channels. A first gate extension contacts the first gate portion and the second gate extension contacts the second gate portion. At least one gate contact contacts the first gate extension to establish conductivity with the first gate portion and contacts the second gate extension to establish conductivity with the second gate portion.

A semiconductor structure includes a field effect transistor having a plurality of source / drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source / drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source / drain region of the plurality of source / drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source / drain region to a backside interconnect structure disposed above the backside interlevel dielectric.

An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor having a first semiconductor nanostructure corresponding to a channel region of the first semiconductor nanostructure and a first gate metal surrounding the second semiconductor nanostructure. The CFET includes a transistor including a second semiconductor nanostructure above the first semiconductor nanostructure and a second gate metal surrounding the second semiconductor nanostructure. The CFET includes an isolation structure between the first and second semiconductor nanostructures.

A power inverter is provided. The power inverter includes: first, second and third legs configured to output alternating voltages having different phases. Each the first leg, the second leg, and the third leg includes: a first power metal oxide semiconductor field effect transistor (MOSFET) on a SiC substrate, and connected between a power terminal of direct current voltage and an output terminal configured to output a voltage of a corresponding phase among the first phase, the second phase and the third phase; a second power MOSFET on the SiC substrate, and connected between the output terminal and a ground terminal; and a redundancy circuit including a redundancy power transistor configured to replace the first power MOSFET based on the first power MOSFET failing and replace the second power MOSFET based on the second power MOSFET failing.

The invention discloses a passive multi-stage voltage soft turn-off circuit suitable for SiC MOSFETs. The passive multi-stage voltage soft turn-off circuit comprises a driving main branch, a plurality of voltage reduction branches, a driving resistor, a discharging resistor and a driving power supply circuit. The driving power supply circuit is powered by a positive power supply VCC when the SiC MOSFET is turned on, and is powered by a negative power supply VEE when the SiC MOSFET is turned off. The voltage reduction branches are connected to the two ends of the driving main branch in parallel. The step-down branch comprises a step-down delay unit, a step-down action unit and a step-down unit which are sequentially connected in series; the delay time of each step-down branch is increased in sequence, and the step-down voltage drop is increased in sequence. According to the invention, the voltage level can be conveniently controlled by changing the number of the voltage reduction branches, an additional power supply module does not need to be added, the voltage reduction time can be controlled by the voltage reduction delay branches, the degree of freedom of driving is greatly increased, and the circuit is low in complexity, high in voltage reduction degree of freedom and high in reliability.

A semiconductor structure is presented including a bottom field effect transistor (FET) including a plurality of bottom source / drain (S / D) epi regions, a top FET including a plurality of top S / D epi regions, a bonding dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S / D epi region of the plurality of bottom S / D epi regions of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET electrically connects to back-end-of-line (BEOL) components and the bottom FET electrically connects to a backside power delivery network (BSPDN).

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure for optimizing switching characteristics and a preparation method thereof, and provides a silicon carbide MOSFET device for reducing reverse output capacitance Crss, increasing input capacitance Ciss and increasing output capacitance Coss to improve Crosstalk voltage spike and a preparation method thereof. By introducing the composite gate oxide structure, the high-K material passivation layer and the P + structure at the bottom of the P-WELL into the planar silicon carbide MOSFET device, the reverse output capacitance Crss can be effectively reduced, the input capacitance Ciss can be increased, the output capacitance Coss can be increased, and finally, the Vgs voltage peak in the Crosstalk turn-off process can be effectively improved, and the performance of the device is improved. The breakdown and burnout of the device caused by overhigh voltage in the on-off process of the device are prevented, and the service life of the device is prolonged. Besides, the device structure and the preparation method are simple, and the effect is remarkable, so that high-performance and batch preparation and production can be realized, and the device has huge market potential and wide application prospects.

Provided are a detection circuit and an image generation device capable of accurately generating a detection signal corresponding to a change in a scanning speed. Mirror detection circuit (detection circuit) inputs a voltage generated in a monitoring piezoelectric element for monitoring an operation state of a second scanning part (light deflecting element) to a gate of field effect transistor constituting a source follower circuit, and generates a detection signal corresponding to expansion or contraction of the piezoelectric element from a source voltage of field effect transistor.

A semiconductor device and a logic device formed of the semiconductor device are provided. The semiconductor device includes a first field effect transistor (FET), disposed on a semiconductor substrate, and including vertically separated first channel structures formed as thin sheets each having opposite major planar surfaces facing toward and away from the semiconductor substrate; and a second FET, disposed on the semiconductor substrate and overlapped with the first FET. A conductive type of the second FET is complementary to a conductive type of the first FET. Second channel structures of the second FET are separately arranged along a lateral direction, and formed as thin walls.