4392 results about "Field-effect transistor" patented technology

The invention discloses a big data-driven hydrogen fluoride purification risk entropy assessment and multi-parameter monitoring system, which relates to the technical field of chemical process monitoring, comprises a multi-mode heterogeneous sensor network, and realizes high-precision detection and three-dimensional monitoring by using a nanowire FET (Field Effect Transistor) and the like. The space-time tensor decomposition module extracts features and identifies a causal relationship; the risk entropy manifold learning module evaluates the risk; the self-adaptive twin network monitors the abnormity and simulates and disposes the abnormity; and a knowledge graph-reinforcement learning system decision making subsystem and a plurality of subsystems such as an optical monitoring subsystem and a multi-scale modeling subsystem are also provided, so that whole-process risk management and control are realized. The hydrogen fluoride purification monitoring level is greatly improved, the detection sensitivity and the anomaly detection accuracy are remarkably improved, risk early warning is more timely, decision response is accelerated, the production efficiency is improved, energy consumption is reduced, the system has self-repairing and self-power-supply capabilities, data are safe and traceable, reliable operation of the system is guaranteed, and economic losses and potential safety hazards are reduced.

The invention belongs to the technical field of field effect transistor performance prediction, and particularly relates to a reliability prediction method, device and system for a field effect transistor, and the method comprises the steps: determining the correlation between the time sequence data of environment parameters, electrical parameters and performance parameters in historical operation records and the change of the performance parameters through a correlation analysis method when the time sequence data changes; key performance parameters are screened out, then a virtual operation model of the field effect transistor is constructed before life prediction is conducted through the screened key performance parameters, and historical data are used for conducting validity verification on the virtual operation model; finally, dynamic changes of environment parameters and electrical parameters are simulated through historical data when the successfully verified virtual operation model is utilized, the degradation trend of key performance parameters is recorded, residual life prediction is carried out based on the degradation trend, prediction efficiency is improved, life prediction can more accurately reflect actual working conditions, and the service life prediction efficiency is improved. And the accuracy of residual life prediction is improved.

The invention discloses an online aging state monitoring method and system for a silicon carbide MOSFET, and belongs to the technical field of semiconductor device monitoring, and the method specifically comprises the steps: collecting the working voltage, working current and junction temperature data of the silicon carbide MOSFET in real time, analyzing and processing the data through a data processing unit, and extracting the aging state characteristic parameters of the MOSFET; a dynamic aging state evaluation model fusing multi-source data and time sequence information is adopted to evaluate the aging state of the silicon carbide MOSFET, and a result is output to a display unit; according to the method, the aging state of the silicon carbide MOSFET is monitored, multi-level alarm strategies are set, different levels of alarm signals are triggered according to the aging state, meanwhile, feedback data are collected to optimize the state evaluation model, real-time and accurate monitoring of the aging state of the silicon carbide MOSFET is achieved, and the reliability and stability of a power electronic system are improved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

A semiconductor device is provided. The semiconductor device includes a back-end-of-line (BEOL) layer, a backside power distribution network (BSPDN), a stacked field effect transistor (stacked FET) and a backside contact. The stacked FET is vertically interposed between the BEOL layer and the BSPDN and includes a top FET with top source / drain (S / D) epitaxy and a bottom FET with bottom S / D epitaxy. The stacked FET is characterized as having at least partial vertical alignment of the top FET and the bottom FET. A backside contact electrically connects the BSPDN and the top S / D epitaxy and cuts through the bottom S / D epitaxy with isolation between the backside contact and the bottom S / D epitaxy.

A method of fabricating a field effect transistor (FET) over a substrate that includes: growing a doped p-type semiconductor from a silicon nanosheet of the substrate, the substrate including a layer stack of alternating layers of the silicon nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the layer stack including a trench exposing sidewalls of the layer stack, the doped p-type semiconductor and the sacrificial layer being separated by a dielectric inner spacer; removing the dummy gate; and etching the sacrificial layer selectively to the doped p-type semiconductor, the etching including exposing the substrate to a process gas including a fluorocarbon and a fluorine-containing etch gas in the absence of plasma.

The invention discloses a manufacturing method of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric integration technology capable of eliminating a buffer layer. The manufacturing method comprises the following steps: depositing a back gate electrode and a back gate dielectric on a substrate in sequence; transferring the channel layer to the back gate medium; sequentially forming a buffer layer, a source electrode, a drain electrode, a top gate dielectric layer formed by a high-k dielectric material and a top gate electrode on the channel layer; and annealing treatment is carried out in a vacuum environment, and the buffer layer sublimates, so that Van der Waals interfaces are formed between the channel layer and the top gate dielectric layer and between the channel layer and the source electrode as well as between the channel layer and the drain electrode. According to the high-k gate dielectric integration technology based on the erasable buffer layer, the erasable buffer layer after vacuum annealing is utilized, damage to a two-dimensional material is avoided, a high-quality high-k gate dielectric is deposited, interface regulation and control between a channel layer and a top gate dielectric are achieved, and the equivalent oxide thickness is reduced; and good contact between the channel layer and source and drain metal is realized, the contact resistance of the transistor is reduced, and the electrical performance of the transistor is improved.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) device with low threshold voltage, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, an N well layer, a P well layer and a heavily doped P layer are formed in the semiconductor epitaxial layer through ion implantation, the grid electrode comprises a triangular grid electrode and a rectangular grid electrode, the grid oxide layer covering the surface of the triangular grid electrode is in contact with the N substrate layer, and the N drift layer is divided into a left part and a right part by the grid oxide layer. According to the invention, the grid electrode is designed to further comprise the triangular grid electrode, the electric field effect of the grid electrode between the tip part of the triangular grid electrode and the drain electrode is better, but the grid oxide layer wrapped by the triangular grid electrode at the tip part is thicker, so that charges flowing out of the drain electrode gather towards the inside of the heavily doped N layer more quickly along the grid oxide layer; at the moment, more charge flow can be provided in a smaller grid voltage environment.

The invention provides a method for manufacturing a semiconductor device and a vertically stacked semiconductor device, which can be applied to the technical field of semiconductors. The manufacturing method includes: disposing a lower field effect transistor and an upper field effect transistor on a substrate, the lower field effect transistor and the upper field effect transistor being stacked in a vertical direction; the upper surface of the substrate is connected with the lower surface of the lowermost gate stack in the lower field effect transistor and the lower surface of the source / drain layer; forming a full silicide layer on the exposed lower surface of the gate stack in the lower field effect transistor and the exposed lower surface of the source / drain layer; patterning the full silicide layer to form an opening which exposes the lower surface of the lowermost gate stack in the lower field effect transistor, and forming silicide layer patterns which are arranged on the two sides of the opening in the first direction and are connected with the lower surface of a source / drain layer in the lower field effect transistor at the same time; filling a dielectric material in the opening so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack; a contact hole is provided in contact with the silicification layer pattern.

In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.

The invention discloses an accelerated degradation model of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) under alternating gate drive, which takes gate negative bias voltage, junction temperature, multiple stresses of gate voltage rise time and switching times as inputs and threshold voltage variation as outputs, solves the problem of inaccurate threshold voltage drift prediction of the SiC MOSFET under alternating-current BTI (Bias Temperature Instability), and improves the prediction accuracy of the SiC MOSFET under alternating-current BTI. The method can be used for describing the SiC MOSFET threshold voltage degradation rule in the alternating gate drive mode. According to the invention, the change rule of key performance parameters in the long-term use process of the SiC MOSFET device can be reflected, and the method has important significance for accurately evaluating and optimizing and improving the use reliability of the device.

A semiconductor device including a stacked structure including first vertically stacked channel regions positioned over second vertically stacked channel regions. The first and second vertically stacked channel regions have a mid dielectric layer positioned therebetween. A structure is present having a first portion in electrical communication with the first vertically stacked channel regions and a second portion in electrical communication with the second vertically stacked channel regions. The semiconductor device also includes at least one two-component gate cut structure present adjacent to the gate all around structure. A first component of the two-component gate cut structure in positioned on one side of the mid dielectric layer adjacent to the first portion of the gate structure, and a second component of the two-component gate cut structure is positioned on a second side of the mid dielectric layer adjacent to the second portion of the gate structure.

The invention belongs to the technical field of power devices, and provides a silicon carbide device structure, a preparation method thereof and a chip, a P-type heavily doped region is isolated from a junction field effect transistor region at an adjacent position by a P-type well region, and an N-type heavily doped region is isolated from the junction field effect transistor region at an adjacent position by the P-type well region. The adjacent junction field effect transistor regions are isolated by the P-type well regions, so that a super-junction-like structure is formed, the junction field effect transistor regions can have donor doping with higher doping concentration, corner arrangement is avoided, a depletion region can be completely closed, the on resistance of the device is reduced, and the reliability of the device is improved.

The invention provides a grid-controlled junction field effect transistor, which comprises a substrate and an epitaxial layer formed on the substrate, the channel region of the second doping type is formed downwards from the top surface of the epitaxial layer; the second doping type source electrode contact region is formed downwards from the top surface of the epitaxial layer and is connected to the outer edge of the channel region; the grid electrode of the first doping type is formed on the channel region in the vertical direction, and the outer edge of the grid electrode is located in the outer edge of the channel region in the transverse direction, so that a preset distance is kept between the grid electrode and the source electrode contact region of the second doping type in the transverse direction; and the well region is positioned below the second doping type source contact region. According to the invention, the technical problem that the input capacitance and grid leakage of a traditional grid-controlled junction field effect transistor are relatively large is solved.

The invention belongs to but is not limited to the technical field of state monitoring, and particularly relates to a multi-feature fusion power field effect transistor online state monitoring and evaluation method and system, which are used for understanding the aging mechanism of a device by selecting a proper aging signal and calculating the features of the aging signal. Then, effective feature information strongly correlated with the life sequence is screened out by using a mutual information correlation coefficient algorithm; next, dimension reduction fusion is performed on the screened features by using a KPCA polynomial kernel function algorithm, so that a health index is constructed, and the degradation state of the device is reflected; and monitoring and evaluating the health state of the device by using CNN, XGBoost and RF classifiers according to the constructed health indexes so as to determine the health state of the device. In addition, the RF classification model with the best classification effect is deployed on the DSP development board, the performance of the prediction model is further optimized, and the prediction time of the model is shortened. According to the method, the health state of the power device is described by integrating the multi-feature information.

The invention discloses a cascode cascade type switching device with a cascode current limiting structure. The cascode cascade type switching device comprises a grid end, a source end, a drain end, a low-voltage enhancement type field effect transistor, a high-voltage depletion type field effect transistor and the current limiting structure. The current limiting structure comprises a plurality of common-gate current limiting depletion type field effect transistors and a current limiting resistor. According to the current-limiting depletion type field-effect transistor, when a switching device is turned on, the grid current of the high-voltage depletion type field-effect transistor can be limited through the current-limiting resistor and the series internal resistors of the plurality of current-limiting depletion type field-effect transistors, so that the working reliability of the current-limiting depletion type field-effect transistor and the whole switching device is improved.

The invention provides an electric field enhancement type shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises a substrate, an epitaxial layer formed on the substrate, a gate trench formed on a cellular region on the epitaxial layer, and a first gate dielectric layer formed at the bottom of the gate trench and a first polycrystalline silicon layer located in the first gate dielectric layer, a P-type epitaxial layer is formed on the first gate dielectric layer and the first polycrystalline silicon layer, and an isolation dielectric layer is formed on the P-type epitaxial layer; a second gate dielectric layer is formed on the side wall of the residual gate trench, and a second polycrystalline silicon layer is formed in the residual gate trench; a well region and a source region of a cellular region are formed on the epitaxial layer, and a contact hole dielectric layer is formed on the epitaxial layer; and contact holes communicated with the well region are formed on the contact hole dielectric layer and the epitaxial layer below the contact hole dielectric layer. By adding the shield grid P-type epitaxial layer, the electric field intensity in the middle of the drift region is effectively improved, the breakdown voltage is improved, and meanwhile, the conduction loss can be further reduced by adjusting epitaxy.

A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.

The invention relates to the technical field of semiconductor manufacturing, and provides a method and a system for testing the service life of a power field effect transistor. The method comprises the following steps: acquiring test environment parameter information of a to-be-tested power field effect transistor in a database; the test environment parameter information comprises a plurality of environment parameter sets; for each environmental parameter set, performing an electrical performance test on the to-be-tested power field effect transistor in a test environment corresponding to the environmental parameter set to obtain electrical performance parameter information corresponding to the environmental parameter set; performing defect prediction on the to-be-tested power field effect transistor based on a preset defect prediction algorithm and the electrical performance parameter information to obtain defect prediction information; and predicting the service life of the power field effect transistor based on the defect prediction information. The method improves the accuracy of the life test result.

The invention discloses an intelligent control cooling fan driving method, relates to the technical field of intelligent cooling, and solves the problems that the working mode of a traditional fan is irrelevant to an electric control working state, the fan always runs at the maximum rotating speed after electric control is started, and electric energy is wasted. The cooling fan driving method comprises the steps that the controller conducts power sampling and dynamic calibration on the direct-current side and the alternating-current side of the inverter circuit respectively, and voltage and current are obtained; calculating corresponding power and a power loss value according to the corresponding voltage and current on the two sides, performing temperature compensation on the power loss value according to the junction temperature of the field effect transistor to obtain real-time power loss, and recording loss duration; according to the environment temperature, a loss power threshold value and a loss time threshold value are preset and compared with the real-time power loss and the loss duration time, and meanwhile the real-time power loss and the loss duration time are stored to the controller; and establishing a nonlinear mapping model of the PWM duty ratio and the voltage of the electric control high-power output port, and regulating and controlling the rotating speed of the fan in combination with a multi-stage speed regulation mechanism so as to complete the driving control of the fan.

A semiconductor device includes a plurality of field effect transistors (FET) formed upon semiconductor fins. Each FET includes a gate disposed transversely upon a first portion of the fins of the FET, one or more source / drain regions disposed upon the fins and in contact with the gate, and an electrically isolating layer disposed adjacent to a second portion of the fins above the gate and the source / drain regions, the electrically isolating layer having an interface with the gate. The device further includes a buried power rail (BPR) disposed between otherwise adjacent FETs. The BPR includes a metal rail extending beyond the interface into the gate, and electrically isolating sidewalls separating the metal rail from the gate and the source / drain regions. The device also includes a via-buried power rail contact disposed adjacent to the electrically isolating sidewalls, in contact with the metal rail, and in contact with one source / drain region.

A semiconductor device includes a dielectric wall provided in a direction perpendicular to a substrate, a first metal oxide field effect transistor (MOSFET) provided on one side surface of the dielectric wall, a second MOSFET provided above the first MOSFET in a direction perpendicular to the substrate, and a third MOSFET provided in parallel with the first MOSFET on the other side surface of the dielectric wall.

The invention relates to the technical field of electronic circuits, in particular to a threshold voltage control system and control equipment of a field effect transistor. Comprising a main feedback loop used for obtaining an actual value of a threshold voltage of a field effect transistor, comparing the actual value of the threshold voltage with a set value to obtain a deviation signal, and sending the deviation signal to a control module; the auxiliary feedback loop is used for collecting the current change rate of the field effect transistor and sending the current change rate to the control module; the control module is used for generating a control signal according to the deviation signal and the current change rate and adjusting the grid voltage of the field effect transistor according to the control signal so as to control the threshold voltage of the field effect transistor. According to the invention, the main feedback loop and the auxiliary feedback loop cooperatively collect the voltage deviation signal and the current change rate of the field effect transistor so as to dynamically adjust the grid voltage of the field effect transistor, thereby improving the control precision.

A semiconductor structure includes a device layer, which in turn includes a plurality of field effect transistors, each of which has a first source-drain region, a second source-drain region, at least one channel region coupling the first and second source-drain regions; and a gate surrounding the at least one channel region. The semiconductor structure further includes a front side wiring layer with wiring coupled to the plurality of field effect transistors at a front side of the device layer; a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.

The invention discloses a microwave cold noise source fusing TEC temperature control and noise temperature compensation technologies, and belongs to the technical field of microwave radiometer calibration. The device comprises a cold source module, a noise compensation module and a constant-temperature control module, wherein the cold source module generates a low-temperature noise signal through a field-effect tube and a terminal resistor; the noise compensation module detects environment temperature change in real time based on a thermistor and a Wheatstone bridge, drives a noise diode to generate a compensation signal, couples the compensation signal with a cold source noise signal after attenuation, and counteracts noise temperature deviation caused by the environment temperature. The constant temperature control module adopts a platinum resistance sensor and a PID algorithm to control a Peltier element in a closed-loop mode, and accurate adjustment (+ / -0.1 DEG C) is achieved. According to the invention, noise compensation and TEC negative feedback temperature control technologies are combined, so that the noise temperature of the system is stabilized in a range of + / -0.1 K for a long time, the measurement precision and reliability of the microwave radiometer in an outdoor complex environment are remarkably improved, and the method is suitable for scenes of remote sensing detection, unmanned aerial vehicle monitoring and the like.

The embodiment of the invention provides a field effect transistor, electronic equipment and a preparation method of the field effect transistor, and relates to the technical field of semiconductors. Wherein the field effect transistor comprises a second substrate, an oxide layer and a grid electrode, and the material of the second substrate comprises silicon carbide; the second substrate comprises a source region and a channel region, and the doping concentration of the source region is larger than that of the channel region. The oxide layer is bonded with the second substrate; the oxide layer covers at least part of the channel region; the oxide layer is formed by oxidizing a silicon material. The grid electrode is arranged on the side, away from the second substrate, of the oxide layer. According to the field effect transistor provided by the embodiment of the invention, the oxidation degree of the gate oxide layer is relatively high, and the interface state density between the silicon carbide substrate and the gate oxide layer is relatively small, so that the channel mobility of the silicon carbide field effect transistor is effectively improved, and the electrical performance and reliability of the field effect transistor are optimized.

A multi-gate hybrid-channel field-effect transistor (FET) structure of an integrated device like a nanosheet device or a forksheet device comprises a substrate layer, a first layer stack and a second layer stack arranged side by side on the substrate layer, a first and second additional semiconductor channel layer arranged respectively besides the second layer stack, and a dielectric wall arranged on the substrate layer between the first layer stack and the second layer stack. The first and second layer stack each comprise one or more semiconductor channel layers and gate layers stacked alternatingly with respective surfaces parallel to the surface of the substrate layer. Respective surfaces of the first and second additional semiconductor channel layer are parallel to each other and perpendicular to the surface of the substrate layer.

A semiconductor device is provided and includes a first transistor including a first source / drain (S / D) region, a second transistor stacked over the first transistor and including a second S / D region, a first backside power rail (BPR) disposed below the first transistor, a second BPR disposed below the first BPR, a via by which the second S / D region and the first BPR are connected and metallization. The metallization passes through and is insulated from the first BPR. The first S / D region and the second BPR are connected by the metallization.

The invention relates to the field of nonvolatile memories, in particular to an SOT-MRAM circuit unit based on a 2T2M differential structure and a storage array circuit of the SOT-MRAM circuit unit. The SOT-MRAM unit comprises a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first phase inverter, a second phase inverter, a write line, a read line, an input line and an output line which have a specific connection relation. According to the SOT-MRAM circuit unit, through the special 2T2M differential structure design and in combination with the excellent performance of a spin-orbit moment magnetic tunnel junction, the storage and operation performance and efficiency of a 2T2MSOT-MRAM differential circuit unit array are integrally improved, the dependence on the performance of the MTJ is reduced, the SOT-MRAM circuit unit has the better energy efficiency ratio and the more stable read-write speed and precision, and the SOT-MRAM circuit unit has the advantages of being simple in structure, low in cost and high in reliability. And the reliability and the stability are excellent.

Embodiments of the present disclosure provide a semiconductor device structure having a vertically stacked complementary field effect transistor (CFET). The CFET is formed by bonding two substrates on which a semiconductor stack is formed. Bonding structures are formed between the semiconductor stacks using wafer bonding techniques. Embodiments of the present disclosure enable flexibility in selecting different N / P channel characteristics, provide a simple way to form N / P channel isolation structures, and reduce potential leakage paths and defects in stacking CFETs. The embodiment of the invention also relates to a semiconductor device and a manufacturing method thereof.