3132 results about "Field-effect transistor" patented technology

The invention discloses a big data-driven hydrogen fluoride purification risk entropy assessment and multi-parameter monitoring system, which relates to the technical field of chemical process monitoring, comprises a multi-mode heterogeneous sensor network, and realizes high-precision detection and three-dimensional monitoring by using a nanowire FET (Field Effect Transistor) and the like. The space-time tensor decomposition module extracts features and identifies a causal relationship; the risk entropy manifold learning module evaluates the risk; the self-adaptive twin network monitors the abnormity and simulates and disposes the abnormity; and a knowledge graph-reinforcement learning system decision making subsystem and a plurality of subsystems such as an optical monitoring subsystem and a multi-scale modeling subsystem are also provided, so that whole-process risk management and control are realized. The hydrogen fluoride purification monitoring level is greatly improved, the detection sensitivity and the anomaly detection accuracy are remarkably improved, risk early warning is more timely, decision response is accelerated, the production efficiency is improved, energy consumption is reduced, the system has self-repairing and self-power-supply capabilities, data are safe and traceable, reliable operation of the system is guaranteed, and economic losses and potential safety hazards are reduced.

A semiconductor device is provided. The semiconductor device includes a back-end-of-line (BEOL) layer, a backside power distribution network (BSPDN), a stacked field effect transistor (stacked FET) and a backside contact. The stacked FET is vertically interposed between the BEOL layer and the BSPDN and includes a top FET with top source / drain (S / D) epitaxy and a bottom FET with bottom S / D epitaxy. The stacked FET is characterized as having at least partial vertical alignment of the top FET and the bottom FET. A backside contact electrically connects the BSPDN and the top S / D epitaxy and cuts through the bottom S / D epitaxy with isolation between the backside contact and the bottom S / D epitaxy.

The invention belongs to the technical field of power devices, and provides a silicon carbide device structure, a preparation method thereof and a chip, a P-type heavily doped region is isolated from a junction field effect transistor region at an adjacent position by a P-type well region, and an N-type heavily doped region is isolated from the junction field effect transistor region at an adjacent position by the P-type well region. The adjacent junction field effect transistor regions are isolated by the P-type well regions, so that a super-junction-like structure is formed, the junction field effect transistor regions can have donor doping with higher doping concentration, corner arrangement is avoided, a depletion region can be completely closed, the on resistance of the device is reduced, and the reliability of the device is improved.

The invention belongs to but is not limited to the technical field of state monitoring, and particularly relates to a multi-feature fusion power field effect transistor online state monitoring and evaluation method and system, which are used for understanding the aging mechanism of a device by selecting a proper aging signal and calculating the features of the aging signal. Then, effective feature information strongly correlated with the life sequence is screened out by using a mutual information correlation coefficient algorithm; next, dimension reduction fusion is performed on the screened features by using a KPCA polynomial kernel function algorithm, so that a health index is constructed, and the degradation state of the device is reflected; and monitoring and evaluating the health state of the device by using CNN, XGBoost and RF classifiers according to the constructed health indexes so as to determine the health state of the device. In addition, the RF classification model with the best classification effect is deployed on the DSP development board, the performance of the prediction model is further optimized, and the prediction time of the model is shortened. According to the method, the health state of the power device is described by integrating the multi-feature information.

The invention discloses an intelligent control cooling fan driving method, relates to the technical field of intelligent cooling, and solves the problems that the working mode of a traditional fan is irrelevant to an electric control working state, the fan always runs at the maximum rotating speed after electric control is started, and electric energy is wasted. The cooling fan driving method comprises the steps that the controller conducts power sampling and dynamic calibration on the direct-current side and the alternating-current side of the inverter circuit respectively, and voltage and current are obtained; calculating corresponding power and a power loss value according to the corresponding voltage and current on the two sides, performing temperature compensation on the power loss value according to the junction temperature of the field effect transistor to obtain real-time power loss, and recording loss duration; according to the environment temperature, a loss power threshold value and a loss time threshold value are preset and compared with the real-time power loss and the loss duration time, and meanwhile the real-time power loss and the loss duration time are stored to the controller; and establishing a nonlinear mapping model of the PWM duty ratio and the voltage of the electric control high-power output port, and regulating and controlling the rotating speed of the fan in combination with a multi-stage speed regulation mechanism so as to complete the driving control of the fan.

The invention relates to the technical field of electronic circuits, in particular to a threshold voltage control system and control equipment of a field effect transistor. Comprising a main feedback loop used for obtaining an actual value of a threshold voltage of a field effect transistor, comparing the actual value of the threshold voltage with a set value to obtain a deviation signal, and sending the deviation signal to a control module; the auxiliary feedback loop is used for collecting the current change rate of the field effect transistor and sending the current change rate to the control module; the control module is used for generating a control signal according to the deviation signal and the current change rate and adjusting the grid voltage of the field effect transistor according to the control signal so as to control the threshold voltage of the field effect transistor. According to the invention, the main feedback loop and the auxiliary feedback loop cooperatively collect the voltage deviation signal and the current change rate of the field effect transistor so as to dynamically adjust the grid voltage of the field effect transistor, thereby improving the control precision.

A semiconductor structure includes a device layer, which in turn includes a plurality of field effect transistors, each of which has a first source-drain region, a second source-drain region, at least one channel region coupling the first and second source-drain regions; and a gate surrounding the at least one channel region. The semiconductor structure further includes a front side wiring layer with wiring coupled to the plurality of field effect transistors at a front side of the device layer; a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.

The invention discloses a microwave cold noise source fusing TEC temperature control and noise temperature compensation technologies, and belongs to the technical field of microwave radiometer calibration. The device comprises a cold source module, a noise compensation module and a constant-temperature control module, wherein the cold source module generates a low-temperature noise signal through a field-effect tube and a terminal resistor; the noise compensation module detects environment temperature change in real time based on a thermistor and a Wheatstone bridge, drives a noise diode to generate a compensation signal, couples the compensation signal with a cold source noise signal after attenuation, and counteracts noise temperature deviation caused by the environment temperature. The constant temperature control module adopts a platinum resistance sensor and a PID algorithm to control a Peltier element in a closed-loop mode, and accurate adjustment (+ / -0.1 DEG C) is achieved. According to the invention, noise compensation and TEC negative feedback temperature control technologies are combined, so that the noise temperature of the system is stabilized in a range of + / -0.1 K for a long time, the measurement precision and reliability of the microwave radiometer in an outdoor complex environment are remarkably improved, and the method is suitable for scenes of remote sensing detection, unmanned aerial vehicle monitoring and the like.

A semiconductor device is provided and includes a first transistor including a first source / drain (S / D) region, a second transistor stacked over the first transistor and including a second S / D region, a first backside power rail (BPR) disposed below the first transistor, a second BPR disposed below the first BPR, a via by which the second S / D region and the first BPR are connected and metallization. The metallization passes through and is insulated from the first BPR. The first S / D region and the second BPR are connected by the metallization.

The invention discloses a neuron circuit and brain-like computing system based on multi-neuromorphic behaviors, and the neuron circuit maps an appreciation-Ross model to the field of physical circuits through a capacitance dynamic response mechanism and the cross-interval nonlinear characteristics of a metal-oxide semiconductor field effect transistor. Then the expanded appreciation-Ross model is realized through the design of a metal-oxide semiconductor field effect transistor; the neuron circuit comprises a membrane voltage circuit, a slow variable circuit and a recovery variable circuit. The membrane voltage circuit is used for receiving an input signal and accumulating membrane voltage; the slow variable circuit is used for accumulating a slow variable according to the membrane voltage and enabling the neuron circuit to enter a hyperpolarization stage after the slow variable is greater than a preset threshold value; the recovery variable circuit is used for outputting a recovery variable according to the film voltage delay and resetting the film voltage to a resting potential through the recovery variable.

A semiconductor device includes a semiconductor substrate having a mesa structure, a dielectric layer surrounding the mesa structure, and a gate electrode over the dielectric layer. The semiconductor substrate includes a bottom source region, a contact source region, and a sidewall body region in the mesa structure. The semiconductor substrate includes a liner doped region adjoining a frontside surface of the semiconductor substrate and a drain region adjoining a backside surface of the semiconductor substrate. The bottom source region, the contact source region, and the drain region have a first conductivity type, and the sidewall body region and the liner doped region have a second conductivity type opposite to the first conductivity type. A bottom of the gate electrode is higher than a top end of a first portion of the liner doped region in the mesa structure.

The invention provides a preparation method of a planar gate accumulation layer channel field effect transistor embedded with a 3C / 4H-SiC heterogeneous junction. The preparation method comprises the following steps: growing an (n-) 4H-SiC drift region and an (n) 4H-SiC current expansion layer (CSL) on an (n +) 4H-SiC substrate by adopting a hot wall chemical vapor deposition (HWCVD) technology; forming a (p) 4H-SiC body region and an (n) 4H-SiC layer on the two sides of the CSL by using a mask, inductively coupled plasma (ICP) etching and ion implantation methods; growing a (p) 3C-SiC region on the upper part of the inner side of each (p) 4H-SiC body region by using a mask, ICP (Inductively Coupled Plasma) etching and HWCVD (High Weight Chemical Vapor Deposition); forming (n) 4H-SiC channels on the two sides of the middle part of the CSL by using a mask and HWCVD, and forming a (p) 3C / (n) 4H-SiC heterogeneous junction with a (p) 3C-SiC region at the bottom; respectively forming an (n +) 4H-SiC source region and a (p +) 4H-SiC source region on the outer side of each (n) 4H-SiC channel by utilizing ion implantation; forming an (n +) 3C-SiC region on the outer side of each (p +) 4H-SiC source region by adopting mask, ICP etching and HWCVD, and forming an (n +) 3C / (n) 4H-SiC heterogeneous junction with the (n) 4H-SiC layer below the (p +) 4H-SiC source region; performing high-temperature annealing to eliminate defects and activate impurities; forming an oxide layer and an (n +) poly-Si gate on the top; and respectively evaporating an alloy grid electrode, a source electrode and a drain electrode to prepare the planar gate accumulation layer channel field effect transistor embedded with the 3C / 4H-SiC heterogeneous junction. The leakage current of the transistor is small and is smaller than the on-resistance (Ron, sp), and the reverse recovery time is short.

A semiconductor device is provided. The semiconductor device includes a stacked field effect transistor (FET) formed on a substrate and connected to a backside metal line of a backside power distribution network (BSPDN). The semiconductor device also includes a lateral junction diode co-integrated with the stacked nanosheet FET.

In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

The invention discloses a ferroelectric semiconductor junction field effect transistor, a preparation method and application. The transistor can simultaneously realize optical sensor, storage, synapse and logic in a single device by utilizing the physical characteristics of the transistor. The structure comprises a source electrode, a drain electrode, a control grid electrode, a channel layer, a ferroelectric grid layer, an oxide layer and a substrate from top to bottom. The channel layer is made of a two-dimensional transition metal sulfide semiconductor material, the ferroelectric gate layer is made of a two-dimensional ferroelectric semiconductor material, the source electrode and the drain electrode are located on two layers of the two-dimensional semiconductor channel respectively, and the control gate is located over the ferroelectric gate layer. According to the preparation method and application of the ferroelectric semiconductor junction field effect transistor, the logic functions of optical signal sensing, data storage, synaptic calculation and self-switching can be integrated in a single transistor, the function discrete limitation of a traditional device is broken through, a new path is provided for a high-density integrated reconfigurable electronic device, and the field effect transistor is suitable for large-scale popularization and application. And the structure complexity and the function density are effectively balanced.

The invention provides an MOSFET and a manufacturing method thereof. The MOSFET includes a substrate; the epitaxial layer is arranged on the substrate; the trench gate group comprises a first trench gate and a plurality of second trench gates, the first trench gate extends into the epitaxial layer from the surface of the side, away from the substrate, of the epitaxial layer, the first trench gate extends in the first direction on the plane where the epitaxial layer is located, and the second trench gates are arranged at intervals in the first direction; the orthographic projection of the second trench gate on the substrate is located in the orthographic projection range of the first trench gate on the substrate, the top of the second trench gate is in contact with the bottom of the first trench gate, and a gate layer in the second trench gate is connected with a gate layer in the first trench gate; each shielding region wraps the bottom and all the side walls of the second trench gate and extends towards the surface of the side, away from the substrate, of the epitaxial layer so as to cover the side wall of the first trench gate, and the multiple shielding regions are arranged at intervals. The shielding region has a three-dimensional structure, so that the stress of a trench gate oxide electric field can be reduced, the cell size of the MOSFET can be reduced, and the current density of the MOSFET can be improved.

A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E / C) regions and a base region between the E / C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S / D) regions, a channel region between the S / D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.

The invention provides a switching power supply device comprising a transformer which comprises a primary winding and a secondary winding and is used for converting an input voltage into an output voltage; the primary switching tube is connected with the primary winding and controls the on-off of the primary winding; the rectifying unit is connected with the secondary winding and rectifies the output of the secondary winding, and the rectifying unit comprises a semiconductor field effect transistor; the control unit is connected with the rectification unit and generates a control signal so as to control the switch of the semiconductor field effect transistor through the control signal; the current detection unit detects the output current and generates a current detection signal; the control unit receives the current detection signal and adjusts the control signal according to the current detection signal. According to the device, the COOLMOS with small internal resistance and high switching speed is adopted, the switching loss is reduced, the switching signal is dynamically adjusted by the control unit according to the real-time output current, the rectification conduction loss and the switching noise are reduced, the power supply conversion efficiency is improved, and the electromagnetic interference is reduced.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses an MOSFET (metal oxide semiconductor field effect transistor) structure with a nanosheet full-surrounding grid electrode and a manufacturing process thereof, the MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a grid oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, the grid electrode comprises a grid electrode covering layer and a grid electrode nanosheet; a plurality of grid nanosheets are arranged in a single MOS cell, are distributed in a horizontal matrix, extend to the inside of the grid covering layer and are in direct contact with the grid covering layer. Through the three-dimensional embedded contact between the nanosheet grids in horizontal matrix distribution and the high-conductivity covering layer, the static control capability of the channel is remarkably enhanced, the grid resistance is reduced, higher current driving density and better switching characteristics are realized, and the physical limitation of a traditional planar device is broken through.

The invention discloses a current-to-voltage conversion circuit structure for electroporation delivery. The current-to-voltage conversion circuit structure comprises a current-to-voltage conversion circuit and a voltage-to-pulse conversion circuit. The current-to-voltage circuit converts current signals into voltage through an input signal processing module, high-precision amplification is achieved through an operational amplifier and a feedback network of a signal amplification module, the driving capacity is enhanced through a transistor cascade circuit, and temperature drift is dynamically compensated in combination with a thermistor. The voltage-to-pulse circuit corrects non-linear errors through a resistance network of the linearization processing module, achieves gain adjustment through an operational amplifier and an adjustable resistor, and finally adapts to load changes through a field effect transistor and a negative feedback network. The circuit realizes high conversion precision, wide temperature range stability and load adaptive capability, and is suitable for high-precision scenes such as medical treatment or beauty electroporation, industrial sensing and the like.

Techniques are provided to form an integrated circuit having different semiconductor devices with different backside contact structures. Field effect transistors (FETs) each includes semiconductor material extending in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. Different contact structures are formed on the source or drain regions of the n-channel FETs compared to the p-channel FETs. A backside contact structure on an n-channel source or drain region includes a first layer of phosphorous-doped titanium, a second layer that includes scandium, and a third layer that includes a metal, such as molybdenum. A backside contact structure on a p-channel source or drain region may include only a layer of metal, such as molybdenum, or the layer of metal and a layer of boron-doped titanium. The contact structures may be used to provide enhanced ohmic contact.

The invention discloses a P-type tellurium oxide thin film field effect transistor and a preparation method thereof. The transistor is provided with a bottom gate top contact structure. The preparation method comprises the following steps: firstly, cleaning the silicon / silicon dioxide substrate, then depositing a tellurium oxide film as the semiconductor active layer by using a metal mask and an electron beam evaporation method, and finally preparing a layer of nickel with the thickness of about 50nm on the active layer by using the mask to serve as the source electrode and the drain electrode. Compared with a traditional tellurium oxide transistor, the tellurium oxide transistor prepared by the method has the advantages that the carrier mobility and the switching ratio are obviously improved, and the hysteresis effect can be ignored. The electrical performance of the tellurium oxide transistor with the bottom gate top contact structure is improved, and the tellurium oxide transistor has the advantages of being low in cost and simple in process step.

A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate having an upper surface; an insulation pattern provided above the substrate and contacting an upper surface of the active pattern; channels spaced apart from each other along a direction perpendicular to the upper surface of the substrate, each of the channels including a material provided in the active pattern; and a gate structure contacting an upper surface of the insulation pattern, an upper surface of the channels, a lower surface of the channels, and sidewalls of the channels opposite to each other. A first distance between an upper surface of the active pattern and a lowermost one of the channels is greater than a second distance between an upper surface of one of the channels and a lower surface of an adjacent channel.

The invention discloses a system for detecting viral nucleic acid on the basis of a CRISPR (clustered regularly spaced short palindromic repeat) technology and an FET (field effect transistor) chip and application of the system, and relates to a method for detecting the viral nucleic acid on the basis of clustered CRISPR (clustered regularly spaced short palindromic repeat) and related proteins (Cas) and a field effect transistor (FET). The CRISPR-FET (clustered regularly interspaced short palindromic repeats-field effect transistor) detection system comprises a non-amplified CRISPR system, a reporter RNA (ribonucleic acid) and gold nanoparticles (AuNPs) connection system, a separation system and a field effect transistor chip detection system. The CRISPR-FET detection method provided by the invention has high sensitivity and high specificity on virus nucleic acid detection, and the lower limit of detection reaches a single copy (100 copies / [mu] L).

A semiconductor structure including a substrate, a first stack of channel layers on the substrate and a second stack of channel layers vertically aligned above the first stack. The width of the first is greater than the second. Additionally, the first channel layers can be cladded with germanium while the second channel layers can have a dog-bone shape.

Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor and the first transistor may include first and second source / drain regions, a first channel region between the first and second source / drain regions, and a first gate structure on the first channel region. A lower surface of the first source / drain region may be higher than a lower surface of the first gate structure relative to the substrate.

A semiconductor device includes: a substrate including active patterns; a device isolation layer disposed between the active patterns; a stacked pattern disposed on the substrate; a power transmission network layer disposed on a first surface of the substrate; a first through via penetrating the stacked pattern; and a second through via disposed between the power transmission network layer and the first through via, wherein the second through via penetrates the active patterns and the device isolation layer.

The present invention relates to a method for active balancing of lithium-ion battery packs based on time optimization, belonging to the field of lithium batteries. A hierarchical active balancing topology structure of module-to-module architecture and unit-to-module architecture is constructed; a relationship between the battery state of charge (SOC) and the pulse width modulation (PWM) duty cycle of the equalizer is established, and the balancing controller is made to act directly on the field effect transistor of the equalizer; by reducing the micro-cycle period between the charge and discharge of the intermediate battery, the SOC of the battery is ensured to converge to a point; a hierarchical balancing topology structure is also developed to simplify the battery pack structure and reduce computing costs. The present invention adopts a time-optimal model predictive control (MPC) strategy and designs a time-optimal method for reducing the micro-cycle of charge and discharge of the intermediate battery, overcoming the problems of large energy loss and rapid battery temperature rise when solving the problem of battery pack inconsistency, and improving the robustness of the system.

The invention provides a low-noise amplification circuit, a radio frequency front-end module and an electronic terminal.The low-noise amplification circuit comprises an input matching adjustment circuit, a common-source amplification circuit, a first inductor, an inter-stage feedback circuit, a common-gate amplification circuit, an input and output feedback circuit, an output matching adjustment circuit and an output attenuation circuit; the common-source amplification circuit comprises at least two first signal amplification units; each first signal amplification unit comprises a first field effect transistor; the common-gate amplification circuit comprises at least two second signal amplification units; and each second signal amplification unit comprises a second field effect transistor. According to the low-noise amplification circuit, transconductance nonlinearity of devices under different bias signals can be mutually counteracted, so that the linearity fluctuation of the low-noise amplification circuit at different temperatures is optimized, and the linearity of the low-noise amplification circuit is kept basically not to change along with the temperature change.

A semiconductor device is provided that includes a multilayered insulator region located between stacked FETs. The multilayered insulator region is referred to herein as a multi-dielectric material middle isolation structure. The multi-dielectric material middle isolation structure includes a middle dielectric isolation structure having a middle dielectric isolation spacer located at two opposing ends of, or surrounding, the middle dielectric isolation structure. The middle dielectric isolation spacer protects the middle dielectric isolation structure during processing of the stacked FETs such that no damage to the middle dielectric isolation structure and the semiconductor channel regions of the stacked FETs is observed.