910 results about "Metal gate" patented technology

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the pseudo gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer; oxidizing the hard mask layer, a part of the contact hole etching stop layer and a part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and a part of the interlayer dielectric layer, wherein the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on the two sides; and removing the dummy gate to form a metal gate. According to the manufacturing method of the semiconductor device provided by the invention, the height of the formed metal gate can be ensured, the manufacturing process is simple, and the controllability is high.

In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

The invention discloses a gate dielectric film growth process, an HEMT (High Electron Mobility Transistor) device and a preparation method, and the gate dielectric film growth process comprises the steps: executing a primary process cycle of atomic layer deposition, and forming an amorphous gate dielectric film on the surface of a substrate; after the primary process circulation is completed, in-situ gas plasma treatment is executed, a single crystal gate dielectric film converted from the amorphous gate dielectric film after treatment is obtained, and when the single crystal gate dielectric film is formed between a metal gate and a barrier layer of the HEMT device, the interface state of the metal gate at a gate groove can be improved, the quality of a contact interface below gate metal is improved, and the performance of the HEMT device is improved. And the defect density and the electron trapping effect are reduced, so that the problems of serious influence on safe operation of the device and even grid degradation caused by grid leakage and threshold voltage drift after stress of the device can be effectively avoided, and the performance of the device is improved.

An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming an n-type work function layer in a gate trench in a gate structure, wherein the n-type work function layer is formed around first channel layers in a p-type gate region and around second channel layers in an n-type gate region, forming a first metal fill layer in a first gate trench over the n-type work function layer in the p-type gate region and in a second gate trench over the n-type work function layer in the n-type gate region, removing the first metal fill layer from the p-type gate region, removing the n-type work function layer from the p-type gate region, forming a p-type work function layer in the first gate trench of the p-type gate region, and forming a second metal fill layer in the first gate trench of the p-type gate region.

A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.

The invention provides a metal gate and a preparation method thereof, and the preparation method comprises the steps: depositing a first metal material, carrying out the dry etching of the first metal material in a second part of a groove, removing a protrusion, enlarging the size of an opening of the groove, and filling a second metal material to form the metal gate, thereby solving a gap defect in the metal gate, and improving the reliability of the metal gate. According to the invention, the stability of the metal gate can be improved, and the difference of pattern loading (pattern loading effect) can be reduced.

The invention provides an enhanced HEMT (High Electron Mobility Transistor) device based on a P-type GaN grid electrode and a manufacturing method, a superlattice pair insertion layer is formed in a P-type GaN layer, the superlattice pair insertion layer comprises a first sub-layer and a second sub-layer which are alternately stacked, one of the first sub-layer and the second sub-layer adopts a GaN layer, and the forbidden bandwidth of the other layer is greater than 3.4 eV; by arranging the superlattice pair insertion layer, an electron barrier can be formed in the P-type GaN layer, and electrons can be prevented from moving in the gate structure, so that gate electric leakage is reduced, meanwhile, the electrons are prevented from crossing the gate structure to bombard the metal gate, and the gate reliability is improved; meanwhile, due to the fact that the ultra-thin superlattice material and the material with the forbidden bandwidth larger than 3.4 eV are AlN, BN, AlGaN, InAlN or BGaN, the dielectric constant of the material is very close to that of a GaN-based material, and therefore the gate capacitance and the threshold voltage of the device cannot be increased.

A 3D semiconductor device including: a first level including a first single crystal layer and a memory control circuit including first transistors and control circuit connectivity provided by first, second, and third metal layers; a second level including second transistors (one which includes a metal gate) disposed atop the first level; third transistors disposed atop second transistors with a fourth metal layer disposed atop; a memory array including word-lines, the memory array includes at least four memory mini arrays, where each mini array includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second or third transistors; a connection path from the fourth metal to the third or second metal layer, which includes a via disposed through the second level, and where the memory control circuit includes at least one power down control circuit.

The invention relates to the technical field of semiconductor manufacturing, and discloses an MOS (Metal Oxide Semiconductor) tube gate forming system adopting a high-K metal gate. A material deposition regulation and control module of the system analyzes the matching degree of deposition uniformity and thickness stability and generates a material deposition control parameter set; an interface processing optimization module adjusts the cavity interface processing balance based on the parameter set, and generates an interface processing optimization parameter set; the gate forming control module adjusts metal gate deposition parameters accordingly, and generates a gate forming regulation and control result; a parameter calibration intervention module dynamically adjusts parameters based on the result, and generates a calibration intervention adjustment data set; and the quality verification promotion module optimizes preparation path parameters according to the parameters and generates a quality verification data table. According to the system, through cooperative work of all the modules, accurate control over the whole preparation process of the MOS transistor grid electrode is achieved, the thickness uniformity, defect control capacity and electrical performance stability of the grid electrode are effectively improved, and the manufacturing requirements of high-precision semiconductor devices are met.

Embodiments of the present invention advantageously provide a method of manufacturing a semiconductor device having multiple threshold voltage capability in a scaled space between nanosheets in an advanced GAA node. One or more embodiments provide an integration scheme to advantageously reduce gate resistance by incorporating n- / p-dipoles with an intermediate bandgap metal with low resistance to achieve a desired work function and low resistance metal gate. In one or more embodiments, the intermediate bandgap metal is used to fill the nanosheets and as a liner for subsequent filling with the low resistance metal. After dipole processing, instead of filling surrounding gate nanosheets with conventional n or p metals, in one or more embodiments, the nanosheets are advantageously filled with a single work function intermediate energy gap metal to achieve n and p work functions. If the work function is shifted in either of the band edges of the P-dipole or the N-dipole after dipole processing, the intermediate bandgap material may also shift the band edges in the opposite manner.

Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source / drain region; a tungsten (W) cap formed from W material deposited over the metal gate and between the gate spacers; and a via gate (VG) formed above the W cap. A semiconductor fabrication method includes: receiving a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source / drain region; depositing tungsten (W) material over the substrate; removing unwanted W material to form a W cap; and forming a via gate (VG) on the W cap.

A semiconductor structure includes a substrate, plurality of active channels, a metal gate, a plurality of inner spacers and a first isolation layer. The substrate has an upper surface and a recess recessed relative to the upper surface. The active channels are vertically stacked on the upper surface of the substrate. The metal gate is disposed on the active channels. The inner spacers are disposed on a lateral surface of the metal gate. The first isolation layer is disposed within the recess and connected with the bottommost inner spacer. The first isolation layer protrudes relative to the upper surface of the substrate.

A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source / drains. Lower ends of the plurality of contact plugs may contact the plurality of source / drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

A string driver device is described in this disclosure. The string driver device includes a semiconductor channel disposed in an upper portion of a semiconductor substrate and a gate dielectric layer disposed above the semiconductor channel. The string driver device also includes a source region and a drain region disposed at opposite sides of the semiconductor channel, each of the source region and the drain region having a corresponding contact disposed thereon. The string driver device further includes a gate that is disposed above the gate dielectric layer and has a first length, and a field plate layer disposed above the gate, the field plate layer having a second length larger than the first length of the gate, wherein the field plate layer includes one or more edge regions extending across the semiconductor channel edge and toward the source region or the drain region.

A memory device and a method of forming the same, the memory device comprising: a semiconductor substrate, a plurality of active regions formed in the semiconductor substrate, the plurality of active regions separated by a plurality of first trenches extending in a first direction, a plurality of second trenches, and a plurality of third trenches extending in a second direction; a bit line doping region in the semiconductor substrate at a bottom of the second trenches and at a bottom of the second trenches communicating with the third trenches; a first isolation layer in the first trenches and the third trenches, a surface of the first isolation layer being lower than a surface of the active regions; a gate dielectric layer surrounding the active regions at the surface of the active regions; a metal gate surrounding the active regions at a surface of the gate dielectric layer on a sidewall of the active regions, a top surface of the metal gate being lower than a top surface of the active regions; and a source region at the top surface of the active regions. The memory device of the present application has improved storage density.

Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.

A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit, a first metal layer, a second metal layer, and a third metal layer; connection of the first transistors comprises the first, and / or the second, and / or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines and at least four memory mini arrays which include at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; the memory control circuit includes first transistors and voltage regulators.

A semiconductor structure includes a field effect transistor having a plurality of source / drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source / drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source / drain region of the plurality of source / drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source / drain region to a backside interconnect structure disposed above the backside interlevel dielectric.

Disclosed is a method of forming gate structures for n-type and p-type transistors. The method includes: forming an interfacial layer and high-K (HK) dielectric layer for the gate structures; forming an n-type metal layer over the HK dielectric layer; forming a hard capping layer over the n-type metal layer while simultaneously strengthening the HK dielectric layer by fluorine passivation; patterning photo resist (PR) material over the hard capping layer that exposes a portion of the hard capping layer over the p-type transistor; removing the n-type metal layer and the hard capping layer over the p-type transistor via wet etching operations using high selectivity chemicals that are highly selective to the hard capping layer and the n-type metal layer; removing the patterned PR material while insulating, by the hard capping layer, gate structures from aluminum oxidation; and forming a p-type metal layer over the hard capping layer and the p-type transistor.

A method of the present disclosure includes forming a fin-shaped structure protruding from a substrate, depositing an isolation feature on sidewalls of the fin-shaped structure, forming a dummy gate stack over a portion of the fin-shaped structure, removing a portion of the dummy gate stack to form a trench exposing the portion of the fin-shaped structure, recessing the portion of the fin-shaped structure to extend the trench downward below a top surface of the isolation feature, depositing a first dielectric layer in the trench, recessing the first dielectric layer, such that a topmost portion of the first dielectric layer is below the top surface of the isolation feature, after the recessing of the first dielectric layer, depositing a second dielectric layer in the trench, the first and second dielectric layers including different material compositions, and replacing an unremoved portion of the dummy gate stack with a metal gate structure.

Described are methods for forming complementary field-effect transistor (CFET), or other vertically aligned semiconductor structures, utilizing a sequential self-aligning process. In one example, a method of forming a complementary field-effect transistor (CFET) is provide. The method includes replacing top sacrificial layers interleaved between channel layers in a top superlattice of a top device structure with top replacement metal gate layers, the top device structure disposed on a bottom device structure, the bottom device structure disposed on a first substrate layer; securing a second substrate layer to the top device structure and removing the first substrate layer from the bottom device structure; and replacing bottom sacrificial layers interleaved between channel layers in a bottom superlattice of the bottom device structure with bottom replacement metal gate layers.

A ferroelectric transistor (FeFET) memory device includes a metal gate, a gate dielectric layer adjacent to the metal gate, a semiconductor channel layer adjacent to the gate dielectric layer, a metal drain electrode, and a metal source electrode recessed into the semiconductor channel layer. The metal gate may be oriented above or below the metal source and drain electrodes with respect to a semiconductor substrate.

Provided is a multi-stack semiconductor device that includes: a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower gate dielectric layer, a lower work-function metal layer and a lower gate metal pattern; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper gate dielectric layer, an upper work-function metal layer and an upper gate metal pattern, wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure, and wherein a replacement metal gate (RMG) inner spacer is formed between the lower work-function metal layer and the upper work-function metal layer at regions where the lower channel structure is not vertically overlapped by the upper channel structure.

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body; the semiconductor body comprises a first surface and a second surface which are oppositely arranged, the semiconductor body further comprises a well region and a first region, the first surface is provided with a gate trench, and the gate trench extends into the semiconductor body from the first surface; the grid electrode is positioned in the grid electrode groove; the grid electrode comprises a polycrystalline silicon grid electrode layer, a metal grid electrode layer and a metal silicide grid electrode layer; the metal silicide gate layer is used for reducing the resistance value of the gate, and the metal gate layer is used for preventing metal in the metal silicide gate layer from diffusing to the polycrystalline silicon gate layer; the second insulating layer is positioned on one side of the gate far away from the semiconductor body; the vertical projection of the second insulating layer on the first surface covers the vertical projection of the gate on the first surface; the source electrode is positioned on the first surface; and a drain electrode located on the second surface. According to the invention, the problem of gate voltage delay is effectively solved.

The invention relates to a millimeter wave frequency band ultra wide band packaging antenna unit and array, and belongs to the field of antennas. The antenna unit sequentially comprises a feeder line layer, a first dielectric substrate layer, a grounding plate, a first bonding layer, a second dielectric substrate layer, a first sub-patch layer, a first metal gate, a first parasitic patch layer, a second bonding layer, a third dielectric substrate layer, a second sub-patch layer, a second metal gate and a second parasitic patch layer from bottom to top. The design structure of the multi-layer stacked patch antenna is adopted, the two patches are stacked to achieve the ultra-wideband performance, the H-shaped gap is adopted for feeding, and the ultra-wideband performance can be achieved easily; the cutting angle design can widen the bandwidth and improve impedance matching on the premise that the structural complexity is not increased, a pair of parasitic patches are added around the stacked patches, and the problem of directional diagram distortion caused by shielding between the stacked structure patches is solved.

A memory device and a method for forming the same. The memory device includes a semiconductor substrate having a plurality of active regions separated by a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction, a third trench extending in the first direction in the semiconductor substrate at the bottom of the first trenches, bit line doped regions in the semiconductor substrate on both sides of the third trench, a gate dielectric layer on the sidewalls of the first and second trenches, a first dielectric layer filling the third trench, metal gates in the first trenches on the first dielectric layer and in the second trenches, the metal gates in the second trenches being broken in the second direction, source regions on the top surface of the active regions, and capacitors on the surface of the semiconductor substrate connected to the source regions. The memory device of the present invention has improved storage density.

A stacked complementary field-effect device (CFET) device includes a bottom contact region and a top contact region. A plurality of stacked CFET devices is between the bottom contact region and the top contact region. Respective ones of the plurality of stacked CFET devices comprise a first transistor layer of a first type over the bottom contact region, and a second transistor layer of a second type over the first transistor layer. The first transistor layer comprises a first plurality of channels surrounded by a first metal gate stack, and the second transistor layer comprises a second plurality of channels surrounded by a second metal gate stack, wherein the respective ones of the plurality of stacked CFET devices include different combinations of N dipole doses and a P dipole dose in both the first metal gate stack and the second metal gate stack.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, and forming a dummy gate and a hard mask layer on the substrate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer by adopting a first planarization process; performing first plasma modification treatment, and at least forming a first modified layer on the surface of the interlayer dielectric layer; second plasma modification processing is carried out, and at least the hard mask layer and a part of the contact hole etching stop layer are modified into a second modified layer; synchronously removing the first modified layer and the second modified layer, and exposing the dummy gate; and removing the dummy gate to form a metal gate. According to the invention, residual metal in the interlayer dielectric layer is avoided, the height consistency of the metal gate is improved, and the reliability of the semiconductor device is improved.

A semiconductor device comprises a semiconductor layer structure, a gate pad on the semiconductor layer structure, and a metal gate runner on the semiconductor layer structure. The metal gate runner comprises an inner gate runner that comprises a first inner segment and a second inner segment that interconnect at a first oblique angle.