683 results about "Metal gate" patented technology

In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.

The invention provides a metal gate and a preparation method thereof, and the preparation method comprises the steps: depositing a first metal material, carrying out the dry etching of the first metal material in a second part of a groove, removing a protrusion, enlarging the size of an opening of the groove, and filling a second metal material to form the metal gate, thereby solving a gap defect in the metal gate, and improving the reliability of the metal gate. According to the invention, the stability of the metal gate can be improved, and the difference of pattern loading (pattern loading effect) can be reduced.

The invention provides an enhanced HEMT (High Electron Mobility Transistor) device based on a P-type GaN grid electrode and a manufacturing method, a superlattice pair insertion layer is formed in a P-type GaN layer, the superlattice pair insertion layer comprises a first sub-layer and a second sub-layer which are alternately stacked, one of the first sub-layer and the second sub-layer adopts a GaN layer, and the forbidden bandwidth of the other layer is greater than 3.4 eV; by arranging the superlattice pair insertion layer, an electron barrier can be formed in the P-type GaN layer, and electrons can be prevented from moving in the gate structure, so that gate electric leakage is reduced, meanwhile, the electrons are prevented from crossing the gate structure to bombard the metal gate, and the gate reliability is improved; meanwhile, due to the fact that the ultra-thin superlattice material and the material with the forbidden bandwidth larger than 3.4 eV are AlN, BN, AlGaN, InAlN or BGaN, the dielectric constant of the material is very close to that of a GaN-based material, and therefore the gate capacitance and the threshold voltage of the device cannot be increased.

Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source / drain region; a tungsten (W) cap formed from W material deposited over the metal gate and between the gate spacers; and a via gate (VG) formed above the W cap. A semiconductor fabrication method includes: receiving a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source / drain region; depositing tungsten (W) material over the substrate; removing unwanted W material to form a W cap; and forming a via gate (VG) on the W cap.

A semiconductor structure includes a substrate, plurality of active channels, a metal gate, a plurality of inner spacers and a first isolation layer. The substrate has an upper surface and a recess recessed relative to the upper surface. The active channels are vertically stacked on the upper surface of the substrate. The metal gate is disposed on the active channels. The inner spacers are disposed on a lateral surface of the metal gate. The first isolation layer is disposed within the recess and connected with the bottommost inner spacer. The first isolation layer protrudes relative to the upper surface of the substrate.

A string driver device is described in this disclosure. The string driver device includes a semiconductor channel disposed in an upper portion of a semiconductor substrate and a gate dielectric layer disposed above the semiconductor channel. The string driver device also includes a source region and a drain region disposed at opposite sides of the semiconductor channel, each of the source region and the drain region having a corresponding contact disposed thereon. The string driver device further includes a gate that is disposed above the gate dielectric layer and has a first length, and a field plate layer disposed above the gate, the field plate layer having a second length larger than the first length of the gate, wherein the field plate layer includes one or more edge regions extending across the semiconductor channel edge and toward the source region or the drain region.

Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.

A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit, a first metal layer, a second metal layer, and a third metal layer; connection of the first transistors comprises the first, and / or the second, and / or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines and at least four memory mini arrays which include at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; the memory control circuit includes first transistors and voltage regulators.

A semiconductor structure includes a field effect transistor having a plurality of source / drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source / drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source / drain region of the plurality of source / drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source / drain region to a backside interconnect structure disposed above the backside interlevel dielectric.

Disclosed is a method of forming gate structures for n-type and p-type transistors. The method includes: forming an interfacial layer and high-K (HK) dielectric layer for the gate structures; forming an n-type metal layer over the HK dielectric layer; forming a hard capping layer over the n-type metal layer while simultaneously strengthening the HK dielectric layer by fluorine passivation; patterning photo resist (PR) material over the hard capping layer that exposes a portion of the hard capping layer over the p-type transistor; removing the n-type metal layer and the hard capping layer over the p-type transistor via wet etching operations using high selectivity chemicals that are highly selective to the hard capping layer and the n-type metal layer; removing the patterned PR material while insulating, by the hard capping layer, gate structures from aluminum oxidation; and forming a p-type metal layer over the hard capping layer and the p-type transistor.

A method of the present disclosure includes forming a fin-shaped structure protruding from a substrate, depositing an isolation feature on sidewalls of the fin-shaped structure, forming a dummy gate stack over a portion of the fin-shaped structure, removing a portion of the dummy gate stack to form a trench exposing the portion of the fin-shaped structure, recessing the portion of the fin-shaped structure to extend the trench downward below a top surface of the isolation feature, depositing a first dielectric layer in the trench, recessing the first dielectric layer, such that a topmost portion of the first dielectric layer is below the top surface of the isolation feature, after the recessing of the first dielectric layer, depositing a second dielectric layer in the trench, the first and second dielectric layers including different material compositions, and replacing an unremoved portion of the dummy gate stack with a metal gate structure.

Provided is a multi-stack semiconductor device that includes: a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower gate dielectric layer, a lower work-function metal layer and a lower gate metal pattern; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper gate dielectric layer, an upper work-function metal layer and an upper gate metal pattern, wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure, and wherein a replacement metal gate (RMG) inner spacer is formed between the lower work-function metal layer and the upper work-function metal layer at regions where the lower channel structure is not vertically overlapped by the upper channel structure.

A memory device and a method for forming the same. The memory device includes a semiconductor substrate having a plurality of active regions separated by a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction, a third trench extending in the first direction in the semiconductor substrate at the bottom of the first trenches, bit line doped regions in the semiconductor substrate on both sides of the third trench, a gate dielectric layer on the sidewalls of the first and second trenches, a first dielectric layer filling the third trench, metal gates in the first trenches on the first dielectric layer and in the second trenches, the metal gates in the second trenches being broken in the second direction, source regions on the top surface of the active regions, and capacitors on the surface of the semiconductor substrate connected to the source regions. The memory device of the present invention has improved storage density.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, and forming a dummy gate and a hard mask layer on the substrate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer by adopting a first planarization process; performing first plasma modification treatment, and at least forming a first modified layer on the surface of the interlayer dielectric layer; second plasma modification processing is carried out, and at least the hard mask layer and a part of the contact hole etching stop layer are modified into a second modified layer; synchronously removing the first modified layer and the second modified layer, and exposing the dummy gate; and removing the dummy gate to form a metal gate. According to the invention, residual metal in the interlayer dielectric layer is avoided, the height consistency of the metal gate is improved, and the reliability of the semiconductor device is improved.

A semiconductor device comprises a semiconductor layer structure, a gate pad on the semiconductor layer structure, and a metal gate runner on the semiconductor layer structure. The metal gate runner comprises an inner gate runner that comprises a first inner segment and a second inner segment that interconnect at a first oblique angle.

The invention discloses a metal gate device structure manufacturing method and a metal gate device structure. The metal gate device structure manufacturing method comprises the steps of forming a fin part on a substrate; sequentially forming a gate dielectric layer and a cap layer on the surface of the fin part; forming a sacrificial and buffer layer on the surface of the cap layer, then performing heat treatment to enable atoms in the sacrificial and buffer layer material to diffuse into the cap layer material so as to improve the diffusion barrier capability of the cap layer, and then removing the sacrificial and buffer layer; sequentially forming a work function layer and a gate electrode layer on the surface of the cap layer after the sacrificial and buffer layers are removed, wherein the work function layer comprises a plurality of work function material layers which are sequentially stacked from inside to outside; wherein the surfaces of one or more inner-layer work function material layers formed before the outermost work function material layer are subjected to oxidation treatment respectively, so that the rough surfaces of the inner-layer work function material layers are leveled, interface diffusion is inhibited, and the stability of threshold voltage is improved.

Gate stacks for stacked device structures, such as stacked transistors, and methods of fabrication thereof are disclosed. An exemplary method includes forming a semiconductor layer stack over a substrate. The semiconductor layer stack includes a first semiconductor layer disposed over a second semiconductor layer. The method further includes forming a first type metal gate layer around the second semiconductor layer. The method further includes, after forming an aluminum-containing isolation layer over the first type metal gate layer, forming a second type metal gate layer around the first semiconductor layer and over the aluminum-containing isolation layer. In some embodiments, the method further includes removing a native metal oxide layer from over the first type metal gate layer before forming the aluminum-containing isolation layer. In some embodiments, removing the native metal oxide layer from over the first type metal gate layer includes performing a chlorine-based gas treatment.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

Integrated circuit structures having combined links for uniform grid metal gate and trench contact cut are described. A structure includes a dielectric sidewall spacer between a gate electrode and a conductive trench contact. First and second parallel dielectric cut plug structures extend through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The first dielectric cut plug has a first recess laterally adjacent to first and second portions of the gate electrode. The second dielectric cut plug has a second recess laterally adjacent to first and second portions of the conductive trench contact. A conductive link is in the first recess, in the second recess, and continuous between the first recess and the second recess.

The utility model relates to the technical field of vacuum electronics, in particular to a trapezoidal staggered gate slow-wave structure of a circular electron beam channel, which comprises a metal shell, trapezoidal upper metal gates and trapezoidal lower metal gates which are symmetrically arranged in a staggered manner are arranged in the metal shell, and the upper metal gates and the lower metal gates are respectively provided with arc-shaped concave holes; along the electron transmission direction, the concave holes respectively penetrate through the upper metal gate and the lower metal gate, and the upper and lower concave holes are enclosed to form a circular electron beam channel. Through the slow-wave structure, the bandwidth of the slow-wave structure can be increased, so that the longitudinal electric field in the slow-wave structure is enhanced.

Integrated circuit structures having internal spacer-last for uniform grid metal gate and trench contact cut are described. A structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An internal spacer liner is intervening laterally between the internal gate spacer and the gate structure.

A fabrication method, includes: forming a gate spacer layer around a sacrificial gate structure disposed over a substrate; performing, on a first material layer that includes the gate spacer layer, treatment operations that are configured to make the first material layer more resistant to Germanium (Ge) diffusion during metal gate replacement operations; forming a second material layer adjacent to the first material layer; and replacing the sacrificial gate structure with a metal gate, wherein the first material layer blocks Ge from entering the metal gate.

The invention provides a method for realizing a multi-valued addressing device through a dual-gate ferroelectric field effect transistor, and relates to the technical field of addressing devices, and the method comprises the steps: preparing a top metal gate, a bottom metal gate, a channel and an MFIS laminated structure, and obtaining a dual-gate ferroelectric field effect transistor structural material; constructing a bigrid ferroelectric field effect transistor structure, and entering a pMOS type working mode through the bigrid ferroelectric field effect transistor; performing voltage control adjustment on the top metal gate and the bottom metal gate according to the bigate ferroelectric field effect transistor structure to obtain control judgment information; by controlling the sum of the voltages of the top metal gate and the bottom metal gate, voltage scanning is carried out, addressing points are obtained, then the multi-valued addressing function is obtained, the multi-valued addressing device function is achieved only through the single double-gate ferroelectric field effect transistor, and occupied space and processing resources are greatly saved.

A method for manufacturing a semiconductor structure includes: depositing atomic layers of tin monoxide along a vertical direction; patterning the atomic layers of tin monoxide into a channel unit; forming a first conducting oxide unit that is connected to the channel unit; forming a second conducting oxide unit that is connected to the channel unit and that is spaced apart from the first conducting oxide unit so as to permit charge carriers to be transmitted between the first conducting oxide unit and the second conducting oxide unit through the patterned atomic layers in the channel unit along the vertical direction; forming a gate dielectric over the channel unit, the first and second conducting oxide units; forming a metal gate over the gate dielectric; recessing the metal gate to expose the gate dielectric; and partially removing the gate dielectric to expose at least the first conducting oxide unit.

Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

The application provides an inverse-conducting insulated gate bipolar transistor and a preparation method thereof, and belongs to the technical field of power semiconductor devices, and comprises: a first groove is a gate groove, a second groove is an emitter groove, and a third groove is an ineffective gate groove; in the lateral direction parallel to the cell surface, the first groove, the second groove and the third groove are sequentially and spacedly arranged, and the first groove and the second groove are connected through a fourth groove, and the fourth groove is a gate groove; in the longitudinal direction, the second groove is located between two adjacent fourth grooves. The beneficial effects are as follows: the gate groove and the ineffective gate groove are connected through the lateral gate groove, the forward conduction voltage drop and the conduction loss of the device are reduced; the current channel is increased, the current distribution is more uniform, the heat loss is reduced, the reliability and the power density of the device are improved; the emitter groove is used for repeatedly arranging the polysilicon gate and the metal gate in the lateral and longitudinal directions, the regularly arranged diodes and Schottky diodes are formed, and the reverse diode current distribution is more uniform.

The present disclosure relates to integrated circuit devices and methods of manufacturing the same. Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of a multi-gate device from one another prior to forming the multi-gate device, and in particular prior to forming the metal gates of the multi-gate device. An exemplary device includes a first multi-gate device having first source / drain features and a first metal gate surrounding a first channel layer, and a second multi-gate device having second source / drain features and a second metal gate surrounding a second channel layer. A gate isolation fin separating the first metal gate and the second metal gate includes a dielectric feature having a first dielectric layer (e.g., a low-k dielectric core) having a first dielectric constant, and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

A semiconductor device comprises a substrate, a metal gate over the substrate, a poly gate over the substrate, and a source region and a drain region formed in the substrate. The poly gate is separated from the metal gate. The metal gate comprises a metal gate stack and first spacers on sidewalls of the metal gate stack, and the poly gate comprises a poly gate stack and second spacers on sidewalls of the poly gate stack. The poly gate is between the source region and the drain region.

The invention discloses a metal gate device structure and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a fin part on a substrate; forming a work function layer comprising a plurality of work function material layers which are sequentially stacked from inside to outside on the surface of the fin part; wherein the surfaces of one or more inner work function material layers formed before the outermost work function material layer are subjected to nitriding treatment by using nitrogen free radicals excited by metastable state particles so as to regulate and control the nitrogen content of the surfaces of the inner work function material layers; then oxygen free radicals excited by metastable state particles are used for oxidation treatment, so that the surface roughness of the inner work function material layer is reduced, and nitrogen loss is prevented; and the outermost work function material layer comprises a TiAlC layer. According to the invention, an electrical path with stable threshold voltage can be improved, the long-term stability of the threshold voltage is enhanced, and the work function and the threshold voltage of the transistor can be regulated and controlled more finely and stably.