1174 results about "Metal gate" patented technology

The invention relates to a manufacturing method of a high dielectric layer metal gate device, and relates to the field of integrated circuits. The manufacturing method comprises the steps that a substrate is provided, the substrate comprises active regions and isolation structures, and the isolation structures and the active regions are arranged at intervals; the substrate is provided with a first region and a second region, the active region protrudes out of the isolation structure to form a first fin part in the first region, and a second fin part is formed in the second region; forming a first work function layer to cover the first fin part and the second fin part; free radicals generated by exciting the first gas through the metastable state particles are in contact with the surface of the first work function layer, and free dangling bonds on the surface of the first work function layer are removed; forming a second work function layer on the first work function layer; etching to remove the second work function layer on the first fin part; and the surface of the first work function layer is treated by free radicals generated by exciting the second gas through the metastable state particles. The problem of material loss of the first work function layer when devices with different threshold voltages are formed on the same substrate is solved.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a double diffusion region between a first dummy metal gate and a second dummy metal gate; a frontside metal wire conductively connected to a top surface of the deep trench via through a frontside via; and a backside metal wire conductively connected to a bottom surface of the deep trench via through a backside via and a backside contact, where the frontside metal wire and the backside metal wire are not vertically aligned but parallel to each other, and directions of the frontside and backside metal wires are orthogonal to a length direction of the deep trench via. A method of forming the same is also provided.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the pseudo gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer; oxidizing the hard mask layer, a part of the contact hole etching stop layer and a part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and a part of the interlayer dielectric layer, wherein the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on the two sides; and removing the dummy gate to form a metal gate. According to the manufacturing method of the semiconductor device provided by the invention, the height of the formed metal gate can be ensured, the manufacturing process is simple, and the controllability is high.

Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.

A semiconductor device and methods for forming the semiconductor device are described. The semiconductor device can include a top transistor and a bottom transistor arranged in a stack configuration, and an isolation layer situated between the top transistor and the bottom transistor. The top transistor can be encompassed by a high-k gate dielectric. The bottom transistor can be encompassed by a metal-doped high-k gate dielectric. A first portion of the isolation layer can be encompassed by the high-k gate dielectric. A second portion of the isolation layer can be encompassed by the metal-doped high-k gate dielectric. The metal-doped high-k gate dielectric can encompass the bottom transistor and the second portion of the isolation layer can be encompassed by a layer of first work function material (WFM). The first WFM can be encompassed by a second WFM.

In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

The invention discloses a gate dielectric film growth process, an HEMT (High Electron Mobility Transistor) device and a preparation method, and the gate dielectric film growth process comprises the steps: executing a primary process cycle of atomic layer deposition, and forming an amorphous gate dielectric film on the surface of a substrate; after the primary process circulation is completed, in-situ gas plasma treatment is executed, a single crystal gate dielectric film converted from the amorphous gate dielectric film after treatment is obtained, and when the single crystal gate dielectric film is formed between a metal gate and a barrier layer of the HEMT device, the interface state of the metal gate at a gate groove can be improved, the quality of a contact interface below gate metal is improved, and the performance of the HEMT device is improved. And the defect density and the electron trapping effect are reduced, so that the problems of serious influence on safe operation of the device and even grid degradation caused by grid leakage and threshold voltage drift after stress of the device can be effectively avoided, and the performance of the device is improved.

An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming an n-type work function layer in a gate trench in a gate structure, wherein the n-type work function layer is formed around first channel layers in a p-type gate region and around second channel layers in an n-type gate region, forming a first metal fill layer in a first gate trench over the n-type work function layer in the p-type gate region and in a second gate trench over the n-type work function layer in the n-type gate region, removing the first metal fill layer from the p-type gate region, removing the n-type work function layer from the p-type gate region, forming a p-type work function layer in the first gate trench of the p-type gate region, and forming a second metal fill layer in the first gate trench of the p-type gate region.

The invention relates to the technical field of solar cell manufacturing, and discloses a method for electroplating copper and tin grid lines on a solar cell, which comprises the following steps of: S1, copper electroplating: putting a cell piece on an electroplating tool, and putting the cell piece into a copper liquid tank for electroplating copper layers on a P surface and an N surface; wherein a very-low-frequency power supply is adopted. And S2, cleaning the copper liquid on the battery piece. S3, tin electroplating: the battery piece after the copper liquid is cleaned is placed in a tin liquid tank for electroplating tin layers on the P surface and the N surface; wherein a very-low-frequency power supply is adopted. And S4, cleaning the tin liquid on the battery piece. And S5, the cleaned battery piece is taken out, and grid line electroplating is completed. The very-low-frequency power supply is used for replacing a silicon controlled rectifier direct-current power supply, and self-developed voltage and current parameters are matched, so that the compactness and the conductivity of the HDT high-efficiency single-crystal heterojunction solar cell on an electroplated metal grid line film layer are improved, and the conversion efficiency of a cell piece is improved.

A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.

The present disclosure is directed to method for the fabrication of spacer structures between source / drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.

A semiconductor fabrication method includes: providing a separating wall and a plurality of liners including a first liner and a second liner between a first fin and a second fin having an epitaxial stack and a sacrificial gate stack over channel regions of the second fin; recessing a sacrificial epitaxial layer of the epitaxial stack to form a cavity; recessing the first line thereby expanding the cavity; recessing the second liner thereby expanding the cavity; forming inner spacer material in the first and second cavities; forming source / drain features; and replacing the sacrificial epitaxial layer and the sacrificial gate stack with a metal gate layer; wherein the metal gate layer has a first critical dimension (CD) measured between the inner spacer material, and wherein the first liner after recessing has a second CD measured between the inner spacer material that is approximately equal to the first CD.

The invention provides a metal gate and a preparation method thereof, and the preparation method comprises the steps: depositing a first metal material, carrying out the dry etching of the first metal material in a second part of a groove, removing a protrusion, enlarging the size of an opening of the groove, and filling a second metal material to form the metal gate, thereby solving a gap defect in the metal gate, and improving the reliability of the metal gate. According to the invention, the stability of the metal gate can be improved, and the difference of pattern loading (pattern loading effect) can be reduced.

The invention provides an enhanced HEMT (High Electron Mobility Transistor) device based on a P-type GaN grid electrode and a manufacturing method, a superlattice pair insertion layer is formed in a P-type GaN layer, the superlattice pair insertion layer comprises a first sub-layer and a second sub-layer which are alternately stacked, one of the first sub-layer and the second sub-layer adopts a GaN layer, and the forbidden bandwidth of the other layer is greater than 3.4 eV; by arranging the superlattice pair insertion layer, an electron barrier can be formed in the P-type GaN layer, and electrons can be prevented from moving in the gate structure, so that gate electric leakage is reduced, meanwhile, the electrons are prevented from crossing the gate structure to bombard the metal gate, and the gate reliability is improved; meanwhile, due to the fact that the ultra-thin superlattice material and the material with the forbidden bandwidth larger than 3.4 eV are AlN, BN, AlGaN, InAlN or BGaN, the dielectric constant of the material is very close to that of a GaN-based material, and therefore the gate capacitance and the threshold voltage of the device cannot be increased.

A trenched, vertical MOS-gated switch is described that uses only three or four masking steps to fabricate. In one embodiment, one mask is used to form first trenches having a first depth, wherein the first trenches are filled with doped polysilicon to form gates to control the conduction of the switch. A second mask is used to form second trenches having a shallower second depth. The second trenches are filled with the same metal used to form the top source electrode and gate electrode. The metal filling the second trenches electrically contacts a top source layer and a body region. A third mask is used to etch the metal to define the source metal, the gate electrode, and floating rings in a termination region surrounding the active area of the switch. An additional mask may be used to form third trenches in the termination region that are deeper than the first trenches.

The invention discloses a power device with a drain electrode led out from the front side and a manufacturing method thereof, the power device comprises a substrate, an epitaxial layer and an isolation layer, and the power device is divided into a gate contact region, an active region, a terminal region and a terminal peripheral region along the horizontal direction; gate metal is arranged on the isolation layer of the gate contact region and is connected with the gate interconnection structure; source electrode metal is arranged on the isolation layer of the active region and is connected with the source region; the terminal region is provided with a voltage-withstanding ring and a cut-off ring structure, the isolation layer of the terminal peripheral region is provided with drain electrode metal, and the drain electrode metal is connected with the first injection region of the terminal peripheral region. According to the invention, the drain electrode metal of the power device is changed into the terminal peripheral area arranged on the front surface of the power device, so that the source electrode metal, the drain electrode metal and the grid electrode metal of the power device are all located on the same plane, the demand of clip materials can be effectively reduced, the performance of the power device can be improved, and the parasitic effect can be reduced.

A gate all around (GAA) field effect transistor (GAA FET) is described. The GAA FET includes a substrate, having a nanosheet structure on the substrate. The GAA FET also includes a source / drain (SD) region in the substrate and coupled to a first end of the nanosheet structure. The GAA FET further includes a drain / source (DS) region in the substrate and coupled to a second end opposite the first end of the nanosheet structure. The GAA FET also includes a metal gate on the nanosheet structure to define channels between the source / drain region and the drain / source region. The GAA FET further includes a trench oxide blocking a bottom channel of the channels.

A 3D semiconductor device including: a first level including a first single crystal layer and a memory control circuit including first transistors and control circuit connectivity provided by first, second, and third metal layers; a second level including second transistors (one which includes a metal gate) disposed atop the first level; third transistors disposed atop second transistors with a fourth metal layer disposed atop; a memory array including word-lines, the memory array includes at least four memory mini arrays, where each mini array includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second or third transistors; a connection path from the fourth metal to the third or second metal layer, which includes a via disposed through the second level, and where the memory control circuit includes at least one power down control circuit.

Devices with isolated metal structures and methods of fabrication are provided. A method for isolating a metal gate includes forming a gate line over a semiconductor substrate; patterning a mask over the gate line, wherein an opening in the mask is located over a region of the gate line to be removed; performing an etching process through the opening to form a trench; and forming an isolation feature in the trench, wherein the isolation feature is selectively formed with no air gap, with a small air gap, or with a full air gap.

The invention relates to the technical field of semiconductor manufacturing, and discloses an MOS (Metal Oxide Semiconductor) tube gate forming system adopting a high-K metal gate. A material deposition regulation and control module of the system analyzes the matching degree of deposition uniformity and thickness stability and generates a material deposition control parameter set; an interface processing optimization module adjusts the cavity interface processing balance based on the parameter set, and generates an interface processing optimization parameter set; the gate forming control module adjusts metal gate deposition parameters accordingly, and generates a gate forming regulation and control result; a parameter calibration intervention module dynamically adjusts parameters based on the result, and generates a calibration intervention adjustment data set; and the quality verification promotion module optimizes preparation path parameters according to the parameters and generates a quality verification data table. According to the system, through cooperative work of all the modules, accurate control over the whole preparation process of the MOS transistor grid electrode is achieved, the thickness uniformity, defect control capacity and electrical performance stability of the grid electrode are effectively improved, and the manufacturing requirements of high-precision semiconductor devices are met.

Embodiments of the present invention advantageously provide a method of manufacturing a semiconductor device having multiple threshold voltage capability in a scaled space between nanosheets in an advanced GAA node. One or more embodiments provide an integration scheme to advantageously reduce gate resistance by incorporating n- / p-dipoles with an intermediate bandgap metal with low resistance to achieve a desired work function and low resistance metal gate. In one or more embodiments, the intermediate bandgap metal is used to fill the nanosheets and as a liner for subsequent filling with the low resistance metal. After dipole processing, instead of filling surrounding gate nanosheets with conventional n or p metals, in one or more embodiments, the nanosheets are advantageously filled with a single work function intermediate energy gap metal to achieve n and p work functions. If the work function is shifted in either of the band edges of the P-dipole or the N-dipole after dipole processing, the intermediate bandgap material may also shift the band edges in the opposite manner.

The invention discloses a solar cell and a preparation method thereof and a solar cell module, the solar cell comprises a silicon substrate, the solar cell is provided with a metal grid line contact area and a non-metal grid line contact area, a plurality of hollowed-out grooves arranged in an array are formed in the non-metal grid line contact area, and the metal grid line contact area is connected with the non-metal grid line contact area. And each hollow groove sequentially penetrates through the passivation layer, the poly layer and the dielectric layer on the back surface of the silicon substrate in the thickness direction of the solar cell. According to the solar cell provided by the invention, the use amount of Poly-Si materials in the areas where the hollowed-out grooves are formed can be effectively reduced through the plurality of hollowed-out grooves formed in the array in the non-metal grid line contact area, so that parasitic absorption is effectively reduced, the photoelectric conversion efficiency is improved, and the photoelectric conversion efficiency is improved. As the whole surface of the solar cell does not need to be subjected to laser treatment, the thermal damage risk of the solar cell is reduced.

Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source / drain region; a tungsten (W) cap formed from W material deposited over the metal gate and between the gate spacers; and a via gate (VG) formed above the W cap. A semiconductor fabrication method includes: receiving a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source / drain region; depositing tungsten (W) material over the substrate; removing unwanted W material to form a W cap; and forming a via gate (VG) on the W cap.

A semiconductor structure includes a bottom field effect transistor (FET) module, the bottom FET module including a bottom metal gate, a pair of bottom source / drain (S / D) contacts, and a top FET module on the bottom FET module in a second direction that is orthogonal to the first direction, the top FET module including a top metal gate, a pair of top S / D contacts, and a top-to-bottom interconnect extending through the bottom FET module and the top FET module in the second direction, a bottom liner covering surfaces of the top-to-bottom interconnect along a plane parallel to the first direction and the second direction, and a top liner covering surfaces of the top-to-bottom interconnect along a plane orthogonal to the first direction.

A semiconductor structure includes a substrate, plurality of active channels, a metal gate, a plurality of inner spacers and a first isolation layer. The substrate has an upper surface and a recess recessed relative to the upper surface. The active channels are vertically stacked on the upper surface of the substrate. The metal gate is disposed on the active channels. The inner spacers are disposed on a lateral surface of the metal gate. The first isolation layer is disposed within the recess and connected with the bottommost inner spacer. The first isolation layer protrudes relative to the upper surface of the substrate.

A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source / drains. Lower ends of the plurality of contact plugs may contact the plurality of source / drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

A string driver device is described in this disclosure. The string driver device includes a semiconductor channel disposed in an upper portion of a semiconductor substrate and a gate dielectric layer disposed above the semiconductor channel. The string driver device also includes a source region and a drain region disposed at opposite sides of the semiconductor channel, each of the source region and the drain region having a corresponding contact disposed thereon. The string driver device further includes a gate that is disposed above the gate dielectric layer and has a first length, and a field plate layer disposed above the gate, the field plate layer having a second length larger than the first length of the gate, wherein the field plate layer includes one or more edge regions extending across the semiconductor channel edge and toward the source region or the drain region.

A memory device and a method of forming the same, the memory device comprising: a semiconductor substrate, a plurality of active regions formed in the semiconductor substrate, the plurality of active regions separated by a plurality of first trenches extending in a first direction, a plurality of second trenches, and a plurality of third trenches extending in a second direction; a bit line doping region in the semiconductor substrate at a bottom of the second trenches and at a bottom of the second trenches communicating with the third trenches; a first isolation layer in the first trenches and the third trenches, a surface of the first isolation layer being lower than a surface of the active regions; a gate dielectric layer surrounding the active regions at the surface of the active regions; a metal gate surrounding the active regions at a surface of the gate dielectric layer on a sidewall of the active regions, a top surface of the metal gate being lower than a top surface of the active regions; and a source region at the top surface of the active regions. The memory device of the present application has improved storage density.

A semiconductor structure includes an epitaxial feature disposed in an active region, a frontside contact disposed directly above and in electrical coupling with the epitaxial feature, a metal gate stack, an inner spacer interposing the metal gate stack and the epitaxial feature, and a backside contact in physical contact with a bottom portion of the metal gate stack and in physical contact with a bottom portion of the frontside contact.