112 results about "Metal gate" patented technology

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

The application provides an inverse-conducting insulated gate bipolar transistor and a preparation method thereof, and belongs to the technical field of power semiconductor devices, and comprises: a first groove is a gate groove, a second groove is an emitter groove, and a third groove is an ineffective gate groove; in the lateral direction parallel to the cell surface, the first groove, the second groove and the third groove are sequentially and spacedly arranged, and the first groove and the second groove are connected through a fourth groove, and the fourth groove is a gate groove; in the longitudinal direction, the second groove is located between two adjacent fourth grooves. The beneficial effects are as follows: the gate groove and the ineffective gate groove are connected through the lateral gate groove, the forward conduction voltage drop and the conduction loss of the device are reduced; the current channel is increased, the current distribution is more uniform, the heat loss is reduced, the reliability and the power density of the device are improved; the emitter groove is used for repeatedly arranging the polysilicon gate and the metal gate in the lateral and longitudinal directions, the regularly arranged diodes and Schottky diodes are formed, and the reverse diode current distribution is more uniform.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

This application provides a method for improving the performance stability of a metal gate device, comprising: step one, providing a substrate, forming an interlayer dielectric layer on the substrate, and forming trenches in the interlayer dielectric layer; step two, forming a first work function metal layer in the trenches; step three, forming a second work function metal layer in the trenches located in the NMOS region of the substrate; step four, forming a titanium nitride barrier layer covering the second work function metal layer; step five, hydrogen treating the titanium nitride barrier layer to reduce the chlorine content of the titanium nitride barrier layer; and step six, forming a metal gate in the trenches. According to this application, the chlorine content of titanium nitride in the metal gate device can be significantly reduced, thereby significantly improving the performance stability of the metal gate device.

Disclosed examples include microelectronic devices, e.g., integrated circuits and methods of making such devices. One example includes a microelectronic device including a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS transistor may include a high-k gate dielectric and a metal gate. The (LDMOS) transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region towards the drain region and field plate conductor layers that extend from the drain region towards the source region with gate dielectric layers and field relief dielectric layers separating the gate conductor layers from the field plate conductor layers.

The application discloses a metal gate device structure and a manufacturing method thereof, comprising: forming a fin on a substrate; forming a work function layer comprising a plurality of layers of work function material stacked in order from inside to outside on the surface of the fin; wherein the surface of one or more layers of inner work function material layer formed before the outermost layer of work function material layer is first subjected to nitriding treatment by using metastable particle excited nitrogen radicals respectively to regulate the surface nitrogen content of the inner work function material layer, and then subjected to oxidation treatment by using metastable particle excited oxygen radicals respectively to reduce the surface roughness of the inner work function material layer and prevent nitrogen loss; the outermost layer of work function material layer comprises a TiAlC layer. The application can improve the electrical path of threshold voltage stability, enhance the long-term stability of threshold voltage, and realize more precise and stable regulation of the work function and threshold voltage of the transistor.

A method includes forming top semiconductor channels for a top device over bottom semiconductor channels for a bottom device; forming a high-k gate dielectric layer wrapping around each of the top and the bottom semiconductor channels; forming a first gate metal over the high-k gate dielectric layer; etching back the first gate metal to expose top portions of the high-k gate dielectric layer while bottom portions of the high-k gate dielectric layer remain, wherein the etching back includes dry etching to etch the first gate metal and to generate a co-polymer byproduct that covers the exposed top portions of the high-k gate dielectric layer; and performing a post-cleaning process to remove the co-polymer byproduct, the post-cleaning process comprising a first wet cleaning to remove silicon oxide components of the co-polymer byproduct and a second wet cleaning to remove metal oxide components of the co-polymer byproduct.

Provided is a plasma processing method capable of achieving flat etching process while suppressing vertical etching.The plasma processing method for plasma-etching a titanium nitride (TiN) film that forms a metal gate and contacts an insulating film on both sides includes the step of etching the titanium nitride (TiN) film by using plasmas that are generated by using a mixed gas of boron trichloride (BCl3) gas, nitrogen (N2) gas, and nitrogen trifluoride (NF3) gas and are generated by radio-frequency power modulated by a pulse, wherein the pulse has a first period with a first amplitude as its amplitude and a second period with a second amplitude as its amplitude and wherein the second amplitude is greater than 0 and less than the first amplitude.

A field-effect transistor (FET) structure and a method for manufacturing the same are disclosed. In one aspect, the FET structure includes: a gate structure extending in a first horizontal direction and disposed between a first source / drain (S / D) epitaxial layer (EPI) structure and a second S / D EPI structure separated in a second horizontal direction. The FET structure further includes: a back-side interlayer dielectric (ILD) layer disposed below a vertical metal gate structure and the first and second S / D EPI structures. The first S / D EPI structure includes a lower portion extending vertically below the bottom surface of the vertical metal gate structure and into the back-side ILD layer, the lower portion including side surfaces and a bottom surface. At least the bottom surface of the lower portion is electrically coupled to a back-side contact, such as an elongated trench contact or an extended contact island extending in the second horizontal direction.

A method of forming a semiconductor structure includes forming a fin over a semiconductor substrate, forming an isolation region on sidewalls of the fin, forming a metal gate over the fin and the isolation region, etching the metal gate to form a trench through the isolation region, passivating the top portion of the semiconductor substrate exposed in the trench to form a dielectric layer at a bottom of the trench, and depositing a dielectric material in the trench to form a dielectric structure. The dielectric structure divides the metal gate into two sections.

A method for manufacturing a semiconductor structure includes: forming a nanosheet stack which includes sacrificial layers and channel layers; forming a gate structure; removing two stack portions of the nanosheet stack to form two source / drain recesses so that the channel layers and the sacrificial layers are respectively formed into channel features and sacrificial features; forming two source / drain portions respectively in the two source / drain recesses; removing a dummy gate of the gate structure and the sacrificial features; and forming a gate electrode which is disposed between the two source / drain portions and around the channel features, the gate electrode including an electrode material and a stressor material different from the electrode material so that a lattice distance in the channel features after forming the gate electrode is different from a lattice distance in the channel features prior to forming the gate electrode.

This disclosure relates to a high-k / metal-gate LDMOS nanosheet device. Examples of the disclosure include a microelectronic device (100) and a method of manufacturing such a device. One example includes a nanosheet laterally diffused metal-oxide-semiconductor (LDMOS) transistor (101). The LDMOS transistor (101) may include a gate dielectric (136) of a high-k material and a metal gate (137). The LDMOS transistor (101) includes a source (141) and a drain (151) extending into a semiconductor substrate (104). A nanosheet region (116) extends between the source (141) and the drain (151). A nanosheet channel layer (135c) alternates with a metal gate layer (137) extending from the source (141) to the drain (151). A nanosheet drain drift layer (138) alternates with a field plate conductor layer (147) extending from the drain (151) to the source (141).

The application relates to the technical field of semiconductor storage, and discloses a 3D chain ferroelectric storage array structure and a preparation method thereof. The 3D chain ferroelectric storage array structure comprises an alternating medium stack as a base body, a horizontal cavity formed through wet etching, a ring channel transistor prepared in the cavity and surrounding a vertical bit line, and a storage unit formed by integrating a ferroelectric capacitor. The vertical bit line serves as a source-drain electrode, and a horizontal metal gate forms a word line, so that a three-dimensional stacked structure is realized. The preparation process of the application is compatible with the existing NAND process, the gate control capability is effectively improved, the short channel effect is inhibited, and the storage density and the device reliability are improved.

Integrated circuit structures with a uniform grid-metal gate and trench contact interface for cFET architectures are described. In one example, a structure comprises a first vertical stack of horizontal nanowires above a second vertical stack of horizontal nanowires, with an intermediate insulator structure positioned vertically between the first and second vertical stacks. A gate structure is located above the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires, and the intermediate insulator structure. A conductive trench contact is adjacent to the gate structure. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact.The first and second dielectric cut plug structures extend through the gate structure, through the dielectric sidewall spacer, and through the conductive trench contact.

Integrated circuit structures having uniform grid metal gate and trench contact cut for cFET architectures are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires, with an intervening insulator structure vertically between the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires. A gate structure is over the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires, and the intervening insulator structure. A conductive trench contact is adjacent to the gate structure. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. First and second dielectric cut plug structures are extending through the gate structure, through the dielectric sidewall spacer, and through the conductive trench contact.

A fabricating method for a transistor with a fin structure and a nanosheet begins by providing a first fin structure with a dummy gate, two spacers, a first embed epitaxial layer, and a second embed epitaxial layer. Subsequently, a first epitaxial layer and a second epitaxial layer are formed to cover the fin structure and the dummy gate. Two first mask layers are then formed. Parts of the first and the second epitaxial layers are removed using the two first mask layers as a mask to expose the dummy gate and a nanosheet is formed from the remaining second epitaxial layer. Later, the dummy gate is replaced by a first gate portion, and a second gate portion is formed to encapsulate the nanosheet. Finally, a metal gate is formed between the first gate portion and the second gate portion.

The present application discloses a method for improving the defects of ultra-low leakage device after chemical mechanical polishing, the ultra-low leakage device adopts tungsten gate, and the thickness of tungsten layer deposited before chemical mechanical polishing is less than 2000 angstroms. The present application adopts tungsten metal gate instead of traditional aluminum metal gate, which can greatly reduce the resistance, and at the same time, provides positive pressure for the gate, which can effectively improve the performance of NMOS device. Meanwhile, the present application adjusts and controls the thickness of tungsten deposition of tungsten metal gate, which can significantly reduce the total number of defects of tungsten metal gate after chemical mechanical polishing, so that the tungsten residue is within the process allowable range, which effectively expands the window of chemical mechanical polishing defects of tungsten metal gate.

A semiconductor device includes a semiconductor channel. The semiconductor device includes a metal gate structure disposed over the semiconductor channel. The semiconductor device includes a gate electrode having a bottom surface contacting an upper surface of the metal gate structure. The gate electrode has its side portions extending from its top surface toward the semiconductor fin with a first depth and a central portion extending from its top surface toward the semiconductor fin with a second depth, the first depth being substantially greater than the second depth.

A phase change material switch includes a phase change layer disposed on a metal liner. A gate dielectric layer is disposed on the phase change layer. A metal gate liner is disposed on the gate dielectric layer.

Integrated circuit structures with a uniform lattice-metal gate and trench contact with jogs are described. In one example, a structure features a first vertical stack of horizontal nanowires or a first fin. A first gate electrode is located above the first vertical stack of horizontal nanowires or the first fin. The integrated circuit structure also features a second vertical stack of horizontal nanowires or a second fin. A second gate electrode is located above the second vertical stack of horizontal nanowires or the second fin. A conductive trench contact is located between the first and second gate electrodes.A dielectric cut-plug structure extends through the first gate electrode, through the conductive trench contact, and through the second gate structure, wherein the dielectric cut-plug structure has a width adjacent to the first gate electrode that is greater than a width adjacent to the second gate electrode.

A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

This disclosure provides a photosensitive device and an imaging apparatus. The photosensitive device disclosed herein includes: a silicon substrate; an insulating material body disposed on the silicon substrate; a photosensitive material layer disposed on the insulating material body, wherein the photosensitive material layer generates photogenerated carriers when photoexcited; a metal source, a metal drain, and a metal gate, all disposed within the insulating material body; a metal gate dielectric layer and a channel layer, wherein the metal gate dielectric layer covers the metal gate and the channel layer covers the metal gate dielectric layer; the metal source and the metal drain are spaced apart on the side of the channel layer away from the metal gate; a photosensitive material filling portion is filled in the gap between the metal source and the metal drain, and the photosensitive material filling portion and the photosensitive material layer are integrally structured; a photosensitive gate dielectric layer and a carrier collection layer, wherein the photosensitive gate dielectric layer covers the channel layer and the carrier collection layer covers the photosensitive gate dielectric layer; the carrier collection layer is used to collect photogenerated carriers, and the photosensitive gate dielectric layer is used to ensure that the photosensitive material filling portion and the channel layer do not interfere with each other in realizing their respective functions, and the photosensitive material filling portion and the channel layer are combined to form a complete phototransistor.

A semiconductor device includes a first channel region above a substrate, a first metal gate structure engaging the first channel region, a first gate sidewall spacer disposed on sidewalls of the first metal gate structure, a second channel region above the substrate, a second metal gate structure engaging the second channel region, a second gate sidewall spacer disposed on sidewalls of the second metal gate structure, a first interposing feature disposed adjacent to the first channel region, a first epitaxial feature disposed on the first interposing feature and abutting the first channel region, a second interposing feature disposed adjacent to the second channel region, and a second epitaxial feature disposed on the second interposing feature and abutting the second channel region. A bottom surface of the second epitaxial feature is above a bottom surface of the first epitaxial feature.

The integrated circuit includes a complementary field-effect transistor (CFET). The CFET includes a first transistor comprising a first source / drain region pair and a plurality of stacked first channels extending in a first lateral direction between the first source / drain region pair. The CFET includes a second transistor located above the first transistor, and the second transistor includes a second source / drain region pair and a plurality of stacked second channels extending in the first lateral direction between the second source / drain region pairs. The CFET includes a gate spacer layer defining a gate trench adjacent to the second channels and gate metal located in the gate trench and between the second channels. The gate metal has a first length in the gate trench in the first lateral direction and a second length in the first lateral direction between the second channels. The first length is greater than the second length. Embodiments of this application also relate to semiconductor devices and methods of forming the same.

The present disclosure relates to a semiconductor structure for a 3D DRAM comprising one 1T1C memory cell architecture and vertical bit lines. The semiconductor structure comprises a stack of semiconductor layers and dielectric layers alternatingly arranged along a first axis. Further, a first and second pillar of memory cells arranged displaced along a second axis and extending along the first axis through the stack. Each memory cell comprises a part of one of the semiconductor layers, and one transistor structure and one capacitor with a semiconductor channel and a metal gate that at least partly surrounds the semiconductor channel. The metal gates of memory cells in the same pillar are isolated from each other, and metal gates of memory cells that comprise parts of the same semiconductor layer form an integral metal structure.

Memory cells, semiconductor devices, semiconductor stacked structures, and fabrication methods are provided. An example memory cell includes a capacitor and a transistor stacked over the capacitor in a compact configuration. The capacitor includes a floating gate, a high-k dielectric layer, and a metal gate. The metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. The transistor includes the metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on the two sidewalls of the metal gate and, and a top portion disposed on the top surface of the metal gate. The transistor further includes two separate S / D regions respectively formed on the two side portions of the gate dielectric layer, and a channel region formed on the top portion of the gate dielectric layer.

The application discloses a kind of semiconductor device technical field, specifically for a kind of split gate trench MOSFET, including device cell unit, the device cell unit includes first conductive type substrate and first conductive type drift region on first conductive type substrate, second conductive type well region is equipped in the upper portion of first conductive type drift region, first conductive type drift region is opened with dielectric slot and gate precipitate slot communicated with dielectric slot, and dielectric slot is filled with high-K oxide, the gate precipitate slot is filled with precipitate gate metal gate, oxide layer one coated on precipitate gate metal gate, precipitate gate silicon carbide coated on oxide layer, silicon carbide is used as the abutment between high-K oxide and precipitate gate metal gate in the application, silicon carbide can ensure the thermal stability of itself and silicon, to prevent the interaction between existing precipitate gate metal gate and high-k gate oxide layer from influencing threshold, to improve the performance of nanometer size MOSFET.

The present disclosure relates to seam filling of metal gates with Si-containing layers. A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source / drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work function layer over the gate dielectric layer. The work function layer includes a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, excess portions of the work function layer, and excess portions of the gate dielectric layer. Remaining portions of the silicon-containing layer, remaining portions of the work function layer, and remaining portions of the gate dielectric layer form a gate stack.

A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit, a first metal layer, a second metal layer, and a third metal layer; connection of the first transistors comprises the first, and / or the second, and / or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines and at least four memory mini arrays which include at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; the memory control circuit includes first transistors and voltage regulators.