1234 results about "Work function" patented technology

The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. In one embodiment, a method for processing a substrate is provided which includes depositing a dielectric material having a dielectric constant greater than 10, forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MX_Y, wherein M is tantalum, hafnium, titanium, and lanthanum, X is a halide selected from the group of fluorine, chlorine, bromine, or iodine, and y is from 3 to 5.

Methods for forming a semiconductor device and related semiconductor device structures are provided. In some embodiments, methods may include forming an NMOS gate dielectric and a PMOS gate dielectric over a substrate and forming a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. In some embodiments, methods may also include, removing the first work function metal over the NMOS gate dielectric and forming a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. In some embodiments, related semiconductor device structures may include an NMOS gate dielectric and a PMOS gate dielectric disposed over a semiconductor substrate. A PMOS gate electrode may be disposed over the PMOS gate dielectric and the PMOS gate electrode may include a first work function metal disposed over the PMOS gate dielectric and a second work function metal disposed over the first work function metal. A NMOS gate electrode may be disposed over the NMOS gate dielectric and the NMOS gate electrode may include the second work function metal.

A process (200) for making integrated circuits with a gate, uses a doped precursor (124, 126N and/or 126P) on barrier material (118) on gate dielectric (116). The process (200) involves totally consuming (271) the doped precursor (124, 126N and/or 126P) thereby driving dopants (126N and/or 126P) from the doped precursor (124) into the barrier material (118). An integrated circuit has a gate dielectric (116), a doped metallic barrier material (118, 126N and/or 126P) on the gate dielectric (116), and metal silicide (180) on the metallic barrier material (118). Other integrated circuits, transistors, systems and processes of manufacture are disclosed.

A gate structure of a semiconductor device having a NFET and a PFET, includes a lower layer of a hafnium-based dielectric over the gates of the NFET and PFET, and an upper layer of a lanthanide dielectric. The dielectrics are annealed to mix them above the NFET resulting in a lowered work function, and corresponding threshold voltage reduction. An annealed, relatively thick titanium nitride cap over the mixed dielectric above the NFET gate also lowers the work function and threshold voltage. Above the TiN cap and the hafnium-based dielectric over the PFET gate, is another layer of titanium nitride that has not been annealed. A conducting layer of tungsten covers the structure.

Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.

According to some embodiments, an electrode have a high effective work function is formed. The electrode may be the gate electrode of a transistor and may be formed on a high-k gate dielectric by depositing a first layer of conductive material, exposing that first layer to a hydrogen-containing gas, and depositing a second layer of conductive material over the first layer. The first layer may be deposited using a non-plasma process in which the substrate is not exposed to plasma or plasma-generated radicals. The hydrogen-containing gas to which the first layer is exposed may include an excited hydrogen species, which may be part of a hydrogen-containing plasma, and may be hydrogen-containing radicals. The first layer may also be exposed to oxygen before depositing the second layer. The work function of the gate electrode in the gate stack may be about 5 eV or higher in some embodiments.

An organic light emitting device structure includes a substrate, a first electrically conductive layer formed over the substrate wherein the first electrically conductive layer has a positive polarity, and a transparent organic light emitting device formed over the first electrically conductive layer. The structure also includes a transparent electrically conductive metal layer formed over the transparent organic light emitting device wherein the metal has a work function less than 4 eV, and a second electrically conductive layer formed over the transparent electrically conductive metal layer, wherein the second electrically conductive layer has a negative polarity, and wherein the second electrically conductive layer comprises a material selected from the group consisting of a transparent electrically conductive oxide and a transparent electrically conductive polymer.

This invention provides a semiconductor device having a field effect transistor comprising agate electrode comprising a metal nitride layer and a polycrystalline silicon layer, and the gate electrode is excellent in thermal stability and realizes a desired work function.

In the semiconductor device, a gate insulating film 6 on a silicon substrate 5 has a high-permittivity insulating film formed of a metal oxide, a metal silicate, a metal oxide introduced with nitrogen, or a metal silicate introduced with nitrogen,

• • the gate electrode has a first metal nitride layer 7 provided on the gate insulating film 6 and containing Ti and N, a second metal nitride layer 8 containing Ti and N, and a polycrystalline silicon layer 9,
  • in the first metal nitride layer 7, a molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X₁ is 1.1<X₁<1.8, and
  • in the second metal nitride layer 8, the molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X₂ is 1.8≦X₂.

Systems, methods and devices for the remote control of a robot which incorporates interchangeable tool heads. Although applicable to many different industries, the core structure of the system includes a robot with a tool head interface for mechanically, electrically and operatively interconnecting a plurality of interchangeable tool heads to perform various work functions. The robot and tool head may include several levels of digital feedback (local, remote and wide area) depending on the application. The systems include a single umbilical cord to send power, air, and communications signals between the robot and a remote computer. Additionally, all communication (including video) is preferably sent in a digital format. Finally, a GUI running on the remote computer automatically queries and identifies all of the various devices on the network and automatically configures its user options to parallel the installed devices. Systems according to the preferred embodiments find particular application in the pipeline arts. For example, interchangeable tool heads may be designed to facilitate inspection, debris clearing, cleaning, relining, lateral cutting after relining, mapping, and various other common pipeline-related tasks.

The present invention relates to high sensitivity chemical sensors, more particularly relates to high sensitivity chemical sensors which are capacitively coupled, FET based analyte sensors. A sub-threshold capacitively coupled Field Effect Transistor (CapFET) sensor for sensing an analyte comprises fixed dielectric placed on substrate of the CapFET and second dielectric sensitive to the analyte, placed between gate terminal of the CapFET and the fixed dielectric, wherein presence of the analyte alters either dielectric constant of the second dielectric or work function of the gate.

A metal/semiconductor/metal (MSM) back-to-back Schottky diode, a resistance memory device using the MSM diode, and associated fabrication processes are provided. The method includes: providing a substrate; forming a metal bottom electrode overlying the substrate, having a first work function; forming a semiconductor layer overlying the metal bottom electrode, having a second work function, less than the first work function; and, forming a metal top electrode overlying the semiconductor layer, having a third work function, greater than the second work function. The metal top and bottom electrodes can be materials such as Pt, Au, Ag, TiN, Ta, Ru, or TaN. In one aspect, the metal top electrode and metal bottom electrode are made from the same material and, therefore, have identical work functions. The semiconductor layer can be a material such as amorphous silicon (a:Si), polycrystalline Si, InOx, or ZnO.

The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel region in an n-type substrate. A floating gate opposing the p-type channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, Nb₂O₅, SrBi₂Ta₂O₃, SrTiO₃, PbTiO₃, and PbZrO₃. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer, having a different work function from the metal layer formed on the floating gate, formed thereon in contact with the low tunnel barrier intergate insulator.

Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes the control gate for programming and erasure through a band engineered crested tunnel barrier. Charge retention is enhanced by utilization of high work function nano-crystals in a non-conductive trapping layer and a high K dielectric charge blocking layer. The band-gap engineered gate-stack with symmetric or asymmetric crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.

Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, Nb₂O₅, SrBi₂Ta₂O₃, SrTiO₃, PbTiO₃, and PbZrO₃. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer, having a different work function from the metal layer formed on the floating gate, formed thereon in contact with the low tunnel barrier intergate insulator.

The invention has an object of providing an organic electroluminescence element with a large emitted light quantity, an exposure unit and an image-forming apparatus both using the element. The organic electroluminescence element in accordance with the invention has, on a substrate, an anode acting as a hole injection electrode, a cathode acting as an electron injection electrode, a plurality of light emission layers each having a light emission region and a charge generation layer injecting electrons into the light emission layer lying close to the anode and injecting holes into the light emission layer lying close to the cathode, these layers being arranged between the anode and the cathode, and is configured so that the work function of the charge generation layer is set higher than the ionization potential of the light emission layer lying close to the anode.

A method forms a gate stack for a semiconductor device with a desired work function of the gate electrode. The work function is adjusted by changing the overall electronegativity of the gate electrode material in the region that determines the work function of the gate electrode during the gate electrode deposition. The gate stack is deposited by an atomic layer deposition type process and the overall electronegativity of the gate electrode is tuned by introducing at least one pulse of an additional precursor to selected deposition cycles of the gate electrode. The tuning of the work function of the gate electrode can be done not only by introducing additional material into the gate electrode, but also by utilizing the effects of a graded mode deposition and thickness variations of the lower gate part of the gate electrode in combination with the effects that the incorporation of the additional material pulses offers.

Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

Device are described that include a semiconductor material layer and at least one graphene-based electrode disposed over a portion of the semiconductor material layer, such that the at least one graphene-based electrode forms an overlap region with the semiconductor material layer. The device includes a means for providing charge carriers in the at least one graphene-based electrode proximate to the overlap region, to reduce a difference between a work function of the at least one graphene-based electrode and an electron affinity of the semiconductor material layer, to reduce a Schottky barrier height between the semiconductor material layer and the at least one graphene-based electrode.

Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or form a part of, the gate electrode in a transistor. Methods of forming a gate electrode using these transition metal alloys are also disclosed.

A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping

Methods and systems for depositing vanadium and/or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and/or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and/or indium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures. The vanadium and/or indium layers can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate includes a ternary metallic conductor formed by atomic layer deposition.

Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.

An OLED device including a cathode, an anode, one or more light-emitting layers disposed between the anode and cathode to produce white light and a layer disposed between the light-emitting layer(s) and the cathode. The layer includes a polycyclic aromatic hydrocarbon compound that has the lowest LUMO value of the compounds in the layer, in an amount greater than or equal to 10% by volume and less than 100% by volume of the layer; at least one second compound exhibiting a higher LUMO value than the polycyclic aromatic hydrocarbon compound, where at least one of the second compounds is a low voltage electron-transporting material, and the total amount of such second compounds(s) is less than or equal to 90% by volume of the layer; and a metallic material based on a metal having a work function less than 4.2 eV.

A method of forming transistors and structures thereof. A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n type dopant. The NMOS device may be doped with either an n type or a p type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided.

A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.