67 results about "Work function" patented technology

The invention discloses a preparation process of a high-performance Cu-Ni-Fe alloy calculated and designed based on a first principle, and relates to the technical field of alloy material preparation. According to the process, a precise Cu-Ni-Fe ternary alloy thermodynamic database is constructed by combining a first principle with a CALPHAD method, a multivariate phase diagram is calculated based on the database to determine a component range, then optimized components of a work function, an elastic constant and a thermal expansion coefficient are calculated through the first principle, and a finished product is obtained through smelting, heat treatment and forming machining. The final alloy is composed of, by atomic percent, 30%-75% of Cu, 10%-30% of Ni and 10%-30% of Fe, the tensile strength is larger than or equal to 816.4 MPa, the total elongation at break is larger than or equal to 34.27%, the thermal expansion coefficient is smaller than 20 * 10 <-6 > / K, the excellent mechanical property and thermal stability are achieved, the problems that component design is blind and performance fluctuation is large in a traditional process are solved, and the alloy is suitable for the fields of ocean engineering, electronic packaging and the like.

The invention relates to a heterogeneous insulation interface parameter testing method and device based on broad-spectrum photoelectric emission, and the method comprises the steps: applying metal electrodes with different work functions to to-be-tested samples of two single-layer materials forming heterogeneous insulation, and obtaining a single-layer material photoelectric emission current spectrum; analyzing the photoelectric emission current spectrums of the single-layer materials to obtain parameters of the two single-layer materials forming heterogeneous insulation; applying metal electrodes with different work functions to a heterogeneous insulation composite sample formed by tightly attaching two single-layer materials forming heterogeneous insulation to obtain a total photoelectric emission current spectrum of the heterogeneous insulation composite sample; separating according to the total photoelectric emission current spectrum of the heterogeneous insulation composite sample to obtain an intermediate interface photoelectric emission current spectrum; and analyzing the photoelectric emission current spectrum of the intermediate interface, and calculating to obtain a real contact potential barrier between the two single-layer materials forming the heterogeneous insulation. Compared with the prior art, high-precision measurement of heterogeneous insulation interface parameters is realized.

The invention discloses a metal gate device structure and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a fin part on a substrate; forming a work function layer comprising a plurality of work function material layers which are sequentially stacked from inside to outside on the surface of the fin part; wherein the surfaces of one or more inner work function material layers formed before the outermost work function material layer are subjected to nitriding treatment by using nitrogen free radicals excited by metastable state particles so as to regulate and control the nitrogen content of the surfaces of the inner work function material layers; then oxygen free radicals excited by metastable state particles are used for oxidation treatment, so that the surface roughness of the inner work function material layer is reduced, and nitrogen loss is prevented; and the outermost work function material layer comprises a TiAlC layer. According to the invention, an electrical path with stable threshold voltage can be improved, the long-term stability of the threshold voltage is enhanced, and the work function and the threshold voltage of the transistor can be regulated and controlled more finely and stably.

The invention discloses an online in-situ characterization method of a chemical mechanical polishing through silicon via heterostructure, and belongs to the technical field of chip manufacturing. According to the TSV heterostructure sample, through the remarkable difference of different components of a TSV heterostructure sample matrix, an insulating layer, a barrier layer and a transmission layer in refractive index, work function and conductivity, a PiFM is taken as a core, a KPFM and a CAFM are combined, and the TSV heterostructure sample can be detected on the same platform by detecting light induction force, surface potential and current signals at a needle tip-sample position. And the real-time in-situ measurement of the TSV sample surface appearance height, roughness and interface component change is realized. According to the method, the light, electricity and force response differences between TSV heterostructure materials are fully utilized, dynamic feedback of the structure morphology and components in the CMP process is achieved, and support is provided for nano-scale and even atomic-scale polishing precision control.

Methods and systems for depositing vanadium and / or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and / or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and / or indium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures. The vanadium and / or indium layers can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

The present application belongs to the technical field of semiconductor, and particularly relates to a gate structure containing an effective work function adjustable work function metal layer and a preparation method thereof. The gate structure comprises a semiconductor substrate, a gate dielectric layer, a work function metal layer, and the material of the work function metal layer is TiAlC. The work function metal layer is changed in density so that the effective work function of the metal is regulated to the effective work function required by the target threshold voltage, and other gate layers. In the process of forming the work function metal layer on the gate dielectric layer, the work function metal layer with different densities is obtained through different process conditions, so that the effective work function of the metal is regulated to the effective work function required by the target threshold voltage. The different process conditions include the pretreatment process of the gate dielectric layer and / or the deposition process of the work function metal layer. The present application only needs one layer of work function metal layer to realize the regulation of the threshold voltage, meets the multi-threshold voltage device, avoids the complex process of other work function regulation methods, and reduces the manufacturing cost.

The application discloses a metal gate device structure and a manufacturing method thereof, comprising: forming a fin on a substrate; forming a work function layer comprising a plurality of layers of work function material stacked in order from inside to outside on the surface of the fin; wherein the surface of one or more layers of inner work function material layer formed before the outermost layer of work function material layer is first subjected to nitriding treatment by using metastable particle excited nitrogen radicals respectively to regulate the surface nitrogen content of the inner work function material layer, and then subjected to oxidation treatment by using metastable particle excited oxygen radicals respectively to reduce the surface roughness of the inner work function material layer and prevent nitrogen loss; the outermost layer of work function material layer comprises a TiAlC layer. The application can improve the electrical path of threshold voltage stability, enhance the long-term stability of threshold voltage, and realize more precise and stable regulation of the work function and threshold voltage of the transistor.

A method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a fin standing on the substrate, along the extension direction of the fin, the fin includes a channel region, the channel region is used to form a stacked work function layer; forming a gate dielectric layer conformally covering the top and sidewall of the fin in the channel region; forming a first work function layer conformally covering the gate dielectric layer in the channel region; forming a filling layer on the first work function layer between adjacent fins, the filling layer exposes at least the first work function layer on the top of the fin, the Fermi level of the material of the filling layer is closer to the Fermi level of the fin than the Fermi level of the material of the stacked work function layer; forming a second work function layer covering the first work function layer and the filling layer, the second work function layer and the first work function layer are used to constitute the stacked work function layer. The second work function layer is located on the top of the first work function layer and the filling layer, which reduces the probability of generating void defects in the second work function layer and improves the uniformity of the threshold voltage of the device.

The invention discloses a two-dimensional ferroelectric vertical heterojunction self-powered X-ray synapse transistor and a manufacturing method thereof, and belongs to the field of X-ray synapse transistors, the two-dimensional ferroelectric vertical heterojunction self-powered X-ray synapse transistor comprises a substrate, the substrate is provided with a bottom layer, a ferroelectric functional layer and a top layer which are stacked in sequence, the bottom layer is connected with a first electrode, and the top layer is connected with a second electrode. The bottom layer and the top layer are independently made of a two-dimensional semi-metal material, the ferroelectric functional layer comprises a two-dimensional ferroelectric material, the bottom layer is not in contact with the top layer, and the work function of the bottom layer is not equal to that of the top layer. According to the invention, a built-in electric field induced by ferroelectric polarization is combined, self-powered X-ray detection under zero bias voltage is realized, synaptic enhancement or inhibition can be realized through bias voltage regulation and control if X-ray pulse is taken as a stimulation signal, and short-term or long-term synaptic plasticity can be simulated. The device is simple in preparation process and excellent in stability, can be widely applied to the fields of medical diagnosis, security check screening, radiation monitoring and intelligent sensing, and provides core technical support for a'detection-synapse 'integrated device.

The invention discloses an HKMG gate work function adjusting process method. The HKMG gate work function adjusting process method comprises the steps of 1, forming an interface layer and a high dielectric constant layer on a semiconductor substrate; and 2, forming a lanthanum oxide layer on the top surface of the high dielectric constant layer. And step 3, performing graphical etching on the lanthanum oxide layer to remove the lanthanum oxide layer outside the first region and retain the lanthanum oxide layer of the first region, wherein the outside of the first region is a region which does not need to reduce the work function of the grid electrode. 4, annealing is carried out to push lanthanum into the high dielectric constant layer, after lanthanum is pushed into the high dielectric constant layer, an electric dipole is formed at the interface of the high dielectric constant layer and the interface layer, and the grid work function of the first area is reduced through the electric dipole. And step 5, removing the residual lanthanum oxide layer. According to the invention, a threshold voltage adjusting process window can be expanded, so that the threshold voltage is matched with a target value to the greatest extent and the device performance is improved.

This invention discloses a MoSe2 / C heterostructure electromagnetic wave absorbing material and its preparation method, addressing the challenges of poor impedance matching, singular loss mechanisms, and limited bandwidth in traditional absorbing materials. The material is synthesized from MoSe2 nanosheets and carbon materials via a solvothermal method, with precise control of the interface electronic structure achieved through the introduction of heteroatoms such as N, P, F, Cl, or Br. Benefiting from the built-in electric field formed by the difference in work function between MoSe2 and carbon, and the Fermi level shift induced by heteroatomation, this material achieves bidirectional control of polarization loss and efficient absorption of broadband electromagnetic waves. Furthermore, the heterostructure interface between MoSe2 and carbon is constructed in situ via a one-step solvothermal method, avoiding interface contamination problems in traditional multi-step synthesis and ensuring structural stability and reproducibility.

The application discloses a preparation process of a high-performance Cu-Ni-Fe alloy based on first-principle calculation design, and relates to the technical field of alloy material preparation. The process constructs a precise Cu-Ni-Fe ternary alloy thermodynamic database by combining a first principle with a CALPHAD method, determines a composition range based on database calculation of a multivariate phase diagram, optimizes the composition by calculating a work function, an elastic constant and a thermal expansion coefficient through a first principle, and obtains a finished product through smelting, heat treatment and forming processing. The final alloy has an atomic percentage composition of Cu 30%-75%, Ni 10%-30% and Fe 10%-30%, a tensile strength of greater than or equal to 816.4 MPa, a total elongation at break of greater than or equal to 34.27%, and a thermal expansion coefficient of less than 20*10 ‑6 / K, and has excellent mechanical properties and thermal stability, thereby solving the problems of blind composition design and large performance fluctuation of a traditional process and being suitable for multiple fields such as ocean engineering and electronic packaging.

A method for forming a III-nitride semiconductor device involves determining work functions of a first III-nitride contact layer and a first metal contact. The determined work function of the first III-nitride contact layer is based on a group III element of the first III-nitride contact layer. Based on the determined work functions of the first III-nitride contact layer and of the first metal contact, it is determined that the work function of the first III-nitride contact layer should be adjusted. The III-nitride semiconductor device is formed including the first III-nitride contact layer adjacent to a second III-nitride contact layer, the first metal contact arranged on the first III-nitride contact layer, and a second metal contact arranged on the second III-nitride contact layer. The first III-nitride contact layer of the formed III-nitride semiconductor device is a boron nitride alloy having an amount of boron that adjusts the work function of the first III-nitride contact layer relative to the determined work function of the first metal layer based on the group III element of the first III-nitride contact layer.

The application provides a semiconductor device manufacturing method, which is applied to the technical field of semiconductor technology.The application comprises the following steps: providing a substrate with first conductive type doping ions, forming a deep trench in the substrate, forming a doping region with second conductive type doping ions in the part of the substrate below the deep trench, and forming a metal silicide layer at the bottom of the deep trench; thus, by combining the formation of the metal silicide layer at the bottom of the deep trench and the formation of the doping region in the part of the substrate below the deep trench, the characteristics of forming ohmic contact by the close work function of the metal silicide layer and the conductive layer can be achieved, the conduction between the conductive layer and the metal silicide layer can be realized, the carrier concentration in the substrate can be improved by the doping region, the characteristics of forming ohmic contact between the substrate with the improved carrier concentration and the metal silicide layer can be achieved, the conduction between the metal silicide layer and the substrate can be realized, and the same type or also type conduction between the conductive layer and the substrate can be realized.

A method for manufacturing an electron source according to the present disclosure includes steps of: (A) preparing a first member provided with a columnar portion made of a first material having an electron emission characteristic, (B) preparing a second member which has a higher work function and a lower strength than the first material, and in which a hole is formed extending in a direction from one end surface toward the other end surface, and (C) pushing the columnar portion into the hole in the second member, wherein the first member has a cross-sectional shape that is dissimilar to the cross-sectional shape of the hole; and in the step (C), by pressing the columnar portion into the hole, a portion of a side surface of the columnar portion scrapes the inner surface of the hole and bites into the second member, thereby fixing the columnar portion to the second member.

The invention provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors, and the method comprises the steps: providing a substrate structure which comprises a substrate; an interlayer dielectric layer on the substrate, the interlayer dielectric layer having at least one trench extending to the substrate, the at least one trench including a first trench for a PMOS device; a dielectric layer on the bottom and sidewalls of the first trench; and a P-type work function layer on the dielectric layer; forming a first N-type work function layer in the at least one groove; and after the first N-type work function layer is formed, a barrier layer and an electrode of the PMOS device are sequentially formed in the first groove, and elements in the barrier layer comprise titanium, nitrogen and silicon.

A kind of metastable phase rare earth nickel-based oxide hydrogen-induced electronic phase transition dynamics regulation method belongs to material science and electronic information field.Specific metal electrode is contacted with rare earth nickel-based oxide material with controllable shape, and is placed in acidic chemical environment, based on the difference between the work function of metal and rare earth nickel-based oxide material, transfer of hydrogen ion in chemical environment is driven, to realize the electronic configuration of rare earth nickel-based oxide material by controllable rate from the transition of three-valence nickel dominated delocalized electronic structure to divalent nickel dominated localized electronic structure, and trigger the increase of material resistivity at controllable rate;When specific metal electrode is contacted with rare earth nickel-based oxide material with controllable shape, and is placed in alkaline chemical environment, it will trigger the sharp decrease of material resistivity.The present application has high safety, low cost and energy saving;It can accurately control the degree and rate of hydrogen-induced phase transition to realize the detection of different acid-base concentration chemical environment.

The application discloses an aluminum alloy corrosion rate prediction method and device based on environment and micro characteristics, electronic equipment and storage medium, and belongs to the technical field of material corrosion protection. The method comprises the following steps: obtaining the service environment temperature, relative humidity, deposition rate of various surface pollutants and dominant pollutant type of a target aluminum alloy; matching the corresponding adsorption work function value in a preset micro adsorption work function list according to the dominant pollutant type to obtain a micro work function parameter representing the degree of difficulty of electron transfer; combining the temperature, humidity and pollutant deposition rate to construct a macro environment characteristic vector, and splicing the micro work function parameter to form a cross-scale fusion characteristic vector; and inputting the fusion characteristic vector into a corrosion rate prediction model to regress and output a corrosion rate prediction result. Through implementation of the application, the problem that the prediction accuracy encounters a bottleneck and the model generalization ability is weak due to the lack of micro bottom layer physical mechanism support of a pure data driven model in the prior art can be solved.

A force applied to a channel region of a semiconductor plate in a first direction relative to the semiconductor plate may generate a strain in a crystal structure that increases carrier mobility to increase drive strength in the channel region. In a three-dimensional (3D) FET structure (600), work function metal layers (616) are provided on opposing faces of semiconductor plates (e.g., nanosheets) such that forces are applied on channel regions (604 (1), (2), (3)) in a first direction corresponding to current flow. A gate dielectric (612) is present between the channel (604 (1), (2), (3)) and the work function metal layer, and furthermore, a gate metal (608) surrounds the channel, the gate dielectric, and the work function metal. According to the FET type (N or P) employing the semiconductor plate, the force in the first direction is a tensile force or a compressive force and is provided to generate a strain in the crystal structure of the semiconductor plate to improve carrier mobility in the channel region. Increasing carrier mobility in a channel region in a 3D FET structure increases the driving strength of the 3D FET, which saves area in an integrated circuit.

This invention provides a method for measuring the work function of metallic materials based on ultraviolet photoelectron yield spectra, belonging to the field of materials analysis technology. The method includes: determining the actual number of incident photons in the main optical path at a target wavelength, where the target wavelength belongs to the vacuum ultraviolet and near-ultraviolet bands; measuring the number of photoelectrons excited by the main optical path on the surface of the metal sample under test at the target wavelength; determining the ultraviolet photoelectron yield spectrum of the metal sample under test based on the actual number of incident photons and photoelectrons in the main optical path at multiple wavelengths; fitting the ultraviolet photoelectron yield spectrum of the metal sample under test based on the Fowler photoelectron emission theory model, and determining the value of the work function of the metallic material based on the fitting results. This invention can accurately analyze the nonlinear variation law of photoelectron yield near a threshold through a nonlinear fitting process, improving the accuracy of work function measurement, especially in complex material systems, exhibiting stronger adaptability and higher measurement accuracy.

Forces applied to the channel regions of semiconductor slabs in a first direction relative to the semiconductor slab, can create strains in the crystal structure that improve carrier mobility to improve drive strength in the channel region. In a three-dimensional (3D) FET structure, a work function metal layer is provided on opposing faces of semiconductor slabs to cause a force to be exerted on the channel regions in a first direction corresponding to current flow. The force in the first direction is either tensile force or compressive force, depending on a FET type (N or P) employing the semiconductor slab, and is provided to create strain in a crystalline structure of the semiconductor slab to improve carrier mobility in the channel region. Increasing carrier mobility in the channel regions in a 3D FET structure increases drive strength of the 3D FET, which saves area in an integrated circuit.

A method for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

A process for producing nanoclusters of silicon and / or germanium exhibiting a permanent magnetic and / or electric dipole moment for adjusting the work function of materials, for micro- and nano-electronics, for telecommunications, for “nano-ovens”, for organic electronics, for photoelectric devices, for catalytic reactions and for fractionation of water.

The present disclosure provides a semiconductor structure and a method for forming the same. The method includes: providing a substrate having a metal gate trench with a work function layer on the bottom and sidewalls of the metal gate trench; forming a diffusion barrier layer on the work function layer, including: performing a physical vapor deposition process with a negative bias power less than a preset power to form a first diffusion barrier sublayer on the work function layer at the bottom of the metal gate trench. The present disclosure can reduce the possibility of premature sealing.

The invention provides a work function metal boundary offset test structure and test method, the work function metal boundary offset test structure comprises: N groups of test units, each group of test units comprises: at least one MOS structure group, each MOS structure group comprises a first MOS structure and two second MOS structures different from the first MOS structure, the two second MOS structures are arranged on the two sides of the first MOS structure in a spaced mode. The first MOS structure and the second MOS structure form two work function metal boundaries; in the same group of test units, the work function metal boundaries on the same side have the same preset offset relative to the active region of the first MOS structure; in different groups of test units, work function metal boundaries on the same side have different preset offsets relative to an active region of the first MOS structure; n is an integer greater than or equal to 3. According to the invention, work function metal offset condition monitoring of a metal replacement gate technology and accurate measurement of an overlay error are realized.

Embodiments of the invention include forming a first transistor having first nanosheets, first dipole gate dielectric material being formed around the first nanosheets. An aspect includes forming a second transistor comprising second nanosheets, second dipole gate dielectric material being formed around the second nanosheets, the first and second transistors being in a vertical stack, a first spacing between the first nanosheets being different from a second spacing between the second nanosheets. An aspect includes forming a workfunction metal stack having a first workfunction metal and a second workfunction metal, the first and second workfunction metals being formed between the first nanosheets, the first workfunction metal being formed to pinch off in the second spacing between the second nanosheets such that the second workfunction metal is absent in the second spacing between the second nanosheets.

The present application provides a method for improving continuity of a work function thin film, forming a tunneling oxide layer on a substrate; forming an isolation layer on the tunneling oxide layer; forming a work function thin film on the isolation layer, the work function thin film serves as a floating gate in a semi-floating gate device to store charges and conduction electrons, performing a heat treatment on the tunneling oxide layer, the isolation layer and the work function layer, the isolation layer reacts with a surface of the tunneling oxide layer to form a dense barrier layer, the isolation layer reacts with O in the tunneling oxide layer to form a new tunneling oxide layer, the heat treatment lasts until the isolation layer is fully consumed, and the work function thin film remaining after the reaction uniformly covers an upper surface of the dense barrier layer.

Device with: a first group of nanostructures (66) on a substrate (50), wherein the first group of nanostructures (66) has a first channel region; a second group of nanostructures (66) on the substrate (50), wherein the second group of nanostructures has a second channel region; a dielectric gate layer (112) enclosing each of the first and second groups of nanostructures (66); a first work function setting layer (114A) on the dielectric gate layer (112) of the first group of nanostructures (66), wherein the first work function setting layer (114A) surrounds each of the first group of nanostructures (66) and the first work function setting layer (114A) has an n work function metal; an adhesive layer (114B) on the first work function setting layer (114A), wherein the adhesive layer (114B) encloses each of the first group of nanostructures, and the adhesive layer (114B) comprises titanium aluminum carbide, tantalum aluminum carbide or silicon-doped tantalum aluminum carbide; a protective layer (114F) between the first work function setting layer (114A) and the adhesive layer (114B) on the first group of nanostructures (66), wherein the protective layer (114F) surrounds each of the first group of nanostructures (66) and comprises amorphous silicon; wherein the adhesive layer (114B) fills a region between respective parts of the protective layer (114F) on adjacent nanostructures of the first group of nanostructures (66) and thus separates the respective parts of the protective layer (114F) on adjacent nanostructures of the first group of nanostructures (66); a second work function setting layer (114C, 114D) on the adhesive layer (114B) of the first group of nanostructures (66) and on the dielectric gate layer (112) of the second group of nanostructures (66), wherein the second work function setting layer (114C, 114D) has a p-work function metal and the p-work function metal is different from the n-work function metal; and a fill layer (114E) on the second exit work adjustment layer (114C, 114D).

An embodiment includes a device having nanostructures on a substrate, the nanostructures including a channel region. The device also includes a gate dielectric layer wrapping around each of the nanostructures. The device also includes a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a first n-type work function metal, aluminum, and carbon, the first n-type work function metal having a work function value less than titanium. The device also includes a glue layer on the first work function tuning layer. The device also includes and a fill layer on the glue layer.

A semiconductor device includes a plurality of fin structures disposed over a substrate and a work function alloy layer disposed over each fin structure of the plurality of fin structures. The plurality of fin structures includes a first fin structure and a second fin structure. A content of a first element in a first portion of the work function alloy layer, which portion is disposed over the first fin structure, is different from a content of the first element in a second portion of the work function alloy layer, which portion is disposed over the second fin structure.