180 results about "Work function" patented technology

The invention discloses a preparation process of a high-performance Cu-Ni-Fe alloy calculated and designed based on a first principle, and relates to the technical field of alloy material preparation. According to the process, a precise Cu-Ni-Fe ternary alloy thermodynamic database is constructed by combining a first principle with a CALPHAD method, a multivariate phase diagram is calculated based on the database to determine a component range, then optimized components of a work function, an elastic constant and a thermal expansion coefficient are calculated through the first principle, and a finished product is obtained through smelting, heat treatment and forming machining. The final alloy is composed of, by atomic percent, 30%-75% of Cu, 10%-30% of Ni and 10%-30% of Fe, the tensile strength is larger than or equal to 816.4 MPa, the total elongation at break is larger than or equal to 34.27%, the thermal expansion coefficient is smaller than 20 * 10 <-6 > / K, the excellent mechanical property and thermal stability are achieved, the problems that component design is blind and performance fluctuation is large in a traditional process are solved, and the alloy is suitable for the fields of ocean engineering, electronic packaging and the like.

The invention relates to a heterogeneous insulation interface parameter testing method and device based on broad-spectrum photoelectric emission, and the method comprises the steps: applying metal electrodes with different work functions to to-be-tested samples of two single-layer materials forming heterogeneous insulation, and obtaining a single-layer material photoelectric emission current spectrum; analyzing the photoelectric emission current spectrums of the single-layer materials to obtain parameters of the two single-layer materials forming heterogeneous insulation; applying metal electrodes with different work functions to a heterogeneous insulation composite sample formed by tightly attaching two single-layer materials forming heterogeneous insulation to obtain a total photoelectric emission current spectrum of the heterogeneous insulation composite sample; separating according to the total photoelectric emission current spectrum of the heterogeneous insulation composite sample to obtain an intermediate interface photoelectric emission current spectrum; and analyzing the photoelectric emission current spectrum of the intermediate interface, and calculating to obtain a real contact potential barrier between the two single-layer materials forming the heterogeneous insulation. Compared with the prior art, high-precision measurement of heterogeneous insulation interface parameters is realized.

The invention discloses a method for researching the corrosion resistance behavior of zinc alloy based on a first principle. The method comprises the following steps: firstly, retrieving a zinc primitive cell model from a material database and carrying out structure optimization; performing crystal face cutting, cell expansion and re-structure optimization to obtain a zinc plate model; then aluminum atom random replacement doping processing is carried out, and optimization is carried out to obtain a doping model; performing static self-consistent calculation to obtain surface energy, and screening out the most stable doping model; fixing two layers of atoms at the bottom of the most stable doping model, performing chloride ion adsorption calculation and structure optimization, and calculating adsorption energy to determine a most stable adsorption site; and finally, carrying out electronic structure calculation of state density and a work function, and representing the corrosion resistance of the zinc alloy. According to the method, a zinc alloy corrosion micromechanism is deeply analyzed, theoretical guidance is provided for component optimization and corrosion resistance improvement, and compared with a traditional experimental method, the research and development cost and time are remarkably reduced, the research efficiency is improved, and the method has important theoretical and practical application value.

The present invention discloses a method for evaluating and regulating the wear resistance of ductile iron based on the electronic work function, which relates to the technical fields of surface engineering and performance evaluation. The method includes collecting the electronic work function data and material characteristic data on the surface of ductile iron; extracting the characteristics of the electronic work function data to obtain the electronic work function characteristics; establishing a mathematical model based on the electronic work function characteristics to analyze the correlation between the electronic work function data and the material characteristic data; analyzing the relationship between the electronic work function characteristics and the wear resistance, and establishing a comprehensive evaluation model to evaluate the wear resistance of ductile iron. The present invention combines characterization techniques, complex data analysis methods and multivariate statistical models at the same time. It can not only deeply understand the connection between the electronic structure and macroscopic properties of materials, but also establish a comprehensive evaluation model to predict the wear resistance of ductile iron; this method guides the design of materials and the optimization of the production process.

There is provided a photoelectric conversion element, an imaging device, and an electronic apparatus that make it possible to improve a response speed. A first photoelectric conversion element (10) according to an embodiment of the present disclosure includes: a first electrode (11); a second electrode (16) disposed to be opposed to the first electrode (11); an organic layer (13) provided between the first electrode (11) and the second electrode (16) and including a hole-transporting material; a work function adjustment layer (15) provided between the second electrode (16) and the organic layer (13) and having an electron affinity or a work function larger than a work function of the first electrode (11); and an electron block layer (14) provided between the organic layer (13) and the work function adjustment layer (15) and having an anisotropic electric susceptibility of 413 or more or an intramolecular dipole moment of 1.84 debye or more.

The invention provides a gate annealing method for a ferroelectric transistor, and the method comprises the steps: forming an N / P well layer, a source electrode and a drain electrode on a substrate, and enabling the source electrode and the drain electrode to be formed at the two sides of the N / P well layer; through an atomic layer deposition process, ferroelectric materials are deposited in a grid region where a grid is to be formed, a ferroelectric layer is formed, titanium oxide is deposited on the surface of the ferroelectric layer to serve as a stress layer, amorphous silicon is deposited on the surface of the stress layer to serve as a sacrificial layer, and laser annealing treatment is carried out on the surface of the sacrificial layer to induce the ferroelectric layer to generate a ferroelectric phase. The stress layer provides stress for the ferroelectric layer to stabilize the ferroelectric phase; the sacrificial layer is removed, titanium nitride is deposited on the surface of the stress layer after laser annealing to serve as a work function layer, conductive metal is deposited on the work function layer to form a conductive layer, and the gate metal lamination layer is obtained. The invention further provides a gate structure obtained based on the gate annealing method and a ferroelectric transistor.

The invention provides a two-dimensional material solar hydrogen production efficiency prediction method and device based on machine learning. The method comprises the following steps: reading a non-magnetic hexagonal crystal system single-layer material in a database to construct an initial data set; for samples with complete labels in the data set, training a single-layer material band edge position prediction model by adopting a feature engineering and gradient boosting decision tree algorithm; next, predicting and complementing samples with missing labels by using the trained model so as to generate a complete data set and further construct heterojunction double layers; carrying out data enhancement on a heterojunction sample of literature investigation through a CVAE-GAN hybrid architecture, and optimizing a feature vector; then training the new model by adopting a random forest algorithm to realize accurate prediction of the band edge position of the previously constructed heterojunction; and finally, the heterojunction type is judged in combination with a work function and a band edge position, the solar hydrogen production efficiency is calculated in batches by utilizing a program, and a high-efficiency heterojunction material is screened out.

The invention discloses a metal gate device structure and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a fin part on a substrate; forming a work function layer comprising a plurality of work function material layers which are sequentially stacked from inside to outside on the surface of the fin part; wherein the surfaces of one or more inner work function material layers formed before the outermost work function material layer are subjected to nitriding treatment by using nitrogen free radicals excited by metastable state particles so as to regulate and control the nitrogen content of the surfaces of the inner work function material layers; then oxygen free radicals excited by metastable state particles are used for oxidation treatment, so that the surface roughness of the inner work function material layer is reduced, and nitrogen loss is prevented; and the outermost work function material layer comprises a TiAlC layer. According to the invention, an electrical path with stable threshold voltage can be improved, the long-term stability of the threshold voltage is enhanced, and the work function and the threshold voltage of the transistor can be regulated and controlled more finely and stably.

The invention discloses an online in-situ characterization method of a chemical mechanical polishing through silicon via heterostructure, and belongs to the technical field of chip manufacturing. According to the TSV heterostructure sample, through the remarkable difference of different components of a TSV heterostructure sample matrix, an insulating layer, a barrier layer and a transmission layer in refractive index, work function and conductivity, a PiFM is taken as a core, a KPFM and a CAFM are combined, and the TSV heterostructure sample can be detected on the same platform by detecting light induction force, surface potential and current signals at a needle tip-sample position. And the real-time in-situ measurement of the TSV sample surface appearance height, roughness and interface component change is realized. According to the method, the light, electricity and force response differences between TSV heterostructure materials are fully utilized, dynamic feedback of the structure morphology and components in the CMP process is achieved, and support is provided for nano-scale and even atomic-scale polishing precision control.

Methods and systems for depositing vanadium and / or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and / or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and / or indium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures. The vanadium and / or indium layers can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

In an embodiment, a device includes: a first nanostructure; a gate dielectric layer around the first nanostructure; a first p-type work function tuning layer on the gate dielectric layer; a dielectric barrier layer on the first p-type work function tuning layer; and a second p-type work function tuning layer on the dielectric barrier layer, the dielectric barrier layer being thinner than the first p-type work function tuning layer and the second p-type work function tuning layer.

Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.

A method and an apparatus for measuring an electrical property of a sample material are provided. In the method, an alternating voltage is applied to a piezoelectric ceramic so that a probe fixed on the piezoelectric ceramic vibrates above a surface of the sample material, a target contact potential difference between the probe and the sample material is measured, and a target amplitude of an induced alternating current generated due to the vibration of the probe above the surface of the sample material, a target work function of the surface of the sample material is determined according to the target contact potential difference and a determined work function of the probe, and a target charge density of the surface of the sample material is determined according to the target amplitude, the target contact potential difference, and a pre-stored target amplitude determination function for the induced alternating current.

The application relates to the technical field of photoelectric functional materials, in particular to an interface modification layer material and a synthesis method and application thereof. The interface modification layer material provided by the application increases the steric hindrance of the molecule by introducing a functional group at the para-position of the benzene ring in the BPhen molecular structure, and reduces the aggregation and crystallization of the molecule; the molecular weight of the synthesized phenanthroline derivative is large, the glass transition temperature is higher than that of BPhen, and the thermal stability of the material is better; the synthesized phenanthroline derivative exists in the form of ionized quaternary ammonium salt, the reactivity of the imine group in the molecular structure is weaker than that of BPhen or BCP, and the stability of the device is improved; and the synthesis method of the interface modification layer material provided by the application is simple, the yield is high, the purification is easy, the price is low, and the interface modification layer material can be prepared on a large scale. The interface modification layer material can be applied in a semiconductor photoelectric device, and is used as an electrode modification layer to reduce the electrode work function.

The present application belongs to the technical field of semiconductor, and particularly relates to a gate structure containing an effective work function adjustable work function metal layer and a preparation method thereof. The gate structure comprises a semiconductor substrate, a gate dielectric layer, a work function metal layer, and the material of the work function metal layer is TiAlC. The work function metal layer is changed in density so that the effective work function of the metal is regulated to the effective work function required by the target threshold voltage, and other gate layers. In the process of forming the work function metal layer on the gate dielectric layer, the work function metal layer with different densities is obtained through different process conditions, so that the effective work function of the metal is regulated to the effective work function required by the target threshold voltage. The different process conditions include the pretreatment process of the gate dielectric layer and / or the deposition process of the work function metal layer. The present application only needs one layer of work function metal layer to realize the regulation of the threshold voltage, meets the multi-threshold voltage device, avoids the complex process of other work function regulation methods, and reduces the manufacturing cost.

The present application relates to a manufacturing method of a high-k metal gate device, and relates to the field of integrated circuits. The manufacturing method includes: providing a substrate, the substrate including an active region and an isolation structure, the isolation structure and the active region being disposed at intervals; the substrate having a first region and a second region, the active region protruding from the isolation structure to form a first fin portion in the first region and a second fin portion in the second region; forming a first work function layer covering the first fin portion and the second fin portion; removing dangling bonds free on the surface of the first work function layer by contacting the surface of the first work function layer with free radicals generated by exciting a first gas with metastable particles; forming a second work function layer on the first work function layer; etching and removing the second work function layer on the first fin portion; treating the surface of the first work function layer with free radicals generated by exciting a second gas with metastable particles. To improve the problem of material loss of the first work function layer when devices with different threshold voltages are formed on the same substrate.

A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a vertical channel pattern on the bit line, a gate electrode adjacent to the vertical channel pattern in the first direction, a first work function adjustment pattern on the gate electrode, and a first contact on the vertical channel pattern. The first work function adjustment pattern is adjacent to one end of the vertical channel pattern in the first direction. The first work function adjustment pattern includes a metal material different from that of the gate electrode.

The application discloses a metal gate device structure and a manufacturing method thereof, comprising: forming a fin on a substrate; forming a work function layer comprising a plurality of layers of work function material stacked in order from inside to outside on the surface of the fin; wherein the surface of one or more layers of inner work function material layer formed before the outermost layer of work function material layer is first subjected to nitriding treatment by using metastable particle excited nitrogen radicals respectively to regulate the surface nitrogen content of the inner work function material layer, and then subjected to oxidation treatment by using metastable particle excited oxygen radicals respectively to reduce the surface roughness of the inner work function material layer and prevent nitrogen loss; the outermost layer of work function material layer comprises a TiAlC layer. The application can improve the electrical path of threshold voltage stability, enhance the long-term stability of threshold voltage, and realize more precise and stable regulation of the work function and threshold voltage of the transistor.

A method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a fin standing on the substrate, along the extension direction of the fin, the fin includes a channel region, the channel region is used to form a stacked work function layer; forming a gate dielectric layer conformally covering the top and sidewall of the fin in the channel region; forming a first work function layer conformally covering the gate dielectric layer in the channel region; forming a filling layer on the first work function layer between adjacent fins, the filling layer exposes at least the first work function layer on the top of the fin, the Fermi level of the material of the filling layer is closer to the Fermi level of the fin than the Fermi level of the material of the stacked work function layer; forming a second work function layer covering the first work function layer and the filling layer, the second work function layer and the first work function layer are used to constitute the stacked work function layer. The second work function layer is located on the top of the first work function layer and the filling layer, which reduces the probability of generating void defects in the second work function layer and improves the uniformity of the threshold voltage of the device.

The application discloses a method for rapidly developing amorphous thin film material with high fracture toughness, which comprises the following steps: depositing corresponding alloy elements on a substrate based on different element targets by using a physical vapor deposition co-sputtering method to obtain a sample library containing a plurality of amorphous thin films with different element compositions; performing potential test by using a Kelvin probe force microscope to characterize the surface potential distribution of each amorphous thin film in the sample library, and obtaining the surface potential difference of each amorphous thin film; calculating the surface electronic work function of each amorphous thin film by using the obtained surface potential difference; the composition of the amorphous thin film with the maximum electronic work function is the composition of the amorphous thin film with the maximum fracture toughness in the sample library, and the amorphous thin film material with high fracture toughness is developed according to the composition.

The present invention discloses a nano-vacuum optical mixer for regulating the work function of a transparent electrode and a preparation method thereof, belonging to the field of semiconductor photodetectors and millimeter wave / terahertz devices. The optical mixer includes a back electrode, a semiconductor layer, a nano-insulating layer, and a transparent electrode sequentially arranged from bottom to top; wherein the area occupied by the nano-insulating layer is smaller than that of the semiconductor layer and the transparent electrode, forming a nano-air channel; the transparent electrode can regulate the work function to achieve matching with the work function of the semiconductor layer. The present invention adopts a transparent electrode, which increases the utilization rate of incident light, thereby significantly improving the photocurrent and responsivity of the device; at the same time, by regulating the work function of the transparent electrode, the work functions of semiconductor layers with different doping types and concentrations can be matched, realizing effective regulation and optimization of the threshold voltage, photocurrent, and dark current.

The invention discloses a two-dimensional ferroelectric vertical heterojunction self-powered X-ray synapse transistor and a manufacturing method thereof, and belongs to the field of X-ray synapse transistors, the two-dimensional ferroelectric vertical heterojunction self-powered X-ray synapse transistor comprises a substrate, the substrate is provided with a bottom layer, a ferroelectric functional layer and a top layer which are stacked in sequence, the bottom layer is connected with a first electrode, and the top layer is connected with a second electrode. The bottom layer and the top layer are independently made of a two-dimensional semi-metal material, the ferroelectric functional layer comprises a two-dimensional ferroelectric material, the bottom layer is not in contact with the top layer, and the work function of the bottom layer is not equal to that of the top layer. According to the invention, a built-in electric field induced by ferroelectric polarization is combined, self-powered X-ray detection under zero bias voltage is realized, synaptic enhancement or inhibition can be realized through bias voltage regulation and control if X-ray pulse is taken as a stimulation signal, and short-term or long-term synaptic plasticity can be simulated. The device is simple in preparation process and excellent in stability, can be widely applied to the fields of medical diagnosis, security check screening, radiation monitoring and intelligent sensing, and provides core technical support for a'detection-synapse 'integrated device.

The present disclosure provides a semiconductor device and a method for manufacturing the same. The device includes: a substrate, in which spaced source regions and drain regions are included; a top surface of the substrate includes a gate structure located between the source regions and the drain regions, and the gate structure includes a gate dielectric layer, a composite work function layer, and a gate material layer sequentially stacked in a first direction away from the substrate. The composite work function layer at least includes a first work function adjustment structure and a second work function adjustment structure arranged in a second direction parallel to the substrate and having different work function values; wherein, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stack structures with different numbers of stacked layers in the first direction. By making the composite work function layer have different work function values in different regions in the lateral direction, the semiconductor device has different electric field resistance strengths in the lateral direction, thereby improving the breakdown voltage of the semiconductor device.

The invention discloses an HKMG gate work function adjusting process method. The HKMG gate work function adjusting process method comprises the steps of 1, forming an interface layer and a high dielectric constant layer on a semiconductor substrate; and 2, forming a lanthanum oxide layer on the top surface of the high dielectric constant layer. And step 3, performing graphical etching on the lanthanum oxide layer to remove the lanthanum oxide layer outside the first region and retain the lanthanum oxide layer of the first region, wherein the outside of the first region is a region which does not need to reduce the work function of the grid electrode. 4, annealing is carried out to push lanthanum into the high dielectric constant layer, after lanthanum is pushed into the high dielectric constant layer, an electric dipole is formed at the interface of the high dielectric constant layer and the interface layer, and the grid work function of the first area is reduced through the electric dipole. And step 5, removing the residual lanthanum oxide layer. According to the invention, a threshold voltage adjusting process window can be expanded, so that the threshold voltage is matched with a target value to the greatest extent and the device performance is improved.

This invention discloses a MoSe2 / C heterostructure electromagnetic wave absorbing material and its preparation method, addressing the challenges of poor impedance matching, singular loss mechanisms, and limited bandwidth in traditional absorbing materials. The material is synthesized from MoSe2 nanosheets and carbon materials via a solvothermal method, with precise control of the interface electronic structure achieved through the introduction of heteroatoms such as N, P, F, Cl, or Br. Benefiting from the built-in electric field formed by the difference in work function between MoSe2 and carbon, and the Fermi level shift induced by heteroatomation, this material achieves bidirectional control of polarization loss and efficient absorption of broadband electromagnetic waves. Furthermore, the heterostructure interface between MoSe2 and carbon is constructed in situ via a one-step solvothermal method, avoiding interface contamination problems in traditional multi-step synthesis and ensuring structural stability and reproducibility.

The embodiment of the invention discloses a method for regulating and controlling Rashba spin splitting in a WSeTe single layer, and the method comprises the steps: selecting single-layer WSeTe, and carrying out the structure optimization; determining a net intrinsic electric field direction through charge density difference and work function calculation; on the basis of energy band calculation containing / not containing spin orbit coupling, gamma point spin splitting is observed; verifying the characteristics of Rashba splitting according to the spin texture graph, and analyzing the main contribution of Rashba splitting according to the energy band projection graph; applying in-plane biaxial strain to regulate and control the Rashba splitting strength; applying a vertical electric field to regulate and control the Rashba splitting strength; and meanwhile, strain and an electric field are applied to regulate and control the Rashba splitting strength. In-plane biaxial strain and vertical electric field independent regulation and control and common regulation and control are selected, and the regulation and control means of Rashba spin splitting are added. By adopting the technical scheme of the invention, more effective strain electric field control is expected to be realized by reasonably designing the material symmetry and the energy band structure.

The application discloses a preparation process of a high-performance Cu-Ni-Fe alloy based on first-principle calculation design, and relates to the technical field of alloy material preparation. The process constructs a precise Cu-Ni-Fe ternary alloy thermodynamic database by combining a first principle with a CALPHAD method, determines a composition range based on database calculation of a multivariate phase diagram, optimizes the composition by calculating a work function, an elastic constant and a thermal expansion coefficient through a first principle, and obtains a finished product through smelting, heat treatment and forming processing. The final alloy has an atomic percentage composition of Cu 30%-75%, Ni 10%-30% and Fe 10%-30%, a tensile strength of greater than or equal to 816.4 MPa, a total elongation at break of greater than or equal to 34.27%, and a thermal expansion coefficient of less than 20*10 ‑6 / K, and has excellent mechanical properties and thermal stability, thereby solving the problems of blind composition design and large performance fluctuation of a traditional process and being suitable for multiple fields such as ocean engineering and electronic packaging.

A method for forming a III-nitride semiconductor device involves determining work functions of a first III-nitride contact layer and a first metal contact. The determined work function of the first III-nitride contact layer is based on a group III element of the first III-nitride contact layer. Based on the determined work functions of the first III-nitride contact layer and of the first metal contact, it is determined that the work function of the first III-nitride contact layer should be adjusted. The III-nitride semiconductor device is formed including the first III-nitride contact layer adjacent to a second III-nitride contact layer, the first metal contact arranged on the first III-nitride contact layer, and a second metal contact arranged on the second III-nitride contact layer. The first III-nitride contact layer of the formed III-nitride semiconductor device is a boron nitride alloy having an amount of boron that adjusts the work function of the first III-nitride contact layer relative to the determined work function of the first metal layer based on the group III element of the first III-nitride contact layer.

A method includes forming a dummy gate stack over a semiconductor region, forming a source / drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, with the semiconductor region being exposed to the trench, forming a gate dielectric layer extending into the trench, and depositing a work-function tuning layer on the gate dielectric layer. The work-function tuning layer comprises aluminum and carbon. The method further includes depositing a p-type work-function layer over the work-function tuning layer, and performing a planarization process to remove excess portions of the p-type work-function layer, the work-function tuning layer, and the gate dielectric layer to form a gate stack.

The application provides a semiconductor device manufacturing method, which is applied to the technical field of semiconductor technology.The application comprises the following steps: providing a substrate with first conductive type doping ions, forming a deep trench in the substrate, forming a doping region with second conductive type doping ions in the part of the substrate below the deep trench, and forming a metal silicide layer at the bottom of the deep trench; thus, by combining the formation of the metal silicide layer at the bottom of the deep trench and the formation of the doping region in the part of the substrate below the deep trench, the characteristics of forming ohmic contact by the close work function of the metal silicide layer and the conductive layer can be achieved, the conduction between the conductive layer and the metal silicide layer can be realized, the carrier concentration in the substrate can be improved by the doping region, the characteristics of forming ohmic contact between the substrate with the improved carrier concentration and the metal silicide layer can be achieved, the conduction between the metal silicide layer and the substrate can be realized, and the same type or also type conduction between the conductive layer and the substrate can be realized.