190 results about "EEPROM" patented technology

The invention relates to the technical field of embedded data storage, and discloses a method and a system for prolonging the service life of a FLASH simulation EEPROM (Electrically Erasable Programmable Read-Only Memory) in a single chip microcomputer, and the method comprises the following steps: firstly, initializing the FLASH, dividing the FLASH into a main data area, a mapping table area, a backup area and a transaction log area, selecting a physical block through a dynamic wear leveling algorithm when data is written, and writing the data into a database; the method comprises the following steps of: starting a backup area or a transaction log area, safely updating a mapping table by using a transaction mechanism, performing cyclic redundancy check when reading data, if the cyclic redundancy check fails, starting cascade recovery from the backup area or the transaction log area, and finally, updating a transaction log to record operation so as to form a closed-loop management process. According to the invention, through a set of dynamic wear leveling and data classification management mechanism, global and uniform distribution of the write load in the storage array is realized, the physical block with the least erasing times is selected during writing, the access frequency of the data can be identified, and cold data which is not changed frequently can be actively migrated.

The invention provides an EEPROM (Electrically Erasable Programmable Read-Only Memory) data read-write method and device based on a real-time industrial Ethernet and a medium. The method comprises the following steps: setting an initial offset and an access length of EEPROM access on a target slave station according to EEPROM capacity parameters, and establishing a paging transaction; when the paging transaction is of a reading type, sequentially triggering EEPROM control registers of the target slave station, reading EEPROM data to a buffer area of the master station according to pages from the initial offset, and executing cyclic redundancy check on each page of read data; when the paging transaction is of a write-in type, reading a to-be-written data file into a buffer area of the master station, writing the to-be-written data file into an EEPROM (Electrically Erasable Programmable Read-Only Memory) of a target slave station according to a page sequence from initial offset, and after writing of each page is completed, reading back data of the page and executing cyclic redundancy check; and when all page data of the paging transaction of the reading type or the writing type passes cyclic redundancy check, outputting a transaction completion state to the soft programmable logic controller. According to the method and the device, the technical effects of safely, efficiently and accurately reading and writing the EEPROM on line in batches and ensuring the data consistency can be achieved.

The invention discloses an integrated galvanometer laser projection method and an integrated galvanometer laser control device. The integrated galvanometer laser projection method comprises the steps that 1, a control card stores various data in a classified mode; when an upper computer issues a system parameter instruction, a communication interface is automatically switched according to a communication mode of the upper computer, and instruction data is analyzed and stored in an EEPROM (Electrically Erasable Programmable Read-Only Memory); 2, after the upper computer issues an instruction, the control card cooperatively controls the on-off state of the laser light source and the deflection angle of the laser galvanometer, and the position and the focal length of the lens are adjusted; 3, positioning an instruction according to a target point of the upper computer; the control card cooperatively controls the laser and the galvanometer to coarsely position the center of the target; and performing fine positioning on the center of the target by taking the target point obtained by coarse positioning as an initial reference position. The integrated galvanometer laser control device has the advantages that the environmental adaptability, the control precision and the operation convenience of the integrated galvanometer laser control device are remarkably improved.

The invention relates to a negative pressure quantitative adjustment and fine adjustment system for vacuum sizing of a drip tape production line, and belongs to the field of mechano-electronics. By adopting a mode of combining a mechanical design technology, a microelectronic technology, a communication technology, a pneumatic technology and the like, quantitative adjustment and fine adjustment of the vacuum degree in the vacuum sizing box are realized through independent work or matched and combined work of the air inlet nozzles with different calibers; and the combination mode of the air inlet nozzles stored in the EEPROM storage chip is called according to the production requirements of different pipe diameters and wall thicknesses, so that the production efficiency is effectively improved, and the purposes of accurately determining the diameter and the pipe wall thickness of the drip irrigation belt production line are achieved. The whole system has the advantages of high precision, low cost, convenience in use, high efficiency and the like, and has a wide market prospect.

The invention relates to an SPD hub chip testing method and device, equipment and a storage medium. The method comprises the steps that if it is determined that a to-be-tested SPD hub chip is placed in a replaceable limiting frame of a test seat and communication connection is established with an upper computer, target environment parameters are set, the to-be-tested SPD hub chip is initialized, the upper computer is in communication connection with the test seat, preset test data are written into an EEPROM of the SPD hub chip based on the target environment parameters, then read-back comparison is carried out, and the to-be-tested SPD hub chip is initialized; the static verification data is used for judging the static storage reliability of the to-be-tested SPD hub chip in the current environment, executing continuous read-write operation on the to-be-tested SPD hub chip to obtain a dynamic pressure test data set, and generating a test result of the to-be-tested SPD hub chip based on the static verification data and the dynamic pressure test data set.

The invention provides a data storage method and device, an electric energy meter and a storage medium, and belongs to the technical field of data storage, the method comprises the following steps: circularly executing a data writing operation until a stop instruction is received; wherein the data writing operation comprises the following steps of: writing data to be stored into a current writing address of the EEPROM unit in real time, and updating the accumulated duration of writing and the current writing address; in response to the fact that the accumulated duration is larger than or equal to the first duration, determining data written into the EEPROM unit within the accumulated duration as target data, reading the target data from the EEPROM unit, writing the target data into the Flash unit, and resetting the accumulated duration; and in response to the fact that the current write-in address of the EEPROM unit is the first specified address, initializing the current write-in address of the EEPROM unit into a second specified address. According to the data storage method and device, the electric energy meter and the storage medium provided by the invention, the requirements of the electric energy meter on real-time access efficiency and long-term storage of mass data can be met at the same time.

The invention belongs to the technical field of program updating, and particularly relates to a method for flashing Bootloader software, which comprises the following steps of: judging the validity of an application program by an operation starting manager, judging the validity of a programming mark if the application program is valid, and skipping to the operation of the application program if the programming mark is invalid; flashing the software of the second version of the boot loader and the effective copy mark into the flash area, and resetting the micro-control unit; the application program judges whether the copy effective mark is effective or not, if yes, the software of the second-version boot loader is copied to the position where the software of the first-version boot loader is located, after copying is completed, the copy effective mark is removed, and the software of the second-version boot loader is copied. And starting a memory protection unit preset by the micro-control unit to perform write access protection of all memories except for using the EEPROM, and enabling the application program to wait for other tasks. According to the method, the problem that the brick is damaged due to power failure when the power failure occurs in the process of flashing the Bootloader by running the APP is solved.

The invention discloses a BMS slave control ID modification method for a standard box PACK. A user initiates an ID modification request; the user permission and the ID legality are verified in sequence, and the main control board generates and issues an ID modification instruction after verification is passed; the slave control board verifies an ID modification instruction, returns an acknowledgement ACK, writes a new ID into a main storage area and a backup storage area of an EEPROM (Electrically Erasable Programmable Read-Only Memory) through atomic operation to realize dual-area redundant backup, and after the slave control board completes EEPROM writing, an address filtering register of a local CAN controller is directly updated without restarting to enable the new ID to take effect immediately, so that the reliability of the slave control board is improved. Meanwhile, a heartbeat message carrying the new ID and the module state information is sent to the main control board, so that the main control board synchronously updates the online equipment mapping table; if the slave control board fails to respond or the master control board does not receive the response after timeout, the master control board tries to issue the ID modification instruction again, the test is carried out for 3 times at most, and the interval between every two times is preset time; and if the retry still fails, triggering a system alarm and recording an error log.

The invention discloses an MAC (Media Access Control) address configuration method, which is applied to a Feiteng processor platform, and the Feiteng processor platform comprises a Feiteng processor, an EEPROM (Electrically Erasable Programmable Read-Only Memory) and UEFI firmware. The method comprises the following steps: writing a target MAC address into a specific storage position of an EEPROM; and the UEFI firmware reads the MAC address from the specific storage position of the EEPROM in the DXE stage, and writes the MAC address into the MAC address register of the Feiteng processor network controller. According to the invention, the persistent configuration of the MAC address can be realized.

The invention relates to a frame format online reconstruction system and method based on an FPGA (Field Programmable Gate Array) external memory, belongs to the technical field of carrier rockets, and solves the problems of long development period and code compatibility of single-task software. The system comprises a TOP module, a RESET function module, an MLVDS communication function module, an EEPROM storage function module and a frame format reconstruction function module, the EEPROM storage function module is used for performing write operation on configuration parameters sent by a main module according to function division of a storage space and solidifying the configuration parameters in an EEPROM, and after power-off restart reset is finished, the EEPROM storage function module is used for performing write operation on the configuration parameters sent by the main module. Reading operation is executed on the EEPROM, and read configuration parameters are distributed to a frame format reconstruction module according to functional area division; and the frame format reconstruction function module is used for executing reconstruction logic operation of the frame format. By means of the system, productization and generalization design of multi-task model software is achieved, and the software reuse rate is remarkably increased.

The present invention relates to systems and methods for authenticating industrial automation components. A first component of an industrial automation system includes an electrically erasable programmable read-only memory (EEPROM) storing data identifying the first component. The data identifying the first component is read from the EEPROM by a second component communicatively coupled with the first component to authenticate the first component. The first component lacks a processor and a microcontroller, and does not run firmware.

The latch device includes an RS type latch flip-flop capable of being supplied between a first supply voltage and a second supply voltage which is lower than the first supply voltage and having first and second flip-flop inputs and a flip-flop output connected to the output terminal. A control module positions the latch flip-flop in a set state or in a reset state when the first supply voltage has a first value which is lower than the low voltage then, the latch flip-flop being positioned, confers the high voltage on the first supply voltage and the low voltage on the second supply voltage and outputs and maintains the high voltage or the low voltage on the flip-flop output while avoiding outputting a prohibited logic state at the two flip-flop inputs.

The application discloses an industrial electronic lock, which comprises a front panel, a main body and a back panel; the front panel is provided with a magnet and an input contact; the main body comprises a CPU system, an EEPROM storage chip, a FLASH chip, a relay module, a logic level module and a communication module; the back panel comprises a power module and a function output module; the input contact, the EEPROM storage chip, the FLASH chip, the relay module, the logic level module and the communication module are connected with the CPU system respectively; the relay module, the logic level module and the communication module are connected with the function output module respectively; and the power module provides power supply for the CPU system, the EEPROM storage chip, the FLASH chip, the relay module, the logic level module and the communication module. The application can realize personnel identity identification, permission management and record operation behavior, and ensures the safety of an industrial site.

The utility model discloses a hydrogenation gas pressure monitor which comprises a microcontroller circuit, and the microcontroller circuit is connected with a power supply circuit, an NBIoT wireless communication circuit, an inlet pressure detection circuit, an outlet pressure detection circuit, a FLASH storage circuit, an EEPROM storage circuit and a screen display circuit. The inlet pressure detection circuit and the outlet pressure detection circuit can immediately report abnormal data in front of and behind the gas pipeline valve to the management platform through the NBIoT wireless communication circuit when pressure values in front of and behind the gas pipeline valve are detected and the pressure is abnormal, the management platform is provided with a data model, pipe network states under different pressure conditions can be identified, and the management platform is convenient to use. And issuing different pressure alarm strategies and parameters. And the platform analyzes and predicts the pressure change of the hydrogenation gas in the pipeline so as to optimize the operation and improve the efficiency, and the technical problems of complicated hardware equipment and wiring and low monitoring efficiency of the gas pressure monitor in the prior art are solved.

This invention relates to the field of projection equipment technology, specifically providing a temperature-adaptive color correction system and method for DLP projection equipment. The system includes an optical temperature monitoring module comprising four temperature sensors for temperature monitoring; a main control processing module using a microcontroller as the core processor, comprising four ADC channels for color compensation calculation; and an execution drive module comprising a first subunit (RGB laser driver circuit connected to the microcontroller), a second subunit (multi-zone fan control circuit), and a third subunit (power management circuit) for heat dissipation control. The microcontroller is connected to an EEPROM memory chip via an I²C bus. A heat dissipation structure module includes four axial fans and corresponding air ducts for each fan. Multiple temperature sensors are placed on key optical components such as the RGB laser and DMD chip to monitor the actual operating temperature of each area in real time.

The invention relates to an anti-counterfeiting method and device for bottled liquid. The device is placed in bottled liquid and cannot be taken out on the premise that the bottle is not damaged, the air bag is arranged at one end of the device, the balancing weight is arranged at the other end of the device, the gravity center of the device is lower, and the vertical posture that the air bag is located above the balancing weight is kept below the balancing weight all the time when the device is immersed in the liquid; due to the fact that the buoyancy borne by the device is greatly reduced, the posture of the device becomes toppling, and it is indicated that original liquid is taken out. The gyroscope is used for monitoring the included angle between the central axis of the device and the vertical line of the horizontal plane so as to judge whether the posture is a vertical posture or a toppling posture, and a signal is sent to the processing chip and stored in an EEPROM (Electrically Erasable Programmable Read-Only Memory). When an inquirer scans or quickly shakes the bottle by using functions such as mobile phone NFC (Near Field Communication), the processing chip reads data in the storage unit and notifies the signal generator to send out a corresponding signal according to the data to indicate whether the liquid in the bottle is original or not.

The invention provides a data writing method and device, electronic equipment and a storage medium. The method comprises the steps of determining at least one target page to be written in an EEPROM (Electrically Erasable Programmable Read-Only Memory) of to-be-written data based on the to-be-written data; and when writing is carried out on each target page, determining the number of bytes with differences between existing data stored in target bytes in each target page and the to-be-written data, and when the number of bytes is smaller than 2, writing the bytes with differences based on the to-be-written data, when the byte number is greater than or equal to 2, performing integral writing on the target page; the data writing efficiency can be improved.

The invention relates to the technical field of electric energy meters, and discloses a load state evaluation method and system for an electric energy meter. The method comprises the following steps: acquiring a first current difference value between an MCU1 and an MCU2 in the electric energy meter, a second current difference value between the MCU2 and an MCU3 and an A-phase reference voltage value of the MCU1; executing three-phase correlation prediction to obtain a three-phase load prediction value in the next period; comparing the three-phase load predicted value of the next period with a load switching threshold value, and judging a load state grade identifier; when the power failure detection circuit outputs a target power failure signal, a three-phase processor collaborative switching instruction is generated; after a three-phase processor collaborative switching instruction is received, task execution schemes are created and stored in different priority areas of the EEPROM respectively, and three-phase collaborative differentiated data protection is completed. Compared with a traditional single-phase independent prediction method, the method has the advantages that the load state prediction precision is remarkably improved, and the whole-process three-phase processor cooperative control from data acquisition to power failure protection is realized.

The invention provides a method and a device for outputting single fixed resolution by a VGA (Video Graphics Array) interface of a domestic platform, and belongs to the technical field of circuits. The method comprises the following steps: storing EDID information corresponding to a preset single fixed resolution in an independent EEPROM (Electrically Erasable Programmable Read-Only Memory); the EDID information in the EEPROM is read through an IIC channel of a VGA interface of the processor; configuring a graphics card register according to the EDID information, and outputting a single fixed-resolution VGA video signal corresponding to the EDID information; the display receives and displays the VGA video signal, and only displays the single fixed resolution in a system graphical interface or a terminal command tool. According to the invention, the use requirement of VGA output single fixed resolution is met, and the use safety and reliability are improved.

The application discloses a kind of new battery management systems applied to A00 grade new energy electric vehicle new type, including main control daughter board and MOS daughter board, the MOS daughter board is fixed on assembly support, the main control daughter board is fixed on MOS daughter board by copper stud, the main control daughter board is constituted by AFE chip, MCU module, power module, CAN module, wake-up module, EEPROM module and FLASH module, the MOS daughter board is constituted by charging MOS, discharging MOS, shunt, DCDC pre-charging MOS, DCDC MOS and heating MOS;The application is under the monitoring of high-power management system, the whole vehicle DCDC module continuously outputs 12V low-voltage power supply to central control platform, reduces battery pack cost, integrates the traditional PDU function in battery pack to management system, simultaneously reduces the assembly complexity of battery pack, improves the whole vehicle safety, built-in power battery output short-circuit protection function, can prevent the whole vehicle safety hazard caused by external short circuit.

The invention discloses a multi-port PCIe bridging chip starting architecture supporting dynamic reconfiguration, and belongs to the technical field of integrated circuit design. According to the architecture, the SPI controller module serves as a core, the SPI controller module is driven to communicate with the EEPROM through the APB request conversion module, and automation and reconfiguration of starting configuration are achieved. The main technical scheme is as follows: an SCLK adjustment module dynamically adjusts the SPI communication frequency (1MHz-17.9 MHz) by decoding an EEPROM clock frequency control signal; the loading starting module adaptively identifies the address width of the EEPROM by polling a 1 / 2 / 3 byte address, and starts corresponding PCIe port link training after the loading configuration module completes initialization register configuration; the configuration data modification module supports an SPI standard instruction set, and online updating of EEPROM configuration data is achieved in the system operation process through the processes of write enabling, data writing, read verification and write forbidding. According to the multi-port PCIe bridging chip, the starting efficiency, compatibility and configuration flexibility of the multi-port PCIe bridging chip are remarkably improved.

The invention belongs to the technical field of integrated circuit testing, and particularly discloses a band-gap reference voltage trimming circuit and a band-gap reference circuit. The circuit disclosed by the invention comprises an enabling module, a control module, a counting module, a fusing module and an output module, and the enabling module receives and responds to an enabling input signal and is used for controlling the starting and working states of the whole circuit; the control module receives and responds to the first input signal and the second input signal and is used for controlling the counting module and the fusing module, the counting module counts clock signals of the second input signal and fuses a thin metal wire corresponding to a trimming position in the output module in cooperation with an output signal of the fusing module, and therefore trimming of the reference voltage is achieved. Through combination of fuse trimming and EEPROM trimming, high-precision adjustment of the band-gap reference voltage is achieved, meanwhile, the occupied area of the trimming circuit is reduced, and the reliability of the circuit is improved. The band-gap reference circuit can be widely applied to reference voltage regulation of the band-gap reference circuit.

A handheld wireless microphone body may be connected to an assortment of microphone heads, where minor variations in the frequency response of microphone heads from one to the next are accounted for using compensation filters based on unique calibration data collected as part of the manufacturing process. Multiple reference microphone heads, which may be different make and model, can be used to collect different sets of calibration data specific for each make and model. One or more unique sets of calibration data for each microphone head, or data enabling access to the calibration data, may be embedded into EEPROM on the microphone head.

The present disclosure provides an update in an electrically erasable programmable read only memory (EEPROM). The computer may store the records at respective locations in the memory. The record may accordingly include an identifier and a size for one of the plurality of variables. In response to a software update notification, the computer may retrieve a first map of the variables from the memory, the first map specifying respective locations of the variables in the memory and a respective size of each of the variables and the identifier. The computer may retrieve a second map of the variables from a remote device, the second map specifying a respective second location in the memory and a second size of the respective variable and the identifier. The computer may store the variables to respective second locations in the memory and store the second map in place of the first map.

EEPROM emulation is provided in a phase-change memory of a circuit integrating a microprocessor. A granularity for writing into lines of the phase-change memory is defined according to a size of data packets to be written. A first error correction code calculated by a program executed by said microprocessor is associated with each data packet. Several data packets and their associated first error correction codes are then stored in a same line of the phase-change memory data packet.

The application provides a multifunctional test chip and method based on a PXI architecture, and relates to the technical field of test chips; the chip comprises a bus interface, a functional module group and an address controller; the bus interface interacts with an upper computer through a PXI bus; the functional module group comprises pulse sending, detection, analog quantity acquisition / output, serial communication, a storage controller and a temperature acquisition module, and can realize pulse signal transceiving, analog quantity processing, serial communication, data storage and temperature acquisition; the address controller divides an address space into eight subspaces, and precise control is realized. The control method comprises the steps of initializing an interface circuit, executing pulse sending and detection, analog quantity output and acquisition, EEPROM operation, UART communication and temperature acquisition and the like. The application integrates special modules, replaces traditional FPGA design, improves performance and reliability, reduces resource waste, reduces cost, shortens the development cycle, and is suitable for complex test scenes such as spaceflight measurement and control.

The invention discloses an EEPROM (Electrically Erasable Programmable Read-Only Memory) unit and a using method thereof The unit comprises a first subunit and a second subunit which are complementary, each of the first subunit and the second subunit comprises a substrate, and a first drain electrode, a source electrode and a second drain electrode are spaced from each other and formed on the substrate; a first channel is arranged between the first drain electrode and the source electrode, a first floating gate and a first selection gate are arranged above the first channel, a first control gate is arranged above the first floating gate, a first matching part is arranged in the first floating gate, and the first selection gate is provided with a second matching part matched with the first matching part; an electron migration path is formed between the first floating gate and the first selection gate; when the erasing operation is carried out, the first subunit and the second subunit are set to be in a first state; and when the programming operation is carried out, the first subunit or the second subunit is set to be in the second state, so that the states of the first subunit and the second subunit are different. The EEPROM unit provided by the invention has relatively high reliability.

The invention discloses a log storage method based on a vehicle machine MCU and related equipment, and relates to the technical field of data processing, and the method comprises the steps: responding to a log storage instruction, obtaining multi-source log data, based on a preset heartbeat mechanism, checking the working state of an SOC, the heartbeat mechanism is constructed based on the SOC and the MCU, and if the working state is normal, the multi-source log data is stored in the multi-source log data, and if the working state is normal, the multi-source log data is stored in the multi-source log data; sending the multi-source log data to the SOC, so that the SOC executes a data storage operation; and if the working state is abnormal, storing the multi-source log data in an EEP space of the MCU. Based on the characteristics of high capacity of the SOC and good stability of the MCU, the data is preferentially stored in the SOC, and further, by combining with a heartbeat mechanism, when the SOC works abnormally or is unstable, the storage path is dynamically adjusted, so that all log data can be completely and stably stored.

The application relates to the technical field of vehicles, in particular to a vehicle offline configuration data processing method and device, electronic equipment and a medium, wherein the method comprises the following steps: initializing an EEPROM emulation module; after the initialization of the EEPROM emulation module is completed, offline configuration data saved in the EEPROM emulation module is read, and it is judged whether the offline configuration data meets a first preset check condition; if the offline configuration data does not meet the first preset check condition, the offline configuration data saved in the EEPROM emulation module is re-read until the number of times that the offline configuration data does not meet the first preset check condition reaches a preset number of times, then offline configuration data is read from a preset SOC end, so that the vehicle function is adapted according to the offline configuration data after the offline configuration data is checked; otherwise, the vehicle function is directly adapted according to the offline configuration data. Thus, the problem of abnormal offline configuration data is solved.

The utility model discloses an optical modem rod which comprises an ONU chip, an optical chip, an optical assembly and a golden finger, the ONU chip is respectively connected with the optical chip and the golden finger, the optical assembly is connected with the optical chip, and the optical assembly comprises an optical transmitting assembly and an optical receiving assembly. According to the optical modem rod, the MAC address is written into the EEPROM of the optical chip, large-scale operation of production personnel is facilitated, and the anti-shoveling plate technology is formed by using the fixed first three bytes of the MAC address of a manufacturer.