2 results about "Sequential access" patented technology

A multiplexed stacked memory device comprises a base die and memory stack comprising one or more memory dies supporting a set of memory banks. The memory banks are organized into bank groups each internally accessed via separate internal data buses. The internal data buses may operate as different internal pseudochannels of a set of internal channels. The base die includes bus aggregation logic to switch data between an external data bus and multiple internal data buses, thereby enabling access to multiple bank groups via the single external data bus. The memory device may be configurable between a sequential access mode to enable sequential access on the external data bus to data on the multiplexed internal data buses and an interleaved access mode that enables interleaved access between the external data bus and the multiplexed internal data buses.

The application discloses a method, system, medium and equipment for optimizing SSD pre-reading, and relates to the technical field of storage. The method comprises the following steps: receiving and judging a host command, and adding the host command to a pre-reading queue for scheduling; when entering a scheduling stage for the first time, initializing and filling a pre-reading buffer based on an LBA address carried by a read command triggering a pre-reading mechanism; after the filling is completed, if the LBA address of a read command subsequently sent by a host belongs to an effective address range covered by the pre-reading buffer, extracting corresponding data from the pre-reading buffer by a SSD controller; and if the LBA address of the host command does not belong to the effective address range covered by the pre-reading buffer, judging that a current sequential access mode has been interrupted, and actively exiting a pre-reading state. The application significantly improves the utilization efficiency of a SSD cache space, eliminates redundant data copying, and reduces delay; meanwhile, the robustness to concurrent and out-of-order I / O is enhanced, and the stability of sequential read performance is improved.