9 results about "Sequential access" patented technology

A multiplexed stacked memory device comprises a base die and memory stack comprising one or more memory dies supporting a set of memory banks. The memory banks are organized into bank groups each internally accessed via separate internal data buses. The internal data buses may operate as different internal pseudochannels of a set of internal channels. The base die includes bus aggregation logic to switch data between an external data bus and multiple internal data buses, thereby enabling access to multiple bank groups via the single external data bus. The memory device may be configurable between a sequential access mode to enable sequential access on the external data bus to data on the multiplexed internal data buses and an interleaved access mode that enables interleaved access between the external data bus and the multiplexed internal data buses.

One aspect of the invention relates to a memory access method in a computer network included in an aircraft, the computer network comprising at least a first and a second device, the method comprising: Issuance of at least one sequential access request, by the first device, to a memory of the second device via a serial bus, the sequential access request comprising a plurality of contiguous memory addresses, Reception, by an address conversion module included in the network and connected to the first device by the serial bus, of the sequential access request, For each address of the plurality of contiguous memory addresses, conversion, by the address conversion module of the network, of the address into a converted address from predefined descriptors, Issuance, by the address conversion module of the network, of an access request to the memory of the second device, each access request comprising at least one converted memory address.Figure to be published with the abbreviation: Figure 3.

The embodiment of the invention provides a data full-amount verification method, device and equipment and a computer program product, a data synchronization method is applied to a distributed storage system, and the distributed storage system comprises a plurality of task nodes used for verifying an original data table; the method comprises the steps of obtaining a to-be-verified data sub-table in each task node, wherein the data sub-table is a part of an original data table; a verification mapping table corresponding to the original data table is determined, the verification mapping table comprises the mapping relation between the metadata file and the data fragments, and the data access sequence corresponding to the verification mapping table is the same as the data access sequence corresponding to the original data table; and based on the verification mapping table, performing full-amount verification on the data sub-table in each task node to obtain a verification result. In the embodiment of the invention, the full-quantity verification operation of the data can be realized by carrying out a large number of sequential access operations on the metadata, so that the time required by the data verification operation is effectively shortened.

Recent advances in logic schemes and fabrication processes have renewed interest in using superconductor electronics for energy-efficient computing and quantum control processors. However, scalable superconducting memory still poses a challenge. To address this issue, this disclosure presents an alternative to approaches that solely emphasize storage cell miniaturization by exploiting the minimal attenuation and dispersion properties of superconducting transmission lines to develop a delay-line memory system. The fully superconducting design is operable at frequencies ranging from approximately 20 GHz to 100 GHz and achieves data densities on the order of tens to thousands of megabits per square centimeter. Additionally, the circulating nature of this design allows for minimal control circuitry, eliminates the need for data splitting and merging, and enables inexpensive implementations of sequential access and content-addressable memories.

The application discloses a method and device for identifying sequential access intervals and a medium, and is applied to the field of data storage. After a storage system obtains a storage interval corresponding to a read request in a block device, the sequential access interval and the storage interval corresponding to the read request are compared. If there is no intersection between the current sequential access interval and the storage interval corresponding to the read request, a new sequential access interval is established according to the storage interval corresponding to the read request to pre-read data in the new sequential access interval. If there is an intersection between the current sequential access interval and the storage interval corresponding to the read request, the corresponding sequential access interval is sequentially slid to pre-read data in the sequential access interval after the sliding. The sequential access interval is a storage interval in the block device. When there is a mixed service scenario of random reading and sequential reading, the sequential access interval is slid to pre-read the sequential reading related data, and the sequential reading is not affected by the random reading.

The invention discloses a dynamic pre-reading method for massive small directories in portable flash memory equipment, and belongs to the technical field of storage management of computer operating systems. Aiming at the problems of excessive invalid I / O (Input / Output) and overlong traversal time consumption caused by scattered storage of directory entries and preread aggressive of the portable flash memory equipment in a scene of traversing massive small directories, the invention provides a dynamic preread method, and by maintaining a preread prompt structure in a memory, when a directory entry read request is processed, the read request of the directory entries is processed, and the read request of the directory entries is read. Judging whether the current access sector and the historical record meet a continuity condition or not; if the continuity is satisfied, dynamically increasing the size of the pre-reading window to reward the sequential access; and if the access is not satisfied or the access is the first time, dynamically reducing the pre-reading window. According to the method, on the premise of not changing the disk layout of the file system, by optimizing the pre-reading strategy in the memory, invalid I / O operation is reduced, the traversal efficiency of massive small directories is improved by several times, and meanwhile, the sequential reading performance of large directories is considered.

During a command bus training (CBT), interconnected memory dice are accessed in a sequence determined (e.g., predetermined) by a bit sequence generator and via a shared data link for retrieving a respective set of feedback data of the CBT from each memory dice. This eliminates a need to individually train and / or control interconnected memory dice for the CBT; thereby, providing a flexible and scalable architecture that can accommodate a range of memory densities (e.g., a number of memory dice that are interconnected) and making it a valuable solution for high-performance memory applications.

The invention relates to the technical field of network security, and discloses an SHA-2 algorithm acceleration method and system based on an RISC-V platform, and the method comprises the steps: compiling a compression function of an SHA-2 algorithm through an RISC-V assembly instruction set; performing data stream recombination and sliding window register mapping on a message expansion process of the SHA-2 algorithm, and mapping sequential access to a plurality of word arrays on the algorithm into cyclic coverage access to a plurality of registers or memory units; performing complete expansion on multiple rounds of iteration loops in the compression function, and statically and sequentially arranging calculation of each round of iteration; operation optimization of RISC-V instruction characteristics is carried out on the SHA-2 algorithm; and adjusting the calculation sequence in the sub-function and the lifetime of the intermediate result to reduce the number of temporary registers. According to the method, the compression function in the SHA-2 algorithm is optimized by using the RISC-V assembly instruction set, so that the operation efficiency is remarkably improved, the processing speed and performance are improved, and the optimization effect range is expanded; the memory access frequency is reduced, and the calculation efficiency is improved.

The application discloses a method, system, medium and equipment for optimizing SSD pre-reading, and relates to the technical field of storage. The method comprises the following steps: receiving and judging a host command, and adding the host command to a pre-reading queue for scheduling; when entering a scheduling stage for the first time, initializing and filling a pre-reading buffer based on an LBA address carried by a read command triggering a pre-reading mechanism; after the filling is completed, if the LBA address of a read command subsequently sent by a host belongs to an effective address range covered by the pre-reading buffer, extracting corresponding data from the pre-reading buffer by a SSD controller; and if the LBA address of the host command does not belong to the effective address range covered by the pre-reading buffer, judging that a current sequential access mode has been interrupted, and actively exiting a pre-reading state. The application significantly improves the utilization efficiency of a SSD cache space, eliminates redundant data copying, and reduces delay; meanwhile, the robustness to concurrent and out-of-order I / O is enhanced, and the stability of sequential read performance is improved.